/**
**===========================================================================
**
** Abstract: main program
**
**===========================================================================
*/
int main(void)
{
int i = 0;
unsigned int ledState=0x1000;
unsigned int portState;
/**
* IMPORTANT NOTE!
* The symbol VECT_TAB_SRAM needs to be defined when building the project
* if code has been located to RAM and interrupts are used.
* Otherwise the interrupt table located in flash will be used.
* See also the <system_*.c> file and how the SystemInit() function updates
* SCB->VTOR register.
* E.g. SCB->VTOR = 0x20000000;
*/
GPIO_Config();
GPIO_ResetBits(GPIOD, GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15);
/* Infinite loop */
while (1)
{
if (GPIO_ReadInputDataBit(GPIOA, GPIO_Pin_0)) {
portState=GPIO_ReadOutputData(GPIOD);
portState&=0x0FFF;
GPIO_Write(GPIOD, portState | ledState);
ledState=ledState<<1;
if (ledState>0x8000)
ledState=0x1000;
for(i=0; i<200000; i++) __NOP();
}
}
}
void
WAKEUP_IRQHandlerPIO0_8 (void)
{
if (LPC_SYSCON->MAINCLKSEL != MAINCLKSEL_SYSPLL_OUT)
{
/* switch to IRC oscillator */
LPC_SYSCON->MAINCLKSEL = MAINCLKSEL_SYSPLL_OUT;
/* push clock change */
LPC_SYSCON->MAINCLKUEN = 0;
LPC_SYSCON->MAINCLKUEN = 1;
/* wait for clock change to be finished */
while (!(LPC_SYSCON->MAINCLKUEN & 1));
/* power down watchdog oscillator */
LPC_SYSCON->PDRUNCFG |= WDTOSC_PD;
}
/* re-trigger match output */
LPC_TMR16B0->EMR &= ~1;
/* reset wakeup logic */
LPC_SYSCON->STARTRSRP0CLR = STARTxPRP0_PIO0_8;
/* disable deep sleep */
SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
/* enable previous clock settings */
LPC_SYSCON->SYSAHBCLKCTRL = g_sysahbclkctrl;
/* select MISO function for PIO0_8 */
LPC_IOCON->PIO0_8 = 1;
/* vodoo -NOP */
__NOP ();
}
static void lcd_delay(unsigned long j)
{
while(j--)
{
__NOP();
}
}
//******************************************************************************
int main(void)
{
/*!< At this stage the microcontroller clock setting is already configured,
this is done through SystemInit() function which is called from startup
file (startup_stm32f4xx.s) before to branch to application main.
To reconfigure the default setting of SystemInit() function, refer to
system_stm32f4xx.c file
*/
uint32_t i = 0;
uint32_t j = 0;
STM_EVAL_LEDInit(LED_BLUE);
STM_EVAL_LEDInit(LED_GREEN);
STM_EVAL_LEDInit(LED_ORANGE);
STM_EVAL_LEDInit(LED_RED);
UART_Configuration();
while(1) /* Infinite loop */
{
STM_EVAL_LEDToggle(LED_BLUE);
STM_EVAL_LEDToggle(LED_GREEN);
STM_EVAL_LEDToggle(LED_ORANGE);
STM_EVAL_LEDToggle(LED_RED);
for(i=0;i<0x00FFFFFF;++i){__NOP();};
printf("j = %i\n",j++);
}
}
void prvGetRegistersFromStack2( uint32_t *pulFaultStackAddress )
{
/* These are volatile to try and prevent the compiler/linker optimising them
away as the variables never actually get used. If the debugger won't show the
values of the variables, make them global my moving their declaration outside
of this function. */
volatile uint32_t r0;
volatile uint32_t r1;
volatile uint32_t r2;
volatile uint32_t r3;
volatile uint32_t r12;
volatile uint32_t lr; /* Link register. */
volatile uint32_t pc; /* Program counter. */
volatile uint32_t psr;/* Program status register. */
r0 = pulFaultStackAddress[ 0 ];
r1 = pulFaultStackAddress[ 1 ];
r2 = pulFaultStackAddress[ 2 ];
r3 = pulFaultStackAddress[ 3 ];
r12 = pulFaultStackAddress[ 4 ];
lr = pulFaultStackAddress[ 5 ];
pc = pulFaultStackAddress[ 6 ];
psr = pulFaultStackAddress[ 7 ];
/* When the following line is hit, the variables contain the register values. */
dbg_printf(DBGMODE_ERR, "\r\n WDG Handler (%d)\r\n", systick_1ms_cnt);
dbg_printf(DBGMODE_ERR, "r0: 0x%08X, r1: 0x%08X, r2: 0x%08X, r3: 0x%08X,", r0, r1, r2, r3);
dbg_printf(DBGMODE_ERR, " r12: 0x%08X\r\nLR: 0x%08X, PC: 0x%08X, PSR: 0x%08X, \r\n", r12, lr, pc, psr);
volatile int cntdn = 0x7FFFFF;
while (cntdn--) __NOP();
NVIC_SystemReset();
while (1);
}
void ms_delay(volatile int ms) {
while (ms-- > 0) {
volatile int x=7000;
while (x-- > 0)
__NOP();
}
}
/*----------------------------------------------------------------------------
set HSI as SystemCoreClock (HSE is not populated on STM32L-Discovery board)
*----------------------------------------------------------------------------*/
void SystemCoreClockSetHSI(void) {
RCC->CR |= ((uint32_t)RCC_CR_HSION); /* Enable HSI */
while ((RCC->CR & RCC_CR_HSIRDY) == 0); /* Wait for HSI Ready */
RCC->CFGR = RCC_CFGR_SW_HSI; /* HSI is system clock */
while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI); /* Wait for HSI used as system clock */
FLASH->ACR = FLASH_ACR_PRFTBE; /* Enable Prefetch Buffer */
FLASH->ACR |= FLASH_ACR_LATENCY; /* Flash 1 wait state */
RCC->CFGR |= RCC_CFGR_HPRE_DIV1; /* HCLK = SYSCLK */
RCC->CFGR |= RCC_CFGR_PPRE_DIV1; /* PCLK = HCLK */
RCC->CR &= ~RCC_CR_PLLON; /* Disable PLL */
/* PLL configuration: = HSI * 12 = 48 MHz */
RCC->CFGR &= ~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL);
RCC->CFGR |= (RCC_CFGR_PLLSRC_HSI_Div2 | RCC_CFGR_PLLMULL12);
RCC->CR |= RCC_CR_PLLON; /* Enable PLL */
while((RCC->CR & RCC_CR_PLLRDY) == 0) __NOP(); /* Wait till PLL is ready */
RCC->CFGR &= ~RCC_CFGR_SW; /* Select PLL as system clock source */
RCC->CFGR |= RCC_CFGR_SW_PLL;
while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL); /* Wait till PLL is system clock src */
}
void SER_Init3 (void) {
#ifdef __DBG_ITM
ITM_RxBuffer = ITM_RXBUFFER_EMPTY;
#else
int i;
RCC->APB1ENR |= ( 1 << 18); /* Enable USART3 clock */
RCC->AHB1ENR |= ( 1 << 2); /* Enable GPIOC clock */
GPIOC->MODER &= ~( 3 << 20);
GPIOC->MODER |= ( 2 << 20); /* PC10: Alternate function mode */
GPIOC->AFR[1] &= ~(0x0F << 8);
GPIOC->AFR[1] |= ( 7 << 8); /* PC10: Alternate function USART3_TX */
GPIOC->MODER &= ~( 3 << 22);
GPIOC->MODER |= ( 2 << 22); /* PC11: Alternate function mode */
GPIOC->AFR[1] &= ~(0x0F << 12);
GPIOC->AFR[1] |= ( 7 << 12); /* PC11: Alternate function USART3_RX */
/* Configure UART3 for 57600 baud*/
USART3->BRR = 0x016c; /* Configure 57600 baud, @ 42MHz */
USART3->CR3 = 0x0000; /* 8 bit, 1 stop bit, */
USART3->CR2 = 0x0000; /* no parity */
for (i = 0; i < 0x1000; i++) __NOP(); /* avoid unwanted output */
USART3->CR1 = 0x200C;
#endif
}
/**
* \brief Enable Wait Mode. Enter condition: (WAITMODE bit = 1) + FLPM
*
* \note In this function, FLPM will retain, WAITMODE bit will be set,
* Generally, this function will be called by pmc_sleep() in order to
* complete all sequence entering wait mode.
* See \ref pmc_sleep() for entering different sleep modes.
*/
void pmc_enable_waitmode(void)
{
uint32_t i;
/* Flash in wait mode */
i = PMC->PMC_FSMR;
i &= ~PMC_FSMR_FLPM_Msk;
i |= ul_flash_in_wait_mode;
PMC->PMC_FSMR = i;
/* Set the WAITMODE bit = 1 */
PMC->CKGR_MOR |= CKGR_MOR_KEY_PASSWD | CKGR_MOR_WAITMODE;
/* Waiting for Master Clock Ready MCKRDY = 1 */
while (!(PMC->PMC_SR & PMC_SR_MCKRDY));
/* Waiting for MOSCRCEN bit cleared is strongly recommended
* to ensure that the core will not execute undesired instructions
*/
for (i = 0; i < 500; i++) {
__NOP();
}
while (!(PMC->CKGR_MOR & CKGR_MOR_MOSCRCEN));
#if (!SAMG)
/* Restore Flash in idle mode */
i = PMC->PMC_FSMR;
i &= ~PMC_FSMR_FLPM_Msk;
i |= PMC_WAIT_MODE_FLASH_IDLE;
PMC->PMC_FSMR = i;
#endif
}
static void SLCD_TimeDelay(uint32_t count)
{
while (count--)
{
__NOP();
}
}
void delay(uint32_t ms)
{
ms *= 3360;
while(ms--) {
__NOP();
}
}
/* Initialises and switches to the external XTAL */
void InitExternalOscillator(void) {
/* Power up the System Oscillator */
LPC_SYSCON->PDRUNCFG &= ~0x0020;
/* Set the appropriate frequency range */
#if __XTAL < 20000000
LPC_SYSCON->SYSOSCCTRL = 0x0;
#else
LPC_SYSCON->SYSOSCCTRL = 0x2;
#endif
/* Wait about 16µS */
for (uint32_t i = 0; i < 200; i++) { __NOP(); }
/* Select the System Oscillator as the PLL Input Source */
LPC_SYSCON->SYSPLLCLKSEL = 0x1;
/* And toggle to update */
LPC_SYSCON->SYSPLLCLKUEN = 0x0;
LPC_SYSCON->SYSPLLCLKUEN = 0x1;
while (!(LPC_SYSCON->SYSPLLCLKUEN & 0x1));
/* Select the PLL Input as the Main Clock source */
LPC_SYSCON->MAINCLKSEL = 0x1;
/* And toggle to update */
LPC_SYSCON->MAINCLKUEN = 0x0;
LPC_SYSCON->MAINCLKUEN = 0x1;
while(!(LPC_SYSCON->MAINCLKUEN & 0x1));
}
/**
* @brief Reset the RCC clock configuration to the default reset state.
* @note The default reset state of the clock configuration is given below:
* - MSI ON and used as system clock source
* - HSE, HSI, PLL and PLLSAIxSource OFF
* - AHB, APB1 and APB2 prescaler set to 1.
* - CSS, MCO OFF
* - All interrupts disabled
* @note This function doesn't modify the configuration of the
* - Peripheral clocks
* - LSI, LSE and RTC clocks
* @retval An ErrorStatus enumeration value:
* - SUCCESS: RCC registers are de-initialized
* - ERROR: not applicable
*/
ErrorStatus LL_RCC_DeInit(void)
{
uint32_t vl_mask = 0;
/* Set MSION bit */
LL_RCC_MSI_Enable();
/* Insure MSIRDY bit is set before writing default MSIRANGE value */
while (LL_RCC_MSI_IsReady() == 0)
{
__NOP();
}
/* Set MSIRANGE default value */
LL_RCC_MSI_SetRange(LL_RCC_MSIRANGE_6);
/* Set MSITRIM bits to the reset value*/
LL_RCC_MSI_SetCalibTrimming(0);
/* Set HSITRIM bits to the reset value*/
LL_RCC_HSI_SetCalibTrimming(0x10);
/* Reset CFGR register */
LL_RCC_WriteReg(CFGR, 0x00000000);
vl_mask = 0xFFFFFFFFU;
/* Reset HSION, HSIKERON, HSIASFS, HSEON, PLLSYSON bits */
CLEAR_BIT(vl_mask, (RCC_CR_HSION | RCC_CR_HSIASFS | RCC_CR_HSIKERON | RCC_CR_HSEON |
RCC_CR_PLLON));
/* Reset PLLSAI1ON bit */
CLEAR_BIT(vl_mask, RCC_CR_PLLSAI1ON);
#if defined(RCC_PLLSAI2_SUPPORT)
/* Reset PLLSAI2ON bit */
CLEAR_BIT(vl_mask, RCC_CR_PLLSAI2ON);
#endif /*RCC_PLLSAI2_SUPPORT*/
/* Write new mask in CR register */
LL_RCC_WriteReg(CR, vl_mask);
/* Reset PLLCFGR register */
LL_RCC_WriteReg(PLLCFGR, 16 << RCC_POSITION_PLLN);
/* Reset PLLSAI1CFGR register */
LL_RCC_WriteReg(PLLSAI1CFGR, 16 << RCC_POSITION_PLLSAI1N);
#if defined(RCC_PLLSAI2_SUPPORT)
/* Reset PLLSAI2CFGR register */
LL_RCC_WriteReg(PLLSAI2CFGR, 16 << RCC_POSITION_PLLSAI2N);
#endif /*RCC_PLLSAI2_SUPPORT*/
/* Reset HSEBYP bit */
LL_RCC_HSE_DisableBypass();
/* Disable all interrupts */
LL_RCC_WriteReg(CIER, 0x00000000);
return SUCCESS;
}
void OpenLock(u8 LockId, u8 Numer)
{
u8 u8Remainder = LockId % 8;
u8 u8Quotient = LockId / 8;
u8 u8loop = Numer / 8;
u8 i;
if (LockId == 0xff)
{
u8Quotient = 0xff;
}
for(i = u8loop; i > 0; i--)
{
/* 第33 - 39、 41 - 47 路由于PCB布线问题，需要作以下调整。*/
/* 32 33 34 35 36 37 38 39 */
/* 32 39 38 37 36 35 34 33 */ //-- 实际被控制的线路
/* 40 41 42 43 44 45 46 47 */
/* 40 47 46 45 44 43 42 41 */ //-- 实际被控制的线路
if (i == u8Quotient+1)
{
if (u8Quotient+1 == 5 || u8Quotient+1 == 6)
{
if (u8Remainder != 0)
{
u8Remainder = 8 - u8Remainder;
}
}
SPIByte(1<<u8Remainder);
}
else
{
SPIByte(0);
}
}
__NOP();
GPIO_SetBits(GPIOB,GPIO_Pin_11);
// for(i = 0;i<1000;i++)
{
__NOP();
}
GPIO_ResetBits(GPIOB,GPIO_Pin_11);
}
/*..........................................................................*/
void BSP_init(void) {
/* NOTE: SystemInit() already called from startup_TM4C123GH6PM.s
* but SystemCoreClock needs to be updated
*/
SystemCoreClockUpdate();
SYSCTL->RCGC2 |= (1 << 5); /* enable clock to GPIOF (User and Eth LEDs)*/
__NOP();
__NOP();
/* configure the pin driving the Ethernet LED */
GPIOF->DIR &= ~(ETH0_LED | ETH1_LED); /* set direction: hardware */
GPIOF->AFSEL |= (ETH0_LED | ETH1_LED);
GPIOF->DR2R |= (ETH0_LED | ETH1_LED);
GPIOF->ODR &= ~(ETH0_LED | ETH1_LED);
GPIOF->PUR |= (ETH0_LED | ETH1_LED);
GPIOF->PDR &= ~(ETH0_LED | ETH1_LED);
GPIOF->DEN |= (ETH0_LED | ETH1_LED);
GPIOF->AMSEL &= ~(ETH0_LED | ETH1_LED);
/* configure the pin driving the User LED */
GPIOF->DIR |= USER_LED; /* set direction: output */
GPIOF->DR2R |= USER_LED;
GPIOF->DEN |= USER_LED;
GPIOF->AMSEL &= ~USER_LED;
GPIOF->DATA_Bits[USER_LED] = 0; /* turn the LED off */
/* configure the pin connected to the Buttons */
GPIOF->DIR &= ~USER_BTN; /* set direction: input */
GPIOF->DR2R |= USER_BTN;
GPIOF->ODR &= ~USER_BTN;
GPIOF->PUR |= USER_BTN;
GPIOF->PDR &= ~USER_BTN;
GPIOF->DEN |= USER_BTN;
GPIOF->AMSEL &= ~USER_BTN;
/* NOTE:
* The OLED display is encapsulated inside the Table AO, so the
* initialization of the OLED display happens in the top-most initial
* transition of the Table AO (see Table_displayInit()).
*/
if (QS_INIT((void *)0) == 0) { /* initialize the QS software tracing */
Q_ERROR();
}
QS_OBJ_DICTIONARY(&l_SysTick_Handler);
}
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System.
*/
void SystemInit (void)
{
#if CORTEX_VECTORS_RAM
// Then assume need to map vectors to RAM
LPC_SYSCON->SYSMEMREMAP = ((LPC_SYSCON->SYSMEMREMAP)& ~3) | 1;
#else
// LPC_SYSCON->SYSMEMREMAP |= 3; // Map to flash
#endif
#if (CLOCK_SETUP) /* Clock Setup */
#if (SYSCLK_SETUP) /* System Clock Setup */
#if (SYSOSC_SETUP) /* System Oscillator Setup */
uint32_t i;
LPC_SYSCON->PDRUNCFG &= ~(1 << 5); /* Power-up System Osc */
LPC_SYSCON->SYSOSCCTRL = SYSOSCCTRL_Val;
for (i = 0; i < 200; i++) __NOP();
LPC_SYSCON->SYSPLLCLKSEL = SYSPLLCLKSEL_Val; /* Select PLL Input */
LPC_SYSCON->SYSPLLCLKUEN = 0x01; /* Update Clock Source */
LPC_SYSCON->SYSPLLCLKUEN = 0x00; /* Toggle Update Register */
LPC_SYSCON->SYSPLLCLKUEN = 0x01;
while (!(LPC_SYSCON->SYSPLLCLKUEN & 0x01)); /* Wait Until Updated */
#if (SYSPLL_SETUP) /* System PLL Setup */
LPC_SYSCON->SYSPLLCTRL = SYSPLLCTRL_Val;
LPC_SYSCON->PDRUNCFG &= ~(1 << 7); /* Power-up SYSPLL */
while (!(LPC_SYSCON->SYSPLLSTAT & 0x01)); /* Wait Until PLL Locked */
#endif
#endif
#if (WDTOSC_SETUP) /* Watchdog Oscillator Setup*/
LPC_SYSCON->WDTOSCCTRL = WDTOSCCTRL_Val;
LPC_SYSCON->PDRUNCFG &= ~(1 << 6); /* Power-up WDT Clock */
#endif
LPC_SYSCON->MAINCLKSEL = MAINCLKSEL_Val; /* Select PLL Clock Output */
LPC_SYSCON->MAINCLKUEN = 0x01; /* Update MCLK Clock Source */
LPC_SYSCON->MAINCLKUEN = 0x00; /* Toggle Update Register */
LPC_SYSCON->MAINCLKUEN = 0x01;
while (!(LPC_SYSCON->MAINCLKUEN & 0x01)); /* Wait Until Updated */
#endif
LPC_SYSCON->SYSAHBCLKDIV = SYSAHBCLKDIV_Val;
LPC_SYSCON->SYSAHBCLKCTRL = AHBCLKCTRL_Val;
LPC_SYSCON->SSP0CLKDIV = SSP0CLKDIV_Val;
LPC_SYSCON->UARTCLKDIV = UARTCLKDIV_Val;
LPC_SYSCON->SSP1CLKDIV = SSP1CLKDIV_Val;
#endif
#if __SYSTEM_CLOCK < 20000000
FLASHCFG = 0;
#elif __SYSTEM_CLOCK < 40000000
FLASHCFG = 1;
#else
FLASHCFG = 2;
#endif
#if (MEMMAP_SETUP || MEMMAP_INIT) /* Memory Mapping Setup */
LPC_SYSCON->SYSMEMREMAP = SYSMEMREMAP_Val;
#endif
//SystemCoreClockUpdate();
}
//------------------------------------------------------------------------------
// Global Functions
void initBasics(void)
{
/* Enable data and instruction cache and prefetch buffer, set wait states
* for Flash memory access.
*/
FLASH->ACR |= FLASH_ACR_DCEN | FLASH_ACR_ICEN | FLASH_ACR_PRFTEN
| FLASH_ACR_LATENCY_1WS;
/* Set 4 bits for group (equal to preemption) priority and 0 bits for
* subpriority. Arbitrary choice. Project dependent.
* Note: use this function provided by core_cm4.h instead of
* NVIC_PriorityGroupConfig() implemented in misc.c of the SPL because
* it's safer: the latter only sets the bits using bitwise OR, the former
* clears the bits first before setting them.
*/
NVIC_SetPriorityGrouping(NVIC_PriorityGroup_4);
/* Select HSI as main oscillator. The HSE oscillator isn't populated on
* the Nucleo board.
*/
RCC->CR |= ((uint32_t)RCC_CR_HSION); // Enable HSI
while ((RCC->CR & RCC_CR_HSIRDY) == 0); // Wait until HSI ready
RCC->CFGR = RCC_CFGR_SW_HSI; // Set HSI as system clock
while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI);
// Wait for HSI used as system clock
/* Configure the HCLK, APB1 and APB2 clock frequency. */
RCC->CFGR |= RCC_CFGR_HPRE_DIV1; // HCLK = SYSCLK
RCC->CFGR |= RCC_CFGR_PPRE1_DIV1; // APB1 = HCLK/1
RCC->CFGR |= RCC_CFGR_PPRE2_DIV1; // APB2 = HCLK/1
/* Configure and enable the PLL. */
RCC->CR &= ~RCC_CR_PLLON; // Disable the PLL
/* PLL configuration: run the CPU at 32MHz;
* f_VCO = f_HSI*(N/M), f_PLL_out = f_VCO/P
*/
RCC->PLLCFGR =
( 16ul | // PLL_M = 16
(192ul << 6) | // PLL_N = 192
( 2ul << 16) | // PLL_P = 6
(RCC_PLLCFGR_PLLSRC_HSI) | // PLL_SRC = HSI
( 4ul << 24) ); // PLL_Q = 4
RCC->CR |= RCC_CR_PLLON; // Enable the PLL
while((RCC->CR & RCC_CR_PLLRDY) == 0) __NOP(); // Wait until PLL ready
/* Select the PLL as system clock source. */
RCC->CFGR &= ~RCC_CFGR_SW;
RCC->CFGR |= RCC_CFGR_SW_PLL;
while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL);
// Wait until PLL is system clock source
/* Update the global SystemCoreClock variable that stores the core
* clock frequency in Hertz.
*/
SystemCoreClockUpdate();
}
/**
* @brief Enables ADC DMA request after last transfer (Single-ADC mode) and enables ADC peripheral
* @param hadc: pointer to a ADC_HandleTypeDef structure that contains
* the configuration information for the specified ADC.
* @param pData: The destination Buffer address.
* @param Length: The length of data to be transferred from ADC peripheral to memory.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
{
uint16_t i = 0;
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
/* Process locked */
__HAL_LOCK(hadc);
/* Enable ADC overrun interrupt */
__HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
/* Enable ADC DMA mode */
hadc->Instance->CR2 |= ADC_CR2_DMA;
/* Set the DMA transfer complete callback */
hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
/* Set the DMA half transfer complete callback */
hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
/* Set the DMA error callback */
hadc->DMA_Handle->XferErrorCallback = ADC_DMAError ;
/* Enable the DMA Stream */
HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
/* Change ADC state */
hadc->State = HAL_ADC_STATE_BUSY_REG;
/* Check if ADC peripheral is disabled in order to enable it and wait during
Tstab time the ADC's stabilization */
if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
{
/* Enable the Peripheral */
__HAL_ADC_ENABLE(hadc);
/* Delay inserted to wait during Tstab time the ADC's stabilazation */
for(; i <= 540; i++)
{
__NOP();
}
}
/* if no external trigger present enable software conversion of regular channels */
if (hadc->Init.ExternalTrigConvEdge == ADC_EXTERNALTRIGCONVEDGE_NONE)
{
/* Enable the selected ADC software conversion for regular group */
hadc->Instance->CR2 |= ADC_CR2_SWSTART;
}
/* Process unlocked */
__HAL_UNLOCK(hadc);
/* Return function status */
return HAL_OK;
}
/**
* @brief delay some time with NOP instruction
* @param count delay time
* @return null
*/
void Delay(UINT32 count)
{
UINT32 i;
for(i = 0; i < count; i++)
{
__NOP();
}
}
static void can_set_global_mode(int mode) {
/* set Global mode */
RSCAN0GCTR = ((RSCAN0GCTR & 0xFFFFFFFC) | mode);
/* Wait to cahnge into Global XXXX mode */
while ((RSCAN0GSTS & 0x07) != mode) {
__NOP();
}
}
void USART_SendChar(unsigned char ch)
{
while ((USART1->ISR & USART_ISR_TXE) == 0)
{
__NOP();
};
USART1->TDR = ch;
}
/*!
* @brief Delay function used to wait FLL stable.
*/
static void APP_FllStableDelay(void)
{
volatile uint32_t i = 30000U;
while (i--)
{
__NOP();
}
}
__NO_RETURN void play_dead( void )
{
osKernelLock( );
while( 1 )
{
__NOP( );
}
}
void Delay(uint32_t ms) { // delay for ms milliseconds
uint32_t s = tick;
while( (tick-s) < ms ) {
__NOP();
}
}
void delay(unsigned int x)
{
while(x!=0)
{
x--;
__NOP();
}
}
/**
* @brief This function handles Hard Fault exception.
* @param None
* @retval None
*/
void HardFault_Handler(void)
{
/* Go to infinite loop when Hard Fault exception occurs */
// while (1)
// {
// }
__NOP();
}
/* NXP_Quick_Jack io initilize detect the mic&gnd */
void QUICKJACK_IO_Init(void)
{
uint32_t MgAcmpOutVal;
uint32_t i = 0;
Chip_GPIO_SetPinDIROutput(LPC_GPIO_PORT, 0, MnGSWENAPINNUM);
Chip_GPIO_SetPinState(LPC_GPIO_PORT, 0, MnGSWENAPINNUM, 1);
Chip_IOCON_PinSetMode(LPC_IOCON, IOCON_PIO14, PIN_MODE_INACTIVE);
Chip_GPIO_SetPinDIRInput(LPC_GPIO_PORT, 0, 14);
Chip_IOCON_PinSetMode(LPC_IOCON, MnGACMPOUTPIN, PIN_MODE_INACTIVE);
Chip_GPIO_SetPinDIRInput(LPC_GPIO_PORT, 0, MnGACMPOUTPINNUM);
MgAcmpOutVal = Chip_GPIO_ReadPortBit(LPC_GPIO_PORT, 0, 6);
for(i=0; i<5; i++) { /* waiting a while */
__NOP();
}
while(MgAcmpOutVal!= Chip_GPIO_ReadPortBit(LPC_GPIO_PORT, 0, 6)) {
for(i=0; i<5; i++) { /* waiting a while */
__NOP();
}
MgAcmpOutVal = Chip_GPIO_ReadPortBit(LPC_GPIO_PORT, 0, 6);
for(i=0; i<5; i++) { /* waiting a while */
__NOP();
}
}
/* configured analog switch selectable pin */
Chip_IOCON_PinSetMode(LPC_IOCON, MnGSWSELPIN, PIN_MODE_INACTIVE);
Chip_GPIO_SetPinDIROutput(LPC_GPIO_PORT, 0, MnGSWSELPINNUM);
if(MgAcmpOutVal==0) {
Chip_GPIO_SetPinState(LPC_GPIO_PORT, 0, MnGSWSELPINNUM, 1);
}
else {
Chip_GPIO_SetPinState(LPC_GPIO_PORT, 0, MnGSWSELPINNUM, 0);
}
/* enabled analog switch enabled pin */
Chip_IOCON_PinSetMode(LPC_IOCON, MnGSWENAPIN, PIN_MODE_INACTIVE);
Chip_GPIO_SetPinDIROutput(LPC_GPIO_PORT, 0, MnGSWENAPINNUM);
Chip_GPIO_SetPinState(LPC_GPIO_PORT, 0, MnGSWENAPINNUM, 0);
}
extern "C" void PIOINT1_IRQHandler(void)
{
U64 systickcnt = SysTickCnt;
if (GPIO1_MIS(0))
{
g_motorPos += g_motorInc;
g_motorTime = systickcnt;
if (g_motorPos == g_motorStop)
{
MotorDir(0, 0); // brake motor
MotorPower(0, 100); // stop the motor
}
GPIO1_IC(0); // clear the interrupt flag
__NOP();__NOP(); // required after clearing interrupt flags
}
}
void DelayUs ( uint32_t usec )
{
uint32_t i;
for (i = (SystemCoreClock / 1000000) * usec; i; i--)
{
__NOP();
}
}
/*FUNCTION**********************************************************************
*
* Function Name : CLOCK_CONFIG_FllStableDelay
* Description : This function is used to delay for FLL stable.
*
*END**************************************************************************/
static void CLOCK_CONFIG_FllStableDelay(void)
{
uint32_t i = 30000U;
while (i--)
{
__NOP();
}
}