int brcm_pm_memc1_suspend(void) { CHECK_MEMC1_INIT(); __brcm_pm_memc1_suspend(0); /* Stop the clocks */ brcm_pm_memc1_clock_stop(); return 0; }
int brcm_pm_memc1_suspend(void) { CHECK_MEMC1_INIT(); brcm_pm_save_restore_rts(BCHP_MEMC_ARB_1_REG_START, memc1_config.client_info, 0); brcm_pm_memc1_ddr_params(0); brcm_pm_memc1_arb_params(0); __brcm_pm_memc1_suspend(0); /* Stop the clocks */ brcm_pm_memc1_clock_stop(); return 0; }
static void __brcm_pm_memc1_powerdown(void) { int ii = 0; memc1_config.ddr23_aphy_params[ii++] = BDEV_RD(BCHP_MEMC_DDR23_APHY_AC_1_PLL_CTRL1_REG); memc1_config.ddr23_aphy_params[ii++] = BDEV_RD(BCHP_MEMC_DDR23_APHY_AC_1_PLL_FREQ_CNTL); memc1_config.ddr23_aphy_params[ii++] = BDEV_RD(BCHP_MEMC_DDR23_APHY_AC_1_CONFIG); memc1_config.ddr23_aphy_params[ii++] = BDEV_RD(BCHP_MEMC_DDR23_APHY_AC_1_PAD_SSTL_DDR2_MODE); memc1_config.ddr23_aphy_params[ii++] = BDEV_RD(BCHP_MEMC_DDR23_APHY_WL1_1_PAD_SSTL_DDR2_MODE); memc1_config.ddr23_aphy_params[ii++] = BDEV_RD(BCHP_MEMC_DDR23_APHY_WL0_1_PAD_SSTL_DDR2_MODE); memc1_config.ddr23_aphy_params[ii++] = BDEV_RD(BCHP_MEMC_DDR23_APHY_AC_1_ODT_CONFIG); BUG_ON(ii > MAX_DDR_APHY_PARAMS_NUM); __brcm_pm_memc1_suspend(1); }
static void __brcm_pm_memc1_powerdown(void) { __brcm_pm_memc1_suspend(1); }