int __cvmx_helper_spi_enable(int interface) { /* * Normally the ethernet L2 CRC is checked and stripped in the * GMX block. When you are using SPI, this isn' the case and * IPD needs to check the L2 CRC. */ int num_ports = cvmx_helper_ports_on_interface(interface); int ipd_port; for (ipd_port = interface * 16; ipd_port < interface * 16 + num_ports; ipd_port++) { union cvmx_pip_prt_cfgx port_config; port_config.u64 = cvmx_read_csr(CVMX_PIP_PRT_CFGX(ipd_port)); port_config.s.crc_en = 1; cvmx_write_csr(CVMX_PIP_PRT_CFGX(ipd_port), port_config.u64); } if (cvmx_sysinfo_get()->board_type != CVMX_BOARD_TYPE_SIM) { cvmx_spi_start_interface(interface, CVMX_SPI_MODE_DUPLEX, CVMX_HELPER_SPI_TIMEOUT, num_ports); if (cvmx_spi4000_is_present(interface)) cvmx_spi4000_initialize(interface); } __cvmx_interrupt_spxx_int_msk_enable(interface); __cvmx_interrupt_stxx_int_msk_enable(interface); __cvmx_interrupt_gmxx_enable(interface); return 0; }
int __cvmx_helper_spi_enable(int interface) { /* */ int num_ports = cvmx_helper_ports_on_interface(interface); int ipd_port; for (ipd_port = interface * 16; ipd_port < interface * 16 + num_ports; ipd_port++) { union cvmx_pip_prt_cfgx port_config; port_config.u64 = cvmx_read_csr(CVMX_PIP_PRT_CFGX(ipd_port)); port_config.s.crc_en = 1; cvmx_write_csr(CVMX_PIP_PRT_CFGX(ipd_port), port_config.u64); } if (cvmx_sysinfo_get()->board_type != CVMX_BOARD_TYPE_SIM) { cvmx_spi_start_interface(interface, CVMX_SPI_MODE_DUPLEX, CVMX_HELPER_SPI_TIMEOUT, num_ports); if (cvmx_spi4000_is_present(interface)) cvmx_spi4000_initialize(interface); } __cvmx_interrupt_spxx_int_msk_enable(interface); __cvmx_interrupt_stxx_int_msk_enable(interface); __cvmx_interrupt_gmxx_enable(interface); return 0; }
/** * Configure all of the ASX, GMX, and PKO regsiters required * to get RGMII to function on the supplied interface. * * @interface: PKO Interface to configure (0 or 1) * * Returns Zero on success */ int __cvmx_helper_rgmii_enable(int interface) { int num_ports = cvmx_helper_ports_on_interface(interface); int port; struct cvmx_sysinfo *sys_info_ptr = cvmx_sysinfo_get(); union cvmx_gmxx_inf_mode mode; union cvmx_asxx_tx_prt_en asx_tx; union cvmx_asxx_rx_prt_en asx_rx; mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface)); if (mode.s.en == 0) return -1; if ((OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)) && mode.s.type == 1) /* Ignore SPI interfaces */ return -1; /* Configure the ASX registers needed to use the RGMII ports */ asx_tx.u64 = 0; asx_tx.s.prt_en = cvmx_build_mask(num_ports); cvmx_write_csr(CVMX_ASXX_TX_PRT_EN(interface), asx_tx.u64); asx_rx.u64 = 0; asx_rx.s.prt_en = cvmx_build_mask(num_ports); cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(interface), asx_rx.u64); /* Configure the GMX registers needed to use the RGMII ports */ for (port = 0; port < num_ports; port++) { /* Setting of CVMX_GMXX_TXX_THRESH has been moved to __cvmx_helper_setup_gmx() */ if (cvmx_octeon_is_pass1()) __cvmx_helper_errata_asx_pass1(interface, port, sys_info_ptr-> cpu_clock_hz); else { /* * Configure more flexible RGMII preamble * checking. Pass 1 doesn't support this * feature. */ union cvmx_gmxx_rxx_frm_ctl frm_ctl; frm_ctl.u64 = cvmx_read_csr(CVMX_GMXX_RXX_FRM_CTL (port, interface)); /* New field, so must be compile time */ frm_ctl.s.pre_free = 1; cvmx_write_csr(CVMX_GMXX_RXX_FRM_CTL(port, interface), frm_ctl.u64); } /* * Each pause frame transmitted will ask for about 10M * bit times before resume. If buffer space comes * available before that time has expired, an XON * pause frame (0 time) will be transmitted to restart * the flow. */ cvmx_write_csr(CVMX_GMXX_TXX_PAUSE_PKT_TIME(port, interface), 20000); cvmx_write_csr(CVMX_GMXX_TXX_PAUSE_PKT_INTERVAL (port, interface), 19000); if (OCTEON_IS_MODEL(OCTEON_CN50XX)) { cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(port, interface), 16); cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(port, interface), 16); } else { cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(port, interface), 24); cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(port, interface), 24); } } __cvmx_helper_setup_gmx(interface, num_ports); /* enable the ports now */ for (port = 0; port < num_ports; port++) { union cvmx_gmxx_prtx_cfg gmx_cfg; cvmx_helper_link_autoconf(cvmx_helper_get_ipd_port (interface, port)); gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(port, interface)); gmx_cfg.s.en = 1; cvmx_write_csr(CVMX_GMXX_PRTX_CFG(port, interface), gmx_cfg.u64); } __cvmx_interrupt_asxx_enable(interface); __cvmx_interrupt_gmxx_enable(interface); return 0; }