static void mt_gpt_set_mode(enum clock_event_mode mode,
struct clock_event_device *evt)
{
struct gpt_device *dev = id_to_dev(GPT_CLKEVT_ID);
//printk("[%s]entry, mode=%d\n", __func__, mode);
switch (mode) {
case CLOCK_EVT_MODE_PERIODIC:
__gpt_stop(dev);
__gpt_set_mode(dev, GPT_REPEAT);
__gpt_enable_irq(dev);
__gpt_start_from_zero(dev);
break;
case CLOCK_EVT_MODE_ONESHOT:
__gpt_stop(dev);
__gpt_set_mode(dev, GPT_ONE_SHOT);
__gpt_enable_irq(dev);
__gpt_start_from_zero(dev);
break;
case CLOCK_EVT_MODE_UNUSED:
case CLOCK_EVT_MODE_SHUTDOWN:
__gpt_stop(dev);
__gpt_disable_irq(dev);
__gpt_ack_irq(dev);
case CLOCK_EVT_MODE_RESUME:
break;
}
}
static void __gpt_reset(struct gpt_device *dev)
{
DRV_WriteReg32(dev->base_addr + GPT_CON, 0x0);
__gpt_disable_irq(dev);
__gpt_ack_irq(dev);
DRV_WriteReg32(dev->base_addr + GPT_CLK, 0x0);
DRV_WriteReg32(dev->base_addr + GPT_CON, 0x2);
DRV_WriteReg32(dev->base_addr + GPT_CMP, 0x0);
if (dev->features & GPT_FEAT_64_BIT) {
DRV_WriteReg32(dev->base_addr + GPT_CMPH, 0);
}
}
static void __gpt_reset(struct gpt_device *dev)
{
mt_reg_sync_writel(0x0, dev->base_addr + GPT_CON);
__gpt_disable_irq(dev);
__gpt_ack_irq(dev);
mt_reg_sync_writel(0x0, dev->base_addr + GPT_CLK);
mt_reg_sync_writel(0x2, dev->base_addr + GPT_CON);
mt_reg_sync_writel(0x0, dev->base_addr + GPT_CMP);
if (dev->features & GPT_FEAT_64_BIT)
mt_reg_sync_writel(0, dev->base_addr + GPT_CMPH);
}
