void crt_init()
{
// коприрование инициализированных данных в ОЗУ (секция .data)
extern uint32_t _data_load_start_ ;
extern uint32_t _data_start_ ;
extern uint32_t _data_end_ ;
volatile uint32_t* data_load = &_data_load_start_ ;
volatile uint32_t* data = &_data_start_ ;
volatile uint32_t* data_end = &_data_end_ ;
while( data < data_end )
{
*(data++) = *(data_load++);
}
// копирование секции .fast в ОЗУ
extern unsigned _fast_load_start_ ;
extern unsigned _fast_start_ ;
extern unsigned _fast_end_ ;
unsigned *fast_load = &_fast_load_start_ ;
unsigned *fast = &_fast_start_ ;
unsigned *fast_end = &_fast_end_ ;
// коприрование кода в ОЗУ (секция .fast)
while(fast < fast_end )
{
*(fast++) = *(fast_load++);
}
// инициализация данных в ОЗУ нулями(секция .bss)
extern unsigned _bss_start_ ;
extern unsigned _bss_end_ ;
unsigned *bss = &_bss_start_ ;
unsigned *bss_end = &_bss_end_ ;
while(bss < bss_end )
{
*(bss++) = 0 ;
}
// инициализация системной библиотеки
extern __attribute__ ((weak)) void __libc_init_array(void);
if (__libc_init_array)
__libc_init_array() ;
}
/**
* \brief This is the code that gets called on processor reset.
* To initialize the device, and call the main() routine.
*/
void Reset_Handler( void )
{
uint32_t *pSrc, *pDest ;
/* Low level Initialize */
LowLevelInit() ;
/* Initialize the relocate segment */
pSrc = &_etext ;
pDest = &_srelocate ;
if ( pSrc != pDest )
{
for ( ; pDest < &_erelocate ; )
{
*pDest++ = *pSrc++ ;
}
}
/* Clear the zero segment */
for ( pDest = &_szero ; pDest < &_ezero ; )
{
*pDest++ = 0;
}
/* Set the vector table base address */
pSrc = (uint32_t *)&_sfixed;
SCB->VTOR = ( (uint32_t)pSrc & SCB_VTOR_TBLOFF_Msk ) ;
if ( ((uint32_t)pSrc >= IRAM_ADDR) && ((uint32_t)pSrc < IRAM_ADDR+IRAM_SIZE) )
{
SCB->VTOR |= 1 << SCB_VTOR_TBLBASE_Pos ;
}
/* Initialize the C library */
__libc_init_array() ;
/* Branch to main function */
main() ;
/* Infinite loop */
while ( 1 ) ;
}
//*****************************************************************************
//
// This is the code that gets called when the processor first starts execution
// following a reset event. Only the absolutely necessary set is performed,
// after which the application supplied entry() routine is called. Any fancy
// actions (such as making decisions based on the reset cause register, and
// resetting the bits in that register) are left solely in the hands of the
// application.
//
//*****************************************************************************
void ResetISR(void)
{
unsigned char *pulSrc, *pulDest;
//
// Copy the data segment initializers from flash to SRAM.
//
pulSrc = (unsigned char *)&_etext;
for(pulDest = (unsigned char *)&_data; pulDest < (unsigned char *)&_edata; )
{
*pulDest++ = *pulSrc++;
}
//
// Zero fill the bss segment.
//
for(pulDest = (unsigned char *)&_bss; pulDest < (unsigned char *)&_ebss; pulDest++)
*pulDest = 0;
#ifdef __USE_CMSIS
SystemInit();
#endif
#if defined (__cplusplus)
//
// Call C++ library initialisation
//
__libc_init_array();
#endif
#if defined (__REDLIB__)
// Call the Redlib library, which in turn calls main()
__main() ;
#else
main();
#endif
//
// main() shouldn't return, but if it does, we'll just enter an infinite loop
//
while (1) {
;
}
}
void _start(void)
{
int bssSize = (int)&__bss_end__ - (int)&__bss_start__;
int mainReturnValue;
memset(&__bss_start__, 0, bssSize);
if (MRI_ENABLE)
{
__mriInit(MRI_INIT_PARAMETERS);
if (MRI_BREAK_ON_INIT)
__debugbreak();
}
software_init_hook();
__libc_init_array();
mainReturnValue = main();
exit(mainReturnValue);
}
/** Startup the C/C++ runtime environment.
*/
void reset_handler(void)
{
unsigned long *section_table_addr = &__data_section_table;
/* copy ram load sections from flash to ram */
while (section_table_addr < &__data_section_table_end)
{
unsigned long *src = (unsigned long *)*section_table_addr++;
unsigned long *dst = (unsigned long *)*section_table_addr++;
unsigned long len = (unsigned long) *section_table_addr++;
for ( ; len; len -= 4)
{
*dst++ = *src++;
}
}
/* zero initialize bss segment(s) */
while (section_table_addr < &__bss_section_table_end)
{
unsigned long *zero = (unsigned long *)*section_table_addr++;
unsigned long len = (unsigned long) *section_table_addr++;
for ( ; len; len -= 4)
{
*zero++ = 0;
}
}
hw_preinit();
/* call static constructors */
__libc_init_array();
/* execute main */
char *argv[] = {0};
main(0, argv);
for ( ; /* forever */ ;)
{
/* if we ever return from main, loop forever */
}
}
//*****************************************************************************
//
// This is the code that gets called when the processor first starts execution
// following a reset event. Only the absolutely necessary set is performed,
// after which the application supplied entry() routine is called. Any fancy
// actions (such as making decisions based on the reset cause register, and
// resetting the bits in that register) are left solely in the hands of the
// application.
//
//*****************************************************************************
void
ResetISR(void)
{
unsigned long *pulSrc, *pulDest;
//
// Fill the stack with a known value.
//
for(pulDest = pulStack; pulDest < pulStack + 256; )
{
*pulDest++ = 0xABCD;
}
//
// Copy the data segment initializers from flash to SRAM.
//
pulSrc = &_flash_data;
for(pulDest = &_data; pulDest < &_edata; )
{
*pulDest++ = *pulSrc++;
}
//
// Zero fill the bss segment.
//
for(pulDest = &_bss; pulDest < &_ebss; )
{
*pulDest++ = 0;
}
//
//Call the constructors
//
__libc_init_array();
//
// Call the application's entry point.
//
main();
}
void __attribute__((naked, noreturn)) Reset_Handler()
{
//Normally the CPU should will setup the based on the value from the first entry in the vector table.
//If you encounter problems with accessing stack variables during initialization, ensure the line below is enabled.
#ifdef sram_layout
asm ("ldr sp, =_estack");
#endif
void **pSource, **pDest;
for (pSource = &_sidata, pDest = &_sdata; pDest != &_edata; pSource++, pDest++)
*pDest = *pSource;
for (pDest = &_sbss; pDest != &_ebss; pDest++)
*pDest = 0;
SystemInit();
__libc_init_array();
(void)main();
for (;;) ;
}
void __attribute__((weak)) __libnx_init(void* ctx, Handle main_thread, void* saved_lr)
{
// Called by crt0.
// Libnx initialization goes here.
envSetup(ctx, main_thread, saved_lr);
newlibSetup();
virtmemSetup();
__libnx_initheap();
// Build argc/argv if present
argvSetup();
// Initialize services.
__appInit();
// Call constructors.
void __libc_init_array(void);
__libc_init_array();
}
void Reset_Handler(void)
{
/*
* Only Initialize Internal SRAM
* USB RAM is used for USB purpose
*/
unsigned int *src, *dst;
/* Copy data section from flash to RAM */
src = &__data_load_addr;
dst = &__data_start;
while (dst < &__data_end)
*dst++ = *src++;
/* Zero fill the bss section */
dst = &__bss_start;
while (dst < &__bss_end)
*dst++ = 0;
SystemInit();
#if defined (__cplusplus)
//
// Call C++ library initialisation
//
__libc_init_array();
#endif
#if defined (__REDLIB__)
// Call the Redlib library, which in turn calls main()
__main() ;
#else
main();
#endif
//
// main() shouldn't return, but if it does, we'll just enter an infinite loop
//
while (1)
{
}
}
/*
* This is the true entry point for untrusted code.
* See nacl_startup.h for the layout at the argument pointer.
*/
void _start(uint32_t *info) {
void (*fini)(void) = nacl_startup_fini(info);
int argc = nacl_startup_argc(info);
char **argv = nacl_startup_argv(info);
char **envp = nacl_startup_envp(info);
Elf32_auxv_t *auxv = nacl_startup_auxv(info);
environ = envp;
/*
* Record the approximate address from which the stack grows
* (usually downwards) so that libpthread can report it. Taking the
* address of any stack-allocated variable will work here.
*/
__nacl_initial_thread_stack_end = &info;
__libnacl_irt_init(auxv);
/*
* If we were started by a dynamic linker, then it passed its finalizer
* function here. For static linking, this is always NULL.
*/
if (fini != NULL)
atexit(fini);
atexit(&__libc_fini_array);
__pthread_initialize();
__libc_init_array();
int (*main_ptr)(int argc, char **argv, char **envp) = &__nacl_main;
if (main_ptr == NULL)
main_ptr = &main;
exit(main_ptr(argc, argv, envp));
/*NOTREACHED*/
__builtin_trap();
}
/**
* @brief This function is the entry point after a system reset
*
* After a system reset, the following steps are necessary and carried out:
* 1. load data section from flash to ram
* 2. overwrite uninitialized data section (BSS) with zeros
* 3. initialize the newlib
* 4. initialize the board (sync clock, setup std-IO)
* 5. initialize and start RIOTs kernel
*/
void reset_handler(void)
{
uint32_t *dst;
uint32_t *src = &_etext;
/* load data section from flash to ram */
for (dst = &_srelocate; dst < &_erelocate; ) {
*(dst++) = *(src++);
}
/* default bss section to zero */
for (dst = &_szero; dst < &_ezero; ) {
*(dst++) = 0;
}
/* initialize the board and startup the kernel */
board_init();
/* initialize std-c library (this should be done after board_init) */
__libc_init_array();
/* startup the kernel */
kernel_init();
}
void init( void )
{
uint8_t *regionAddr;
size_t regionSize;
// Initialize C library
__libc_init_array();
/* Add non-allocated memory in SRAM into heap */
regionAddr = (uint8_t *)&__HeapLimit;
if ( 0x10070000 > (size_t)(&__HeapLimit) ) {
regionSize = 0x10070000 - (size_t)(&__HeapLimit);
vPortAddHeapRegion(regionAddr, regionSize);
}
/* Add non-allocated memory in SDRAM into heap */
regionAddr = (uint8_t *)&__sdram_bss_end__;
if ( 0x30200000 > (size_t)(&__sdram_bss_end__) ) {
regionSize = 0x30200000 - (size_t)(&__sdram_bss_end__);
vPortAddHeapRegion(regionAddr, regionSize);
}
}
/**
* \brief This is the code that gets called on processor reset.
* To initialize the device, and call the main() routine.
*/
void Reset_Handler(void)
{
uint32_t *pSrc, *pDest;
/* Initialize the relocate segment */
pSrc = &_etext;
pDest = &_srelocate;
if (pSrc != pDest) {
for (; pDest < &_erelocate;) {
*pDest++ = *pSrc++;
}
}
/* Clear the zero segment */
for (pDest = &_szero; pDest < &_ezero;) {
*pDest++ = 0;
}
/* Set the vector table base address */
pSrc = (uint32_t *) & _sfixed;
SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
#if __FPU_USED
/* Enable FPU */
SCB->CPACR |= (0xFu << 20);
__DSB();
__ISB();
#endif
/* Initialize the C library */
__libc_init_array();
/* Branch to main function */
main();
/* Infinite loop */
while (1);
}
void _reset_handler (void)
{
char *src;
char *dst;
SCB->VTOR = 0;
/* There's not much frigging around to set things up; the initial
stack pointer is loaded from the vector table. At this point
we are running on the slow clock? We could crank things up
before initialising variables etc but this will put constraints
on the code to set up the clock, etc. */
/* Initialise initialised global variables in .data and relocate
.ramtext function for functions in the ROM model that need
to execute out of RAM for speed. */
for (src = &__data_load__, dst = &__data_start__; dst < &__data_end__; )
*dst++ = *src++;
/* Zero uninitialised global variables in .bss. */
for (dst = &__bss_start__; dst < &__bss_end__; )
*dst++ = 0;
/* Remap the exception table into SRAM to allow dynamic allocation.
This register is zero on reset. */
SCB->VTOR = (uint32_t) &exception_table & SCB_VTOR_TBLOFF_Msk;
/* Set up clocks, etc. */
mcu_init ();
/* Call constructors and init functions. */
__libc_init_array ();
main ();
/* Hang. */
while (1)
continue;
}
extern "C" void init( void )
{
SystemInit();
// Set Systick to 1ms interval, common to all SAM3 variants
if (SysTick_Config(SystemCoreClock / 1000))
{
// Capture error
while (true);
}
UrgentInit(); // initialise anything in the main application that can't wait
// Initialize C library (I think this calls C++ constructors for static data too)
__libc_init_array();
// We no longer disable pullups on all pins here, better to leave them enabled until the port is initialised
// Initialize Serial port U(S)ART pins
ConfigurePin(g_APinDescription[APINS_UART0]);
setPullup(APIN_UART0_RXD, true); // Enable pullup for RX0
ConfigurePin(g_APinDescription[APINS_UART1]);
setPullup(APIN_UART1_RXD, true); // Enable pullup for RX1
// No need to initialize the USB pins on the SAM4E because they are USB by default
// Initialize Analog Controller
AnalogInInit();
// Initialize analogOutput module
AnalogOutInit();
// Initialize HSMCI pins
ConfigurePin(g_APinDescription[APIN_HSMCI_CLOCK]);
ConfigurePin(g_APinDescription[APINS_HSMCI_DATA]);
// Start the USB
udc_start();
}
/**
* \brief This is the code that gets called on processor reset.
* To initialize the device, and call the main() routine.
*/
void Reset_Handler( void )
{
uint32_t *pSrc, *pDest;
/* Initialize the initialized data section */
pSrc = &__etext;
pDest = &__data_start__;
if ( (&__data_start__ != &__data_end__) && (pSrc != pDest) )
{
for (; pDest < &__data_end__ ; pDest++, pSrc++ )
{
*pDest = *pSrc ;
}
}
/* Clear the zero section */
if ( (&__bss_start__ != &__bss_end__) && (pSrc != pDest) )
{
for ( pDest = &__bss_start__ ; pDest < &__bss_end__ ; pDest++ )
{
*pDest = 0 ;
}
}
/* Initialize the C library */
__libc_init_array();
SystemInit() ;
/* Branch to main function */
main() ;
/* Infinite loop */
while ( 1 )
{
}
}
/*******************************************************************************
* Function Name : Reset_Handler
* Description : This is the code that gets called when the processor first starts execution
* following a reset event. Only the absolutely necessary set is performed,
* after which the application supplied main() routine is called.
* Input :
* Output :
* Return :
*******************************************************************************/
void Reset_Handler(void)
{
unsigned long *pulSrc, *pulDest;
/* Initialize the System */
SystemInit();
/* Copy the data segment initializers from flash to SRAM in ROM mode */
pulSrc = &_etext;
for (pulDest = &_sidata; pulDest < &_edata;)
{
*(pulDest++) = *(pulSrc++);
}
/* Zero fill the bss segment */
for (pulDest = &_sbss; pulDest < &_ebss;)
{
*(pulDest++) = 0;
}
/* Copy the fastcode which shall be executed from ROM to SRAM */
pulSrc = &_sifastcode;
for (pulDest = &_sfastcode; pulDest < &_efastcode;)
{
*(pulDest++) = *(pulSrc++);
}
/* Call CTORS of static objects */
__libc_init_array();
/* Call the application's entry point */
main();
while (1)
{
/* The application entry point shall not be left, in case it did ten go into an infinite loop */
}
} /* Reset_Handler */
void Reset_Handler(void) {
unsigned long *src, *dst;
src = &_sidata;
dst = &_sdata;
// Copy data initializers
while (dst < &_edata)
*(dst++) = *(src++);
// Zero bss
dst = &_sbss;
while (dst < &_ebss)
*(dst++) = 0;
SystemInit();
__libc_init_array();
main();
while(1) {}
}
static void call_main(void *p)
{
char *c, quote;
#ifdef CONFIG_QEMU_XS_ARGS
char *domargs, *msg;
#endif
int argc;
char **argv;
char *envp[] = { NULL };
#ifdef CONFIG_QEMU_XS_ARGS
char *vm;
char path[128];
int domid;
#endif
int i;
/* Let other parts initialize (including console output) before maybe
* crashing. */
//sleep(1);
//printk("Start call_main : main.c\n");
#ifdef CONFIG_SPARSE_BSS
sparse((unsigned long) &__app_bss_start, &__app_bss_end - &__app_bss_start);
#endif
#if defined(HAVE_LWIP) && defined(CONFIG_START_NETWORK) && defined(CONFIG_NETFRONT)
start_networking();
#endif
#ifdef CONFIG_PCIFRONT
create_thread("pcifront", pcifront_watches, NULL);
#endif
#ifdef CONFIG_QEMU_XS_ARGS
/* Fetch argc, argv from XenStore */
domid = xenbus_read_integer("target");
if (domid == -1) {
printk("Couldn't read target\n");
do_exit();
}
snprintf(path, sizeof(path), "/local/domain/%d/vm", domid);
msg = xenbus_read(XBT_NIL, path, &vm);
if (msg) {
printk("Couldn't read vm path\n");
do_exit();
}
printk("dom vm is at %s\n", vm);
snprintf(path, sizeof(path), "%s/image/dmargs", vm);
free(vm);
msg = xenbus_read(XBT_NIL, path, &domargs);
if (msg) {
printk("Couldn't get stubdom args: %s\n", msg);
domargs = strdup("");
}
#endif
argc = 1;
#define PARSE_ARGS(ARGS,START,QUOTE,END) \
c = ARGS; \
quote = 0; \
while (*c) { \
if (*c != ' ') { \
START; \
while (*c) { \
if (quote) { \
if (*c == quote) { \
quote = 0; \
QUOTE; \
continue; \
} \
} else if (*c == ' ') \
break; \
if (*c == '"' || *c == '\'') { \
quote = *c; \
QUOTE; \
continue; \
} \
c++; \
} \
} else { \
END; \
while (*c == ' ') \
c++; \
} \
} \
if (quote) {\
printk("Warning: unterminated quotation %c\n", quote); \
quote = 0; \
}
#define PARSE_ARGS_COUNT(ARGS) PARSE_ARGS(ARGS, argc++, c++, )
#define PARSE_ARGS_STORE(ARGS) PARSE_ARGS(ARGS, argv[argc++] = c, memmove(c, c + 1, strlen(c + 1) + 1), *c++ = 0)
PARSE_ARGS_COUNT((char*)start_info.cmd_line);
#ifdef CONFIG_QEMU_XS_ARGS
PARSE_ARGS_COUNT(domargs);
#endif
argv = alloca((argc + 1) * sizeof(char *));
argv[0] = "main";
argc = 1;
PARSE_ARGS_STORE((char*)start_info.cmd_line)
#ifdef CONFIG_QEMU_XS_ARGS
PARSE_ARGS_STORE(domargs)
#endif
argv[argc] = NULL;
for (i = 0; i < argc; i++)
printf("\"%s\" ", argv[i]);
//printf("\n");
__libc_init_array();
environ = envp;
for (i = 0; __CTOR_LIST__[i] != 0; i++)
((void((*)(void)))__CTOR_LIST__[i]) ();
tzset();
exit(main(argc, argv, envp));
}
void OS::start(uint32_t boot_magic, uint32_t boot_addr)
{
OS::cmdline = Service::binary_name();
// Initialize stdout handlers
if(os_default_stdout) {
OS::add_stdout(&OS::default_stdout);
}
PROFILE("OS::start");
// Print a fancy header
CAPTION("#include<os> // Literally");
MYINFO("Stack: %p", get_cpu_esp());
MYINFO("Boot magic: 0x%x, addr: 0x%x", boot_magic, boot_addr);
// Call global ctors
PROFILE("Global constructors");
__libc_init_array();
// PAGING //
PROFILE("Enable paging");
extern void __arch_init_paging();
__arch_init_paging();
// BOOT METHOD //
PROFILE("Multiboot / legacy");
OS::memory_end_ = 0;
// Detect memory limits etc. depending on boot type
if (boot_magic == MULTIBOOT_BOOTLOADER_MAGIC) {
OS::multiboot(boot_addr);
} else {
if (is_softreset_magic(boot_magic) && boot_addr != 0)
OS::resume_softreset(boot_addr);
OS::legacy_boot();
}
assert(OS::memory_end_ != 0);
// Give the rest of physical memory to heap
OS::heap_max_ = OS::memory_end_;
/// STATMAN ///
PROFILE("Statman");
/// initialize on page 9, 8 pages in size
Statman::get().init(0x8000, 0x8000);
PROFILE("Memory map");
// Assign memory ranges used by the kernel
auto& memmap = memory_map();
MYINFO("Assigning fixed memory ranges (Memory map)");
memmap.assign_range({0x8000, 0xffff, "Statman"});
#if defined(ARCH_x86_64)
/**
* TODO: Map binary parts using mem::map instead of assigning ranges directly
* e.g. the .text segment is now mapped individually by __arch_init_paging
*/
memmap.assign_range({0x1000, 0x6fff, "Pagetables"});
memmap.assign_range({0x10000, 0x9d3ff, "Stack"});
#elif defined(ARCH_i686)
memmap.assign_range({0x10000, 0x9d3ff, "Stack"});
#endif
assert(::heap_begin != 0x0 and OS::heap_max_ != 0x0);
// @note for security we don't want to expose this
memmap.assign_range({(uintptr_t)&_end, ::heap_begin - 1,
"Pre-heap"});
uintptr_t span_max = std::numeric_limits<std::ptrdiff_t>::max();
uintptr_t heap_range_max_ = std::min(span_max, OS::heap_max_);
MYINFO("Assigning heap");
memmap.assign_range({::heap_begin, heap_range_max_,
"Dynamic memory", heap_usage });
MYINFO("Virtual memory map");
for (const auto &i : memmap)
INFO2("%s",i.second.to_string().c_str());
PROFILE("Platform init");
extern void __platform_init();
__platform_init();
PROFILE("RTC init");
// Realtime/monotonic clock
RTC::init();
}
//*****************************************************************************
// Reset entry point for your code.
// Sets up a simple runtime environment and initializes the C/C++
// library.
//
//*****************************************************************************
void
ResetISR(void) {
// ******************************
// Modify CREG->M0APPMAP so that M0 looks in correct place
// for its vector table when an exception is triggered.
// Note that we do not use the CMSIS register access mechanism,
// as there is no guarantee that the project has been configured
// to use CMSIS.
unsigned int *pCREG_M0APPMAP = (unsigned int *) 0x40043404;
// CMSIS : CREG->M0APPMAP = <address of vector table>
*pCREG_M0APPMAP = (unsigned int)g_pfnVectors;
//
// Copy the data sections from flash to SRAM.
//
unsigned int LoadAddr, ExeAddr, SectionLen;
unsigned int *SectionTableAddr;
// Load base address of Global Section Table
SectionTableAddr = &__data_section_table;
// Copy the data sections from flash to SRAM.
while (SectionTableAddr < &__data_section_table_end) {
LoadAddr = *SectionTableAddr++;
ExeAddr = *SectionTableAddr++;
SectionLen = *SectionTableAddr++;
data_init(LoadAddr, ExeAddr, SectionLen);
}
// At this point, SectionTableAddr = &__bss_section_table;
// Zero fill the bss segment
while (SectionTableAddr < &__bss_section_table_end) {
ExeAddr = *SectionTableAddr++;
SectionLen = *SectionTableAddr++;
bss_init(ExeAddr, SectionLen);
}
// **********************************************************
// No need to call SystemInit() here, as master CM4 cpu will
// have done the main system set up before enabling CM0.
// **********************************************************
#if defined (__cplusplus)
//
// Call C++ library initialisation
//
__libc_init_array();
#endif
#if defined (__REDLIB__)
// Call the Redlib library, which in turn calls main()
__main() ;
#else
main();
#endif
//
// main() shouldn't return, but if it does, we'll just enter an infinite loop
//
while (1) {
;
}
}
void
ResetISR(void) {
//
// Copy the data sections from flash to SRAM.
//
unsigned int LoadAddr, ExeAddr, SectionLen;
unsigned int *SectionTableAddr;
// Load base address of Global Section Table
SectionTableAddr = &__data_section_table;
// Copy the data sections from flash to SRAM.
while (SectionTableAddr < &__data_section_table_end) {
LoadAddr = *SectionTableAddr++;
ExeAddr = *SectionTableAddr++;
SectionLen = *SectionTableAddr++;
data_init(LoadAddr, ExeAddr, SectionLen);
}
// At this point, SectionTableAddr = &__bss_section_table;
// Zero fill the bss segment
while (SectionTableAddr < &__bss_section_table_end) {
ExeAddr = *SectionTableAddr++;
SectionLen = *SectionTableAddr++;
bss_init(ExeAddr, SectionLen);
}
// Patch the AEABI integer divide functions to use MCU's romdivide library
#ifdef __USE_ROMDIVIDE
// Get address of Integer division routines function table in ROM
unsigned int *div_ptr = (unsigned int *)((unsigned int *)*(PTR_ROM_DRIVER_TABLE))[4];
// Get addresses of integer divide routines in ROM
// These address are then used by the code in aeabi_romdiv_patch.s
pDivRom_idiv = (unsigned int *)div_ptr[0];
pDivRom_uidiv = (unsigned int *)div_ptr[1];
#endif
#if defined (__USE_CMSIS) || defined (__USE_LPCOPEN)
SystemInit();
#endif
#if defined (__cplusplus)
//
// Call C++ library initialisation
//
__libc_init_array();
#endif
#if defined (__REDLIB__)
// Call the Redlib library, which in turn calls main()
__main() ;
#else
main();
#endif
//
// main() shouldn't return, but if it does, we'll just enter an infinite loop
//
while (1) {
;
}
}
void init( void )
{
SystemInit();
// Set Systick to 1ms interval, common to all SAM3 variants
if (SysTick_Config(SystemCoreClock / 1000))
{
// Capture error
while (true);
}
// Disable watchdog
WDT_Disable(WDT);
// Initialize C library
__libc_init_array();
// Disable pull-up on every pin
for (int i = 0; i < PINS_COUNT; i++)
digitalWrite(i, LOW);
// Enable parallel access on PIO output data registers
PIOA->PIO_OWER = 0xFFFFFFFF;
PIOB->PIO_OWER = 0xFFFFFFFF;
PIOC->PIO_OWER = 0xFFFFFFFF;
PIOD->PIO_OWER = 0xFFFFFFFF;
// Initialize Serial port U(S)ART pins
PIO_Configure(
g_APinDescription[PINS_UART].pPort,
g_APinDescription[PINS_UART].ulPinType,
g_APinDescription[PINS_UART].ulPin,
g_APinDescription[PINS_UART].ulPinConfiguration);
digitalWrite(0, HIGH); // Enable pullup for RX0
PIO_Configure(
g_APinDescription[PINS_USART0].pPort,
g_APinDescription[PINS_USART0].ulPinType,
g_APinDescription[PINS_USART0].ulPin,
g_APinDescription[PINS_USART0].ulPinConfiguration);
PIO_Configure(
g_APinDescription[PINS_USART1].pPort,
g_APinDescription[PINS_USART1].ulPinType,
g_APinDescription[PINS_USART1].ulPin,
g_APinDescription[PINS_USART1].ulPinConfiguration);
PIO_Configure(
g_APinDescription[PINS_USART3].pPort,
g_APinDescription[PINS_USART3].ulPinType,
g_APinDescription[PINS_USART3].ulPin,
g_APinDescription[PINS_USART3].ulPinConfiguration);
// Initialize USB pins
PIO_Configure(
g_APinDescription[PINS_USB].pPort,
g_APinDescription[PINS_USB].ulPinType,
g_APinDescription[PINS_USB].ulPin,
g_APinDescription[PINS_USB].ulPinConfiguration);
// Initialize CAN pins
/* PIO_Configure(
g_APinDescription[PINS_CAN0].pPort,
g_APinDescription[PINS_CAN0].ulPinType,
g_APinDescription[PINS_CAN0].ulPin,
g_APinDescription[PINS_CAN0].ulPinConfiguration);
PIO_Configure(
g_APinDescription[PINS_CAN1].pPort,
g_APinDescription[PINS_CAN1].ulPinType,
g_APinDescription[PINS_CAN1].ulPin,
g_APinDescription[PINS_CAN1].ulPinConfiguration); */
// Initialize Analog Controller
pmc_enable_periph_clk(ID_ADC);
adc_init(ADC, SystemCoreClock, ADC_FREQ_MAX, ADC_STARTUP_FAST);
adc_configure_timing(ADC, 0, ADC_SETTLING_TIME_3, 1);
adc_configure_trigger(ADC, ADC_TRIG_SW, 0); // Disable hardware trigger.
adc_disable_interrupt(ADC, 0xFFFFFFFF); // Disable all ADC interrupts.
adc_disable_all_channel(ADC);
// Initialize analogOutput module
analogOutputInit();
}
void
ResetISR(void) {
// Optionally enable RAM banks that may be off by default at reset
#if !defined (DONT_ENABLE_DISABLED_RAMBANKS)
volatile unsigned int *SYSCON_SYSAHBCLKCTRL = (unsigned int *) 0x40048080;
// Ensure that RAM1(26) and USBSRAM(27) bits in SYSAHBCLKCTRL are set
*SYSCON_SYSAHBCLKCTRL |= (1 << 26) | (1 <<27);
#endif
//
// Copy the data sections from flash to SRAM.
//
unsigned int LoadAddr, ExeAddr, SectionLen;
unsigned int *SectionTableAddr;
// Load base address of Global Section Table
SectionTableAddr = &__data_section_table;
// Copy the data sections from flash to SRAM.
while (SectionTableAddr < &__data_section_table_end) {
LoadAddr = *SectionTableAddr++;
ExeAddr = *SectionTableAddr++;
SectionLen = *SectionTableAddr++;
data_init(LoadAddr, ExeAddr, SectionLen);
}
// At this point, SectionTableAddr = &__bss_section_table;
// Zero fill the bss segment
while (SectionTableAddr < &__bss_section_table_end) {
ExeAddr = *SectionTableAddr++;
SectionLen = *SectionTableAddr++;
bss_init(ExeAddr, SectionLen);
}
// Patch the AEABI integer divide functions to use MCU's romdivide library
#ifdef __USE_ROMDIVIDE
// Get address of Integer division routines function table in ROM
unsigned int *div_ptr = (unsigned int *)((unsigned int *)*(PTR_ROM_DRIVER_TABLE))[4];
// Get addresses of integer divide routines in ROM
// These address are then used by the code in aeabi_romdiv_patch.s
pDivRom_idiv = (unsigned int *)div_ptr[0];
pDivRom_uidiv = (unsigned int *)div_ptr[1];
#endif
#if defined (__USE_CMSIS) || defined (__USE_LPCOPEN)
SystemInit();
#endif
#if defined (__cplusplus)
//
// Call C++ library initialisation
//
__libc_init_array();
#endif
#if defined (__REDLIB__)
// Call the Redlib library, which in turn calls main()
__main() ;
#else
main();
#endif
//
// main() shouldn't return, but if it does, we'll just enter an infinite loop
//
while (1) {
;
}
}
//*****************************************************************************
// Reset entry point for your code.
// Sets up a simple runtime environment and initializes the C/C++
// library.
//
//*****************************************************************************
void ResetISR(void) {
// *************************************************************
// The following conditional block of code manually resets as
// much of the peripheral set of the LPC43 as possible. This is
// done because the LPC43 does not provide a means of triggering
// a full system reset under debugger control, which can cause
// problems in certain circumstances when debugging.
//
// You can prevent this code block being included if you require
// (for example when creating a final executable which you will
// not debug) by setting the define 'DONT_RESET_ON_RESTART'.
//
#ifndef DONT_RESET_ON_RESTART
// Disable interrupts
__asm volatile ("cpsid i");
// equivalent to CMSIS '__disable_irq()' function
unsigned int *RESET_CONTROL = (unsigned int *) 0x40053100;
// LPC_RGU->RESET_CTRL0 @ 0x40053100
// LPC_RGU->RESET_CTRL1 @ 0x40053104
// Note that we do not use the CMSIS register access mechanism,
// as there is no guarantee that the project has been configured
// to use CMSIS.
// Write to LPC_RGU->RESET_CTRL0
*(RESET_CONTROL + 0) = 0x10DF1000;
// GPIO_RST|AES_RST|ETHERNET_RST|SDIO_RST|DMA_RST|
// USB1_RST|USB0_RST|LCD_RST|M0_SUB_RST
// Write to LPC_RGU->RESET_CTRL1
*(RESET_CONTROL + 1) = 0x01DFF7FF;
// M0APP_RST|CAN0_RST|CAN1_RST|I2S_RST|SSP1_RST|SSP0_RST|
// I2C1_RST|I2C0_RST|UART3_RST|UART1_RST|UART1_RST|UART0_RST|
// DAC_RST|ADC1_RST|ADC0_RST|QEI_RST|MOTOCONPWM_RST|SCT_RST|
// RITIMER_RST|TIMER3_RST|TIMER2_RST|TIMER1_RST|TIMER0_RST
// Clear all pending interrupts in the NVIC
volatile unsigned int *NVIC_ICPR = (unsigned int *) 0xE000E280;
unsigned int irqpendloop;
for (irqpendloop = 0; irqpendloop < 8; irqpendloop++) {
*(NVIC_ICPR + irqpendloop) = 0xFFFFFFFF;
}
// Reenable interrupts
__asm volatile ("cpsie i");
// equivalent to CMSIS '__enable_irq()' function
#endif // ifndef DONT_RESET_ON_RESTART
// *************************************************************
#if defined (__USE_LPCOPEN)
SystemInit();
#endif
//
// Copy the data sections from flash to SRAM.
//
unsigned int LoadAddr, ExeAddr, SectionLen;
unsigned int *SectionTableAddr;
// Load base address of Global Section Table
SectionTableAddr = &__data_section_table;
// Copy the data sections from flash to SRAM.
while (SectionTableAddr < &__data_section_table_end) {
LoadAddr = *SectionTableAddr++;
ExeAddr = *SectionTableAddr++;
SectionLen = *SectionTableAddr++;
data_init(LoadAddr, ExeAddr, SectionLen);
}
// At this point, SectionTableAddr = &__bss_section_table;
// Zero fill the bss segment
while (SectionTableAddr < &__bss_section_table_end) {
ExeAddr = *SectionTableAddr++;
SectionLen = *SectionTableAddr++;
bss_init(ExeAddr, SectionLen);
}
#if !defined (__USE_LPCOPEN)
// LPCOpen init code deals with FP and VTOR initialisation
#if defined (__VFP_FP__) && !defined (__SOFTFP__)
/*
* Code to enable the Cortex-M4 FPU only included
* if appropriate build options have been selected.
* Code taken from Section 7.1, Cortex-M4 TRM (DDI0439C)
*/
// CPACR is located at address 0xE000ED88
asm("LDR.W R0, =0xE000ED88");
// Read CPACR
asm("LDR R1, [R0]");
// Set bits 20-23 to enable CP10 and CP11 coprocessors
asm(" ORR R1, R1, #(0xF << 20)");
// Write back the modified value to the CPACR
asm("STR R1, [R0]");
#endif // (__VFP_FP__) && !(__SOFTFP__)
// ******************************
// Check to see if we are running the code from a non-zero
// address (eg RAM, external flash), in which case we need
// to modify the VTOR register to tell the CPU that the
// vector table is located at a non-0x0 address.
// Note that we do not use the CMSIS register access mechanism,
// as there is no guarantee that the project has been configured
// to use CMSIS.
unsigned int * pSCB_VTOR = (unsigned int *) 0xE000ED08;
if ((unsigned int *) g_pfnVectors != (unsigned int *) 0x00000000) {
// CMSIS : SCB->VTOR = <address of vector table>
*pSCB_VTOR = (unsigned int) g_pfnVectors;
}
#endif
#if defined (__USE_CMSIS)
SystemInit();
#endif
#if defined (__cplusplus)
//
// Call C++ library initialisation
//
__libc_init_array();
#endif
#if defined (__REDLIB__)
// Call the Redlib library, which in turn calls main()
__main();
#else
main();
#endif
//
// main() shouldn't return, but if it does, we'll just enter an infinite loop
//
while (1) {
;
}
}
void
ResetISR(void) {
#ifndef USE_OLD_STYLE_DATA_BSS_INIT
//
// Copy the data sections from flash to SRAM.
//
unsigned int LoadAddr, ExeAddr, SectionLen;
unsigned int *SectionTableAddr;
// Load base address of Global Section Table
SectionTableAddr = &__data_section_table;
// Copy the data sections from flash to SRAM.
while (SectionTableAddr < &__data_section_table_end) {
LoadAddr = *SectionTableAddr++;
ExeAddr = *SectionTableAddr++;
SectionLen = *SectionTableAddr++;
data_init(LoadAddr, ExeAddr, SectionLen);
}
// At this point, SectionTableAddr = &__bss_section_table;
// Zero fill the bss segment
while (SectionTableAddr < &__bss_section_table_end) {
ExeAddr = *SectionTableAddr++;
SectionLen = *SectionTableAddr++;
bss_init(ExeAddr, SectionLen);
}
#else
// Use Old Style Data and BSS section initialization.
// This will only initialize a single RAM bank.
unsigned int * LoadAddr, *ExeAddr, *EndAddr, SectionLen;
// Copy the data segment from flash to SRAM.
LoadAddr = &_etext;
ExeAddr = &_data;
EndAddr = &_edata;
SectionLen = (void*)EndAddr - (void*)ExeAddr;
data_init((unsigned int)LoadAddr, (unsigned int)ExeAddr, SectionLen);
// Zero fill the bss segment
ExeAddr = &_bss;
EndAddr = &_ebss;
SectionLen = (void*)EndAddr - (void*)ExeAddr;
bss_init ((unsigned int)ExeAddr, SectionLen);
#endif
#ifdef __USE_CMSIS
SystemInit();
#endif
#if defined (__cplusplus)
//
// Call C++ library initialisation
//
__libc_init_array();
#endif
#if defined (__REDLIB__)
// Call the Redlib library, which in turn calls main()
__main() ;
#else
main();
#endif
//
// main() shouldn't return, but if it does, we'll just enter an infinite loop
//
while (1) {
;
}
}
void init( void )
{
SystemInit();
// Set Systick to 1ms interval
if (SysTick_Config(SystemCoreClock / 1000))
{
// Capture error
while (true);
}
// Disable watchdog
WDT_Disable(WDT);
// Initialize C library
__libc_init_array();
// Disable pull-up on every pin
for (uint i = 0u; i < PINS_COUNT; i++)
digitalWrite(i, LOW);
// Enable parallel access on PIO output data registers
PIOA->PIO_OWER = 0xFFFFFFFF;
PIOB->PIO_OWER = 0xFFFFFFFF;
//PIOC->PIO_OWER = 0xFFFFFFFF;
//PIOD->PIO_OWER = 0xFFFFFFFF;
//turn off ERASE and JTAG pins
MATRIX->CCFG_SYSIO = CCFG_SYSIO_SYSIO12 | CCFG_SYSIO_SYSIO7 | CCFG_SYSIO_SYSIO6 | CCFG_SYSIO_SYSIO5 | CCFG_SYSIO_SYSIO4;
// Initialize Serial port UART pins
PIO_Configure(
g_APinDescription[PINS_USART0].pPort,
g_APinDescription[PINS_USART0].ulPinType,
g_APinDescription[PINS_USART0].ulPin,
g_APinDescription[PINS_USART0].ulPinConfiguration);
digitalWrite(0u, HIGH); // Enable pullup for RX0
// Initialize Serial port USART pins
// Pins are disconnected from PIO controller and hooked to the peripheral.
// Currently PIO_Configure always enables the pullup resistor for peripherals. This appears to be a bug, as it is not written correctly for that purpose, but has that affect.
PIO_Configure(
g_APinDescription[PINS_UART1].pPort,
g_APinDescription[PINS_UART1].ulPinType,
g_APinDescription[PINS_UART1].ulPin,
g_APinDescription[PINS_UART1].ulPinConfiguration);
PIO_Configure(
g_APinDescription[B1].pPort,
g_APinDescription[B1].ulPinType,
g_APinDescription[B1].ulPin,
g_APinDescription[B1].ulPinConfiguration);
/*
TODO: wire up USB ID line and check out USB configuration
// Initialize USB pins
PIO_Configure(
g_APinDescription[PINS_USB].pPort,
g_APinDescription[PINS_USB].ulPinType,
g_APinDescription[PINS_USB].ulPin,
g_APinDescription[PINS_USB].ulPinConfiguration);
//TODO: Initialize I2C pins for crypto IC
PIO_Configure(
g_APinDescription[PINS_SPI].pPort,
g_APinDescription[PINS_SPI].ulPinType,
g_APinDescription[PINS_SPI].ulPin,
g_APinDescription[PINS_SPI].ulPinConfiguration);
*/
// Initialize Analog Controller
pmc_enable_periph_clk(ID_ADC);
adc_init(ADC, SystemCoreClock, ADC_FREQ_MAX, ADC_STARTUP_FAST);
adc_configure_timing(ADC, 0, ADC_SETTLING_TIME_3, 1);
adc_configure_trigger(ADC, ADC_TRIG_SW, 0); // Disable hardware trigger.
adc_disable_interrupt(ADC, 0xFFFFFFFF); // Disable all ADC interrupts.
adc_disable_all_channel(ADC);
// Initialize analogOutput module
analogOutputInit();
}
void ResetHandler(void)
{
uint32_t *src = &_etext;
uint32_t *dest = &_sdata;
WDOG_UNLOCK = WDOG_UNLOCK_SEQ1;
WDOG_UNLOCK = WDOG_UNLOCK_SEQ2;
WDOG_STCTRLH = WDOG_STCTRLH_ALLOWUPDATE;
startup_early_hook();
// enable clocks to always-used peripherals
SIM_SCGC5 = 0x00043F82; // clocks active to all GPIO
SIM_SCGC6 = SIM_SCGC6_RTC | SIM_SCGC6_FTM0 | SIM_SCGC6_FTM1 | SIM_SCGC6_ADC0 | SIM_SCGC6_FTFL;
// if the RTC oscillator isn't enabled, get it started early
if (!(RTC_CR & RTC_CR_OSCE)) {
RTC_SR = 0;
RTC_CR = RTC_CR_SC16P | RTC_CR_SC4P | RTC_CR_OSCE;
}
// TODO: do this while the PLL is waiting to lock....
while (dest < &_edata) *dest++ = *src++;
dest = &_sbss;
while (dest < &_ebss) *dest++ = 0;
SCB_VTOR = 0; // use vector table in flash
// start in FEI mode
// enable capacitors for crystal
OSC0_CR = OSC_SC8P | OSC_SC2P;
// enable osc, 8-32 MHz range, low power mode
MCG_C2 = MCG_C2_RANGE0(2) | MCG_C2_EREFS;
// switch to crystal as clock source, FLL input = 16 MHz / 512
MCG_C1 = MCG_C1_CLKS(2) | MCG_C1_FRDIV(4);
// wait for crystal oscillator to begin
while ((MCG_S & MCG_S_OSCINIT0) == 0) ;
// wait for FLL to use oscillator
while ((MCG_S & MCG_S_IREFST) != 0) ;
// wait for MCGOUT to use oscillator
while ((MCG_S & MCG_S_CLKST_MASK) != MCG_S_CLKST(2)) ;
// now we're in FBE mode
// config PLL input for 16 MHz Crystal / 4 = 4 MHz
MCG_C5 = MCG_C5_PRDIV0(3);
// config PLL for 96 MHz output
MCG_C6 = MCG_C6_PLLS | MCG_C6_VDIV0(0);
// wait for PLL to start using xtal as its input
while (!(MCG_S & MCG_S_PLLST)) ;
// wait for PLL to lock
while (!(MCG_S & MCG_S_LOCK0)) ;
// now we're in PBE mode
#if F_CPU == 96000000
// config divisors: 96 MHz core, 48 MHz bus, 24 MHz flash
SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(1) | SIM_CLKDIV1_OUTDIV4(3);
#elif F_CPU == 48000000
// config divisors: 48 MHz core, 48 MHz bus, 24 MHz flash
SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(1) | SIM_CLKDIV1_OUTDIV2(1) | SIM_CLKDIV1_OUTDIV4(3);
#elif F_CPU == 24000000
// config divisors: 24 MHz core, 24 MHz bus, 24 MHz flash
SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(3) | SIM_CLKDIV1_OUTDIV2(3) | SIM_CLKDIV1_OUTDIV4(3);
#else
#error "Error, F_CPU must be 96000000, 48000000, or 24000000"
#endif
// switch to PLL as clock source, FLL input = 16 MHz / 512
MCG_C1 = MCG_C1_CLKS(0) | MCG_C1_FRDIV(4);
// wait for PLL clock to be used
while ((MCG_S & MCG_S_CLKST_MASK) != MCG_S_CLKST(3)) ;
// now we're in PEE mode
// configure USB for 48 MHz clock
SIM_CLKDIV2 = SIM_CLKDIV2_USBDIV(1); // USB = 96 MHz PLL / 2
// USB uses PLL clock, trace is CPU clock, CLKOUT=OSCERCLK0
SIM_SOPT2 = SIM_SOPT2_USBSRC | SIM_SOPT2_PLLFLLSEL | SIM_SOPT2_TRACECLKSEL | SIM_SOPT2_CLKOUTSEL(6);
// initialize the SysTick counter
SYST_RVR = (F_CPU / 1000) - 1;
SYST_CSR = SYST_CSR_CLKSOURCE | SYST_CSR_TICKINT | SYST_CSR_ENABLE;
//init_pins();
__enable_irq();
_init_Teensyduino_internal_();
if (RTC_SR & RTC_SR_TIF) rtc_set(TIME_T);
__libc_init_array();
/*
for (ptr = &__init_array_start; ptr < &__init_array_end; ptr++) {
(*ptr)();
}
*/
startup_late_hook();
main();
while (1) ;
}
void initSystem(void (*retAddr)(void))
{
__libctru_init(retAddr);
__appInit();
__libc_init_array();
}
void init( void )
{
SystemInit();
// Set Systick to 1ms interval, common to all SAM3 variants
if (SysTick_Config(SystemCoreClock / 1000))
{
// Capture error
while (true);
}
/* Configure the SysTick Handler Priority: Preemption priority and subpriority */
NVIC_SetPriority(SysTick_IRQn, 15);
// Disable watchdog
//WDT_Disable(WDT);
// Initialize C library
__libc_init_array();
// default 13pin led will off.
pinMode(13,OUTPUT);
digitalWrite(13, LOW);
/*
// Enable parallel access on PIo output data registers
PIOA->PIO_OWER = 0xFFFFFFFF;
PIOB->PIO_OWER = 0xFFFFFFFF;
PIOC->PIO_OWER = 0xFFFFFFFF;
PIOD->PIO_OWER = 0xFFFFFFFF;
// Initialize Serial port U(S)Art pins
PIO_Configure(
g_APinDescription[PINS_UART].pport,
g_APinDescription[PINS_UART].ulpintype,
g_APinDescription[PINS_UART].ulpin,
g_APinDescription[PINS_UART].ulpinconfiguration);
digitalWrite(0, HIGH); // Enable pullup for rx0
PIO_Configure(
g_APinDescription[PINS_USART0].pport,
g_APinDescription[PINS_USART0].ulpintype,
g_APinDescription[PINS_USART0].ulpin,
g_APinDescription[PINS_USART0].ulpinconfiguration);
PIO_Configure(
g_APinDescription[PINS_USART1].pport,
g_APinDescription[PINS_USART1].ulpintype,
g_APinDescription[PINS_USART1].ulpin,
g_APinDescription[PINS_USART1].ulpinconfiguration);
PIO_Configure(
g_APinDescription[PINS_USART3].pport,
g_APinDescription[PINS_USART3].ulpintype,
g_APinDescription[PINS_USART3].ulpin,
g_APinDescription[PINS_USART3].ulpinconfiguration);
// Initialize USB pins
PIO_Configure(
g_APinDescription[PINS_USB].pport,
g_APinDescription[PINS_USB].ulpintype,
g_APinDescription[PINS_USB].ulpin,
g_APinDescription[PINS_USB].ulpinconfiguration);
// Initialize CAN pins
PIO_Configure(
g_APinDescription[PINS_CAN0].pport,
g_APinDescription[PINS_CAN0].ulpintype,
g_APinDescription[PINS_CAN0].ulpin,
g_APinDescription[PINS_CAN0].ulpinconfiguration);
PIO_Configure(
g_APinDescription[PINS_CAN1].pport,
g_APinDescription[PINS_CAN1].ulpintype,
g_APinDescription[PINS_CAN1].ulPin,
g_APinDescription[PINS_CAN1].ulPinConfiguration);
*/
//disable JTAG-DP,release pin 29(PB3),30(PB4),23(PA15)
RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
//GPIO_PinRemapConfig(GPIO_Remap_SWJ_JTAGDisable,ENABLE);
////remap Timer4
//GPIO_PinRemapConfig(GPIO_Remap_TIM4,ENABLE);
////remap USART3
//GPIO_PinRemapConfig(GPIO_FullRemap_USART3,ENABLE);
////remap USART2
//GPIO_PinRemapConfig(GPIO_Remap_USART2,ENABLE);
////remap CAN1,to PD0,PD1
//GPIO_PinRemapConfig(GPIO_Remap2_CAN1,ENABLE);
// Initialize Analog Controller
ADC_InitTypeDef ADC_InitStructure;
ADC_CommonInitTypeDef ADC_CommonInitStructure;
//RCC_AHB1PeriphClockCmd( RCC_AHB1Periph_GPIOC, ENABLE);
// Enable ADC1 clock
RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC1, ENABLE);
ADC_DeInit();
ADC_CommonInitStructure.ADC_Mode = ADC_Mode_Independent;
ADC_CommonInitStructure.ADC_TwoSamplingDelay = ADC_TwoSamplingDelay_6Cycles;
ADC_CommonInitStructure.ADC_DMAAccessMode = ADC_DMAAccessMode_Disabled;
ADC_CommonInitStructure.ADC_Prescaler = ADC_Prescaler_Div2;
ADC_CommonInit(&ADC_CommonInitStructure);
ADC_InitStructure.ADC_Resolution = ADC_Resolution_12b;
/* ADC1 regular channel 12 configuration ************************************/
ADC_InitStructure.ADC_ScanConvMode = DISABLE;
ADC_InitStructure.ADC_ContinuousConvMode = DISABLE;
ADC_InitStructure.ADC_ExternalTrigConvEdge = ADC_ExternalTrigConvEdge_None;
//ADC_InitStructure.ADC_ExternalTrigConv = ;
ADC_InitStructure.ADC_DataAlign = ADC_DataAlign_Right;
ADC_InitStructure.ADC_NbrOfConversion = 1;
ADC_Init(ADC1, &ADC_InitStructure);
// Enable ADC1
ADC_Cmd(ADC1, ENABLE);
// Enable ADC1 reset calibration register
//ADC_ResetCalibration(ADC1);
// Check the end of ADC1 reset calibration register
while(ADC_GetSoftwareStartConvStatus(ADC1));
// Start ADC1 calibration
//ADC_StartCalibration(ADC1);
// Check the end of ADC1 calibration
//while(ADC_GetCalibrationStatus(ADC1));
// Initialize analogOutput module
analogOutputInit();
/* Configure the NVIC Preemption Priority Bits */
/* 4 bits for pre-emption priority(0-15 PreemptionPriority) and 0 bits for subpriority(0 SubPriority) */
NVIC_PriorityGroupConfig(NVIC_PriorityGroup_4);
}