/*
* Platform specific initialization
*/
static void plf_init(void)
{
/* Set default Hardware interrupts priority */
__nds32__mtsr(PRI1_DEFAULT, NDS32_SR_INT_PRI);
__nds32__mtsr(PRI2_DEFAULT, NDS32_SR_INT_PRI2);
/* Mask all HW interrupts except SWI */
__nds32__mtsr((1 << IRQ_SYS_TICK_VECTOR) | (1 << IRQ_SWI_VECTOR), NDS32_SR_INT_MASK2);
/* Reset the PIT (timers) */
REG32(PIT_INT_EN) = 0; /* disable all timer interrupt */
REG32(PIT_CH_EN) = 0; /* disable all timer */
REG32(PIT_INT_ST) = -1; /* clear pending events */
REG32(PIT_CHNx_LOAD(0)) = 0; /* clean channel 0 reload */
REG32(PIT_CHNx_LOAD(1)) = 0; /* clean channel 1 reload */
REG32(PIT_CHNx_LOAD(2)) = 0; /* clean channel 2 reload */
REG32(PIT_CHNx_LOAD(3)) = 0; /* clean channel 3 reload */
}
void _nds32_init_mem(void) //The function is weak (optional)
{
/* System without SDRAM. Use data local memory as system memory. */
extern char __data_start;
register unsigned int dlmsize;
dlmsize = DLM_SIZE;//0x1000 << ((__nds32__mfsr(NDS32_SR_DLMB) >> 1) & 0xf);
#ifndef DLM_8K
__nds32__mtsr(ILM_BASE|1, NDS32_SR_ILMB);
__nds32__isb();
#endif
/* Set DLM base to .data start address and enable it */
__nds32__mtsr(DLM_BASE|1, NDS32_SR_DLMB);//__nds32__mtsr((unsigned)&__data_start|1, NDS32_SR_DLMB);
__nds32__dsb();
/* Update stack pointer to end of DLM
* We suppose the .data + .bss + stack less then DLM size */
__nds32__set_current_sp((unsigned)&__data_start + dlmsize);
}
void __attribute__ ((optimize("Os"))) __cpu_init()
{
unsigned int tmp;
/* turn on BTB */
tmp = 0x0;
__nds32__mtsr(tmp, NDS32_SR_MISC_CTL);
#if defined(NDS32_BASELINE_V3M) && defined(USE_C_EXT)
/* set IVIC, vector size: 16 bytes, base: 0x0
* If we use v3m toolchain and want to use
* C extension please use USE_C_EXT in CFLAGS
*/
__nds32__mtsr(0x4001, NDS32_SR_IVB);
#else
/* set IVIC, vector size: 4 bytes, base: 0x0
* If we use v3m toolchain and want to use
* assembly version please don't use USE_C_EXT
* in CFLAGS */
__nds32__mtsr(0x0, NDS32_SR_IVB);
#endif
/* Set PSW INTL to 0 */
tmp = __nds32__mfsr(NDS32_SR_PSW);
tmp = tmp & 0xfffffff9;
#if (defined(NDS32_BASELINE_V3M) || defined(NDS32_BASELINE_V3))
/* Set PSW CPL to 7 to allow any priority */
tmp = tmp | 0x70008;
#endif
__nds32__mtsr(tmp, NDS32_SR_PSW);
__nds32__dsb();
#if (defined(NDS32_BASELINE_V3M) || defined(NDS32_BASELINE_V3))
/* Set PPL2FIX_EN to 0 to enable Programmable
* Priority Level */
__nds32__mtsr(0x0, NDS32_SR_INT_CTRL);
/* set priority HW0: 0, HW1: 1, HW2: 2, HW3: 3
* HW4-: 0 */
__nds32__mtsr(0xe4, NDS32_SR_INT_PRI);
#endif
/* enable FPU if the CPU support FPU */
#if defined(NDS32_EXT_FPU_DP) || defined(NDS32_EXT_FPU_SP)
tmp = __nds32__mfsr(NDS32_SR_FUCOP_EXIST);
if ((tmp & 0x80000001) == 0x80000001) {
tmp = __nds32__mfsr(NDS32_SR_FUCOP_CTL);
__nds32__mtsr((tmp | 0x1), NDS32_SR_FUCOP_CTL);
}
#endif
return;
}
/*
* mask/unmask priority >= _irqs_ interrupts
* used in ISR & gie diable
*/
uint32_t hal_intc_irq_mask(int _irqs_)
{
uint32_t prv_msk = __nds32__mfsr(NDS32_SR_INT_MASK2);
if (_irqs_ == -1 )
{
__nds32__mtsr(0, NDS32_SR_INT_MASK2);
}
else if (_irqs_ < 32 )
{
SR_CLRB32(NDS32_SR_INT_MASK2,_irqs_);
}
else
{
DEBUG(1,1,"_irqs_:%d, is invalid!\r\n",_irqs_);
return -1;
}
return prv_msk;
}
/*
* All AE210P hardware initialization
*/
void hardware_init(void)
{
mmu_init(); /* mmu/cache */
plf_init(); /* Perform any platform specific initializations */
#if (defined(CONFIG_CPU_ICACHE_ENABLE) || defined(CONFIG_CPU_DCACHE_ENABLE))
unsigned int reg;
/* Invalid ICache */
nds32_icache_flush();
/* Invalid DCache */
nds32_dcache_invalidate();
/* Enable I/Dcache */
reg = (__nds32__mfsr(NDS32_SR_CACHE_CTL) & ~CACHE_CTL_MSK) | CACHE_CTL_CACHE_ON;
__nds32__mtsr(reg, NDS32_SR_CACHE_CTL);
#endif
}
void _nds32_init_mem(void)
{
/* Enable DLM */
__nds32__mtsr(EDLM_BASE | 0x1, NDS32_SR_DLMB);
__nds32__dsb();
}
void hal_intc_irq_set_priority( uint32_t _prio1_, uint32_t _prio2_ )
{
__nds32__mtsr(_prio1_, NDS32_SR_INT_PRI);
__nds32__mtsr(_prio2_, NDS32_SR_INT_PRI2);
}
void hal_intc_irq_disable_all()
{
__nds32__mtsr(0x0,NDS32_SR_INT_MASK2);
}
void hal_intc_irq_clean_all()
{
__nds32__mtsr(-1,NDS32_SR_INT_PEND2);
}
void hal_intc_irq_unmask(uint32_t _msk_)
{
__nds32__mtsr( _msk_ , NDS32_SR_INT_MASK2);
}
