static void usb_enable_module(int en) { if (en){ __raw_bits_or(BIT_6, AHB_CTL3); __raw_bits_and(~BIT_9, GR_CLK_GEN5); //__raw_bits_or(BIT_5, AHB_CTL0); }else { __raw_bits_and(~BIT_6, AHB_CTL3); __raw_bits_or(BIT_9, GR_CLK_GEN5); __raw_bits_and(~BIT_5, AHB_CTL0); } }
void udc_power_on(void) { __raw_bits_or(BIT_8, USB_PHY_CTRL); __raw_bits_or(BIT_17, USB_PHY_CTRL); __raw_bits_and(~BIT_16, USB_PHY_CTRL); __raw_bits_and(~(BIT_13 | BIT_12), USB_PHY_CTRL); __raw_bits_or(BIT_15 | BIT_14, USB_PHY_CTRL); __raw_bits_and(~BIT_1, AHB_CTL3); __raw_bits_and(~BIT_2, AHB_CTL3); usb_startup(); }
static void sdhci_sprd_set_base_clock(unsigned int clock) { unsigned long flags; /* don't bother if the clock is going off. */ if (clock == 0) return; if (clock > SDIO_MAX_CLK) clock = SDIO_MAX_CLK; //Select the clk source of SDIO __raw_bits_and(~(BIT_17|BIT_18), GR_CLK_GEN5); if (clock >= SDIO_BASE_CLK_96M) { //default is 96M ; } else if (clock >= SDIO_BASE_CLK_64M) { __raw_bits_or((1<<17), GR_CLK_GEN5); } else if (clock >= SDIO_BASE_CLK_48M) { __raw_bits_or((2<<17), GR_CLK_GEN5); } else { __raw_bits_or((3<<17), GR_CLK_GEN5); } printf("after set sd clk, CLK_GEN5:%x\r\n", __raw_readl(GR_CLK_GEN5)); return; }
static int32_t sprdfb_dispc_uninit(struct sprdfb_device *dev) { FB_PRINT("sprdfb:[%s]\n",__FUNCTION__); //disable DISPC clock __raw_bits_and(~(1<<22), AHB_CTL0); return 0; }
static void usb_startup(void) { usb_enable_module(1); dwc_mdelay(10); usb_ldo_switch(0); __raw_bits_and(~BIT_1, AHB_CTL3); __raw_bits_and(~BIT_2, AHB_CTL3); usb_ldo_switch(1); __raw_bits_or(BIT_6, AHB_CTL3); //__raw_bits_or(BIT_7, AHB_SOFT_RST); //dwc_mdelay(10); //__raw_bits_and(~BIT_7, AHB_SOFT_RST); __raw_bits_or(BIT_5, AHB_CTL0); dwc_mdelay(30); }
static int32_t sprdfb_dispc_early_init(struct sprdfb_device *dev) { FB_PRINT("sprdfb:[%s]\n", __FUNCTION__); //select DISPC clock source __raw_bits_and(~(1<<1), AHB_DISPC_CLK); //pll_src=256M __raw_bits_and(~(1<<2), AHB_DISPC_CLK); //set DISPC divdior __raw_bits_and(~(1<<3), AHB_DISPC_CLK); //div=0 __raw_bits_and(~(1<<4), AHB_DISPC_CLK); __raw_bits_and(~(1<<5), AHB_DISPC_CLK); //select DBI clock source __raw_bits_and(~(1<<9), AHB_DISPC_CLK); //pll_src=256M __raw_bits_and(~(1<<10), AHB_DISPC_CLK); //set DBI divdior __raw_bits_and(~(1<<11), AHB_DISPC_CLK); //div=0 __raw_bits_and(~(1<<12), AHB_DISPC_CLK); __raw_bits_and(~(1<<13), AHB_DISPC_CLK); //select DPI clock source __raw_bits_and(~(1<<17), AHB_DISPC_CLK); //pll_src=384M __raw_bits_and(~(1<<18), AHB_DISPC_CLK); //set DPI divdior __raw_bits_and(~(1<<19), AHB_DISPC_CLK); //div=10, dpi_clk = pll_src/(10+1) __raw_bits_or((1<<20), AHB_DISPC_CLK); __raw_bits_and(~(1<<21), AHB_DISPC_CLK); __raw_bits_or((1<<22), AHB_DISPC_CLK); __raw_bits_and(~(1<<23), AHB_DISPC_CLK); __raw_bits_and(~(1<<24), AHB_DISPC_CLK); __raw_bits_and(~(1<<25), AHB_DISPC_CLK); __raw_bits_and(~(1<<26), AHB_DISPC_CLK); //enable dispc matric clock __raw_bits_or((1<<9), AHB_CTL2); //core_clock_en __raw_bits_or((1<<11), AHB_CTL2); //matrix clock en //enable DISPC clock __raw_bits_or(1<<22, AHB_CTL0); printf("0x20900200 = 0x%x\n", __raw_readl(0x20900200)); printf("0x20900208 = 0x%x\n", __raw_readl(0x20900208)); printf("0x20900220 = 0x%x\n", __raw_readl(0x20900220)); dispc_reset(); dispc_module_enable(); is_first_frame = 1; return 0; }