void __iar_program_start(void)
{
/* the calls below are normally made in IAR cstartup */
__iar_init_core();
__iar_init_vfp();
/* the calls below are normally made in IAR cmain
*
* The function "__low_level_init" is a user overrideable hook
* that does nothing by default. Returning zero means that
* ram initialization should be skipped. Skipping ram initialization
* is not allowed by mbed.
*
* The function "__iar_data_init3" is an IAR function which
* initializes ram.
*
*/
__low_level_init();
__iar_data_init3();
/* mbed specific code */
mbed_heap_start = (unsigned char *)__section_begin("HEAP");
mbed_heap_size = (uint32_t)__section_size("HEAP");
mbed_stack_isr_start = (unsigned char *)__section_begin("CSTACK");
mbed_stack_isr_size = (uint32_t)__section_size("CSTACK");
mbed_init();
mbed_rtos_start();
}
void SwitchToOverlay2(void)
{
char * from = __section_begin("MYOVERLAY2_init");
char * to = __section_begin("MYOVERLAY");
long size = __section_size ("MYOVERLAY2_init");
memcpy(to, from, size);//__section_size("MYOVERLAY2_init"));
}
void MMU_CreateTranslationTable(void)
{
mmu_region_attributes_Type region;
#if defined ( __ICCARM__ )
#pragma section=".intvec"
#pragma section=".rodata"
#pragma section=".rwdata"
#pragma section=".bss"
Image$$VECTORS$$Base = (uint32_t) __section_begin(".intvec");
Image$$VECTORS$$Limit= ((uint32_t)__section_begin(".intvec")+(uint32_t)__section_size(".intvec"));
Image$$RO_DATA$$Base = (uint32_t) __section_begin(".rodata");
Image$$RO_DATA$$Limit= ((uint32_t)__section_begin(".rodata")+(uint32_t)__section_size(".rodata"));
Image$$RW_DATA$$Base = (uint32_t) __section_begin(".rwdata");
Image$$RW_DATA$$Limit= ((uint32_t)__section_begin(".rwdata")+(uint32_t)__section_size(".rwdata"));
Image$$RW_IRAM1$$Base = (uint32_t) __section_begin(".bss");
Image$$RW_IRAM1$$Limit= ((uint32_t)__section_begin(".bss")+(uint32_t)__section_size(".bss"));
#endif
/*
* Generate descriptors. Refer to core_ca.h to get information about attributes
*
*/
//Create descriptors for Vectors, RO, RW, ZI sections
section_normal(Sect_Normal, region);
section_normal_cod(Sect_Normal_Cod, region);
section_normal_ro(Sect_Normal_RO, region);
section_normal_rw(Sect_Normal_RW, region);
//Create descriptors for peripherals
section_device_ro(Sect_Device_RO, region);
section_device_rw(Sect_Device_RW, region);
section_normal_nc(Sect_Normal_NC, region);
//Create descriptors for 64k pages
page64k_device_rw(Page_L1_64k, Page_64k_Device_RW, region);
//Create descriptors for 4k pages
page4k_device_rw(Page_L1_4k, Page_4k_Device_RW, region);
/*
* Define MMU flat-map regions and attributes
*
*/
//Create 4GB of faulting entries
MMU_TTSection (&Image$$TTB$$ZI$$Base, 0, 4096, DESCRIPTOR_FAULT);
// R7S72100 memory map.
MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_NORFLASH_BASE0 , 64, Sect_Normal_RO);
MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_NORFLASH_BASE1 , 64, Sect_Normal_RO);
MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_SDRAM_BASE0 , 64, Sect_Normal_RW);
MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_SDRAM_BASE1 , 64, Sect_Normal_RW);
MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_USER_AREA0 , 64, Sect_Normal_RW);
MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_USER_AREA1 , 64, Sect_Normal_RW);
MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_SPI_IO0 , 64, Sect_Normal_RO);
MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_SPI_IO1 , 64, Sect_Normal_RO);
MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_ONCHIP_SRAM_BASE , 10, Sect_Normal_RW);
MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_SPI_MIO_BASE , 1, Sect_Device_RW);
MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_BSC_BASE , 1, Sect_Device_RW);
MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_PERIPH_BASE0 , 3, Sect_Device_RW);
MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_PERIPH_BASE1 , 49, Sect_Device_RW);
#if defined( __ICCARM__ )
//Define Image
MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)Image$$RO_DATA$$Base , RO_DATA_SIZE , Sect_Normal_Cod);
MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)Image$$VECTORS$$Base , VECTORS_SIZE , Sect_Normal_Cod);
MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)Image$$RW_DATA$$Base , RW_DATA_SIZE , Sect_Normal_RW);
MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)Image$$RW_IRAM1$$Base, RW_IRAM1_SIZE, Sect_Normal_RW);
#else
//Define Image
MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RO_DATA$$Base , RO_DATA_SIZE , Sect_Normal_Cod);
MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$VECTORS$$Base , VECTORS_SIZE , Sect_Normal_Cod);
MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RW_DATA$$Base , RW_DATA_SIZE , Sect_Normal_RW);
MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RW_IRAM1$$Base, RW_IRAM1_SIZE, Sect_Normal_RW);
#endif
#if defined( __CC_ARM )
MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_ONCHIP_SRAM_NC_BASE , 10, Sect_Normal_NC);
#elif defined ( __ICCARM__ )
MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_ONCHIP_SRAM_NC_BASE , 10, Sect_Normal_NC);
#else
MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RW_DATA_NC$$Base, RW_DATA_NC_SIZE, Sect_Normal_NC);
MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$ZI_DATA_NC$$Base, ZI_DATA_NC_SIZE, Sect_Normal_NC);
#endif
/* Set location of level 1 page table
; 31:14 - Translation table base addr (31:14-TTBCR.N, TTBCR.N is 0 out of reset)
; 13:7 - 0x0
; 6 - IRGN[0] 0x0 (Inner WB WA)
; 5 - NOS 0x0 (Non-shared)
; 4:3 - RGN 0x1 (Outer WB WA)
; 2 - IMP 0x0 (Implementation Defined)
; 1 - S 0x0 (Non-shared)
; 0 - IRGN[1] 0x1 (Inner WB WA) */
__set_TTBR0(((uint32_t)&Image$$TTB$$ZI$$Base) | 9);
__ISB();
/* Set up domain access control register
; We set domain 0 to Client and all other domains to No Access.
; All translation table entries specify domain 0 */
__set_DACR(1);
__ISB();
}
/**
* @brief Main program
* @param None
* @retval None
*/
int main(void)
{
/*!< At this stage the microcontroller clock setting is already configured,
this is done through SystemInit() function which is called from startup
file startup_stm32f446xx.s) before to branch to application main.
To reconfigure the default setting of SystemInit() function, refer to
system_stm32f4xx.c file
*/
uint32_t address = 0, step = 0x00;
/* Configure QSPI GPIO */
QSPI_GPIO_Config();
/* Initialize DMA ----------------------------------------------------------*/
DMA_StructInit(&DMA_InitStructure);
DMA_DeInit(QSPI_DMA_STREAM);
/*DMA configuration*/
DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)&QUADSPI->DR ;
DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
DMA_InitStructure.DMA_Channel = DMA_Channel_3;
/* Initialize QuadSPI ------------------------------------------------------*/
QSPI_StructInit(&QSPI_InitStructure);
QSPI_InitStructure.QSPI_SShift = QSPI_SShift_HalfCycleShift;
QSPI_InitStructure.QSPI_Prescaler = 0x01; /* 90 MHZ */
QSPI_InitStructure.QSPI_CKMode = QSPI_CKMode_Mode0;
QSPI_InitStructure.QSPI_CSHTime = QSPI_CSHTime_2Cycle;
QSPI_InitStructure.QSPI_FSize = 0x18;
QSPI_InitStructure.QSPI_FSelect = QSPI_FSelect_1;
QSPI_InitStructure.QSPI_DFlash = QSPI_DFlash_Disable;
QSPI_Init(&QSPI_InitStructure);
/* Initialize Command Config -----------------------------------------------*/
QSPI_ComConfig_StructInit(&QSPI_ComConfig_InitStructure);
QSPI_ComConfig_InitStructure.QSPI_ComConfig_ADSize = QSPI_ComConfig_ADSize_24bit;
QSPI_ComConfig_InitStructure.QSPI_ComConfig_IMode = QSPI_ComConfig_IMode_1Line;
QSPI_ComConfig_InitStructure.QSPI_ComConfig_ABMode = QSPI_ComConfig_ABMode_NoAlternateByte;
QSPI_ComConfig_InitStructure.QSPI_ComConfig_DDRMode = QSPI_ComConfig_DDRMode_Disable;
QSPI_ComConfig_InitStructure.QSPI_ComConfig_SIOOMode = QSPI_ComConfig_SIOOMode_Disable;
QSPI_ComConfig_InitStructure.QSPI_ComConfig_DHHC = QSPI_ComConfig_DHHC_Enable;
QSPI_ComConfig_StructInit(&QSPI_ComConfig_InitStructure);
QSPI_Cmd(ENABLE);
while(1)
{
switch(step)
{
case 0:
/* Enable write operations ---------------------------------------------*/
QSPI_Cmd(ENABLE);
QSPI_WriteEnable();
/* Erasing Sequence ----------------------------------------------------*/
QSPI_ComConfig_StructInit(&QSPI_ComConfig_InitStructure);
QSPI_ComConfig_InitStructure.QSPI_ComConfig_ADSize = QSPI_ComConfig_ADSize_24bit;
QSPI_ComConfig_InitStructure.QSPI_ComConfig_IMode = QSPI_ComConfig_IMode_1Line;
QSPI_ComConfig_InitStructure.QSPI_ComConfig_ADMode = QSPI_ComConfig_ADMode_1Line;
QSPI_ComConfig_InitStructure.QSPI_ComConfig_DMode = QSPI_ComConfig_DMode_NoData;
QSPI_ComConfig_InitStructure.QSPI_ComConfig_FMode = QSPI_ComConfig_FMode_Indirect_Write;
QSPI_ComConfig_InitStructure.QSPI_ComConfig_Ins = SECTOR_ERASE_CMD;
QSPI_ComConfig_Init(&QSPI_ComConfig_InitStructure);
/* Set sector address to erase */
QSPI_SetAddress(address);
while(QSPI_GetFlagStatus(QSPI_FLAG_TC) == RESET)
{}
step++;
break;
case 1:
/* Configure automatic polling mode to wait for end of erase -----------*/
QSPI_AutoPollingMemReady();
#if defined(__CC_ARM)
FlashAddr = (uint8_t *)(&Load$$QSPI$$Base);
MAXTransferSize = (uint32_t)(&Load$$QSPI$$Length);
#elif defined(__ICCARM__)
FlashAddr = (uint8_t *)(__section_begin(".qspi_init"));
MAXTransferSize = __section_size(".qspi_init");
#elif defined(__GNUC__)
FlashAddr = (uint8_t *)(&_qspi_init_base);
MAXTransferSize = (uint32_t)((uint8_t *)(&_qspi_init_length));
#endif
step++;
break;
case 2:
/* Enable write operations ---------------------------------------------*/
QSPI_WriteEnable();
QSPI_DMACmd(ENABLE);
/* Writing Sequence ----------------------------------------------------*/
QSPI_SetDataLength(MAXTransferSize);
QSPI_ComConfig_StructInit(&QSPI_ComConfig_InitStructure);
QSPI_ComConfig_InitStructure.QSPI_ComConfig_IMode = QSPI_ComConfig_IMode_1Line;
QSPI_ComConfig_InitStructure.QSPI_ComConfig_ADMode = QSPI_ComConfig_ADMode_1Line;
QSPI_ComConfig_InitStructure.QSPI_ComConfig_DMode = QSPI_ComConfig_DMode_4Line;
QSPI_ComConfig_InitStructure.QSPI_ComConfig_FMode = QSPI_ComConfig_FMode_Indirect_Write;
QSPI_ComConfig_InitStructure.QSPI_ComConfig_ADSize = QSPI_ComConfig_ADSize_32bit;
QSPI_ComConfig_InitStructure.QSPI_ComConfig_Ins = QUAD_IN_FAST_PROG_CMD;
QSPI_ComConfig_InitStructure.QSPI_ComConfig_DummyCycles = 0;
QSPI_ComConfig_Init(&QSPI_ComConfig_InitStructure);
/* DMA channel Tx Configuration */
DMA_InitStructure.DMA_BufferSize = MAXTransferSize;
DMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)FlashAddr;
DMA_InitStructure.DMA_DIR = DMA_DIR_MemoryToPeripheral;
DMA_InitStructure.DMA_Priority = DMA_Priority_Low;
DMA_Init(QSPI_DMA_STREAM, &DMA_InitStructure);
DMA_Cmd(QSPI_DMA_STREAM, ENABLE);
/* Wait for the end of Transfer */
while(DMA_GetFlagStatus(QSPI_DMA_STREAM, QSPI_DMA_FLAG_TC) == RESET)
{}
DMA_ClearFlag(QSPI_DMA_STREAM, QSPI_DMA_FLAG_TC);
QSPI_AbortRequest();
DMA_Cmd(QSPI_DMA_STREAM, DISABLE);
QSPI_DMACmd(DISABLE);
step++;
break;
case 3:
/* Configure automatic polling mode to wait for end of program ---------*/
QSPI_AutoPollingMemReady();
step++;
break;
case 4:
/* Reading Sequence ----------------------------------------------------*/
QSPI_TimeoutCounterCmd(DISABLE);
QSPI_MemoryMappedMode_SetTimeout(0);
QSPI_ComConfig_InitStructure.QSPI_ComConfig_ADSize = QSPI_ComConfig_ADSize_32bit;
QSPI_ComConfig_InitStructure.QSPI_ComConfig_FMode = QSPI_ComConfig_FMode_Memory_Mapped;
QSPI_ComConfig_InitStructure.QSPI_ComConfig_ADMode = QSPI_ComConfig_ADMode_4Line;
QSPI_ComConfig_InitStructure.QSPI_ComConfig_IMode = QSPI_ComConfig_IMode_1Line;
QSPI_ComConfig_InitStructure.QSPI_ComConfig_DMode = QSPI_ComConfig_DMode_4Line;
QSPI_ComConfig_InitStructure.QSPI_ComConfig_Ins = QUAD_INOUT_FAST_READ_4_BYTE_ADDR_CMD;
QSPI_ComConfig_InitStructure.QSPI_ComConfig_DummyCycles = DUMMY_CLOCK_CYCLES_READ_QUAD;
QSPI_ComConfig_Init(&QSPI_ComConfig_InitStructure);
GpioToggle();
break;
default :
TransferStatus = FAILED;
break;
}
}
}
/**
* @brief Main program
* @param None
* @retval None
*/
int main(void)
{
QSPI_CommandTypeDef sCommand;
QSPI_MemoryMappedTypeDef sMemMappedCfg;
__IO uint32_t qspi_addr = 0;
uint8_t *flash_addr;
__IO uint8_t step = 0;
uint32_t max_size, size;
/* STM32F4xx HAL library initialization:
- Configure the Flash prefetch, instruction and Data caches
- Systick timer is configured by default as source of time base, but user
can eventually implement his proper time base source (a general purpose
timer for example or other time source), keeping in mind that Time base
duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and
handled in milliseconds basis.
- Set NVIC Group Priority to 4
- Low Level Initialization: global MSP (MCU Support Package) initialization
*/
HAL_Init();
/* Configure the system clock to 180 MHz */
SystemClock_Config();
BSP_LED_Init(LED1);
BSP_LED_Init(LED3);
/* Initialize QuadSPI ------------------------------------------------------ */
QSPIHandle.Instance = QUADSPI;
HAL_QSPI_DeInit(&QSPIHandle);
QSPIHandle.Init.ClockPrescaler = 1;
QSPIHandle.Init.FifoThreshold = 4;
QSPIHandle.Init.SampleShifting = QSPI_SAMPLE_SHIFTING_HALFCYCLE;
QSPIHandle.Init.FlashSize = QSPI_FLASH_SIZE;
QSPIHandle.Init.ChipSelectHighTime = QSPI_CS_HIGH_TIME_2_CYCLE;
QSPIHandle.Init.ClockMode = QSPI_CLOCK_MODE_0;
if (HAL_QSPI_Init(&QSPIHandle) != HAL_OK)
{
Error_Handler();
}
sCommand.InstructionMode = QSPI_INSTRUCTION_1_LINE;
sCommand.AddressSize = QSPI_ADDRESS_24_BITS;
sCommand.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
sCommand.DdrMode = QSPI_DDR_MODE_DISABLE;
sCommand.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;
sCommand.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;
flash_addr = 0;
size = 0 ;
#if defined(__CC_ARM)
max_size = (uint32_t)(&Load$$QSPI$$Length);
#elif defined(__ICCARM__)
max_size = __section_size(".qspi_init");
#elif defined(__GNUC__)
max_size = (uint32_t)((uint8_t *)(&_qspi_init_length));
#endif
while(1)
{
switch(step)
{
case 0:
CmdCplt = 0;
/* Enable write operations ------------------------------------------- */
QSPI_WriteEnable(&QSPIHandle);
/* Erasing Sequence -------------------------------------------------- */
sCommand.Instruction = SECTOR_ERASE_CMD;
sCommand.AddressMode = QSPI_ADDRESS_1_LINE;
sCommand.Address = qspi_addr;
sCommand.DataMode = QSPI_DATA_NONE;
sCommand.DummyCycles = 0;
if (HAL_QSPI_Command_IT(&QSPIHandle, &sCommand) != HAL_OK)
{
Error_Handler();
}
step++;
break;
case 1:
if(CmdCplt != 0)
{
CmdCplt = 0;
StatusMatch = 0;
/* Configure automatic polling mode to wait for end of erase ------- */
QSPI_AutoPollingMemReady(&QSPIHandle);
/* Initialize the variables for the data writing ------------------- */
#if defined(__CC_ARM)
flash_addr = (uint8_t *)(&Load$$QSPI$$Base);
#elif defined(__ICCARM__)
flash_addr = (uint8_t *)(__section_begin(".qspi_init"));
#elif defined(__GNUC__)
flash_addr =(uint8_t *)(&_qspi_init_base);
#endif
/* Copy only one page if the section is bigger */
if (max_size > QSPI_PAGE_SIZE)
{
size = QSPI_PAGE_SIZE;
}
else
{
size = max_size;
}
step++;
}
break;
case 2:
if(StatusMatch != 0)
{
StatusMatch = 0;
TxCplt = 0;
/* Enable write operations ----------------------------------------- */
QSPI_WriteEnable(&QSPIHandle);
/* Writing Sequence ------------------------------------------------ */
sCommand.Instruction = EXT_QUAD_IN_FAST_PROG_CMD;
sCommand.AddressMode = QSPI_ADDRESS_4_LINES;
sCommand.Address = qspi_addr;
sCommand.DataMode = QSPI_DATA_4_LINES;
sCommand.NbData = size;
if (HAL_QSPI_Command(&QSPIHandle, &sCommand, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
{
Error_Handler();
}
if (HAL_QSPI_Transmit_DMA(&QSPIHandle, flash_addr) != HAL_OK)
{
Error_Handler();
}
step++;
}
break;
case 3:
if(TxCplt != 0)
{
TxCplt = 0;
StatusMatch = 0;
/* Configure automatic polling mode to wait for end of program ----- */
QSPI_AutoPollingMemReady(&QSPIHandle);
step++;
}
break;
case 4:
if(StatusMatch != 0)
{
qspi_addr += size;
flash_addr += size;
/* Check if a new page writing is needed */
if (qspi_addr < max_size)
{
/* Update the remaining size if it is less than the page size */
if ((qspi_addr + size) > max_size)
{
size = max_size - qspi_addr;
}
step = 2;
}
else
{
StatusMatch = 0;
RxCplt = 0;
/* Configure Volatile Configuration register (with new dummy cycles) */
QSPI_DummyCyclesCfg(&QSPIHandle);
/* Reading Sequence ------------------------------------------------ */
sCommand.Instruction = QUAD_INOUT_FAST_READ_CMD;
sCommand.DummyCycles = DUMMY_CLOCK_CYCLES_READ_QUAD;
sMemMappedCfg.TimeOutActivation = QSPI_TIMEOUT_COUNTER_DISABLE;
if (HAL_QSPI_MemoryMapped(&QSPIHandle, &sCommand, &sMemMappedCfg) != HAL_OK)
{
Error_Handler();
}
step++;
}
}
break;
case 5:
/* Execute the code from QSPI memory ------------------------------- */
GpioToggle();
break;
default :
Error_Handler();
}
}
}
/**********************************************************
* Uses the flashloader to upload an application to
* the target. This function will first upload the
* flashloader, then communicate with the flashloader
* to send the program. If successful the application
* will be started when this function returns.
*
* @param verify
* If true, verify the application after it has been
* written to flash
**********************************************************/
void flashWithFlashloader(bool verify)
{
uint32_t startTime = DWT->CYCCNT;
uint32_t time;
#pragma section="fw_section"
int fwSize = __section_size("fw_section");
printf("Preparing to upload firmware (%d bytes)\n", fwSize);
/* Upload flashloader */
#pragma section="flashloader_section"
uploadFlashloader((uint32_t *)__section_begin("flashloader_section"), __section_size("flashloader_section"));
/* Check that flashloader is ready */
verifyFlashloaderReady();
#if defined(SWD_FAST)
/* Doing one Mass Erase is faster than erasing individual pages,
* but it will case wear on all pages.
* Only available on GG, LG, WG and ZG devices. */
uint32_t part = readMem((uint32_t)&(DEVINFO->PART));
uint32_t family = (part & _DEVINFO_PART_DEVICE_FAMILY_MASK) >> _DEVINFO_PART_DEVICE_FAMILY_SHIFT;
if ( family == _DEVINFO_PART_DEVICE_FAMILY_GG ||
family == _DEVINFO_PART_DEVICE_FAMILY_LG ||
family == _DEVINFO_PART_DEVICE_FAMILY_WG ||
family == _DEVINFO_PART_DEVICE_FAMILY_ZG )
{
printf("Erasing entire flash\n");
sendMassEraseCmd();
}
else
{
erasePagesWithFlashloader(fwSize);
}
#else
erasePagesWithFlashloader(fwSize);
#endif
printf("Uploading firmware image\n");
uploadImageToFlashloader(__section_begin("fw_section"), fwSize);
/* Verify that the uploaded image is equal to the original */
if ( verify )
{
if ( verifyFirmware((uint32_t *)__section_begin("fw_section"), fwSize) ) {
printf("Application verified\n");
} else {
RAISE(SWD_ERROR_VERIFY_FW_FAILED);
}
}
/* Calculate the total time spent flashing */
time = DWT->CYCCNT - startTime;
printf("Total time: %f s (%f kB/s)\n", (time/48e6), ((float)fwSize/1024) / (time/48e6));
printf("Starting application\n");
/* Reset target to start application */
resetTarget();
}