/** * _read_divisor() - get current divisor applied to parent clock (from hdwr) * @clk: OMAP struct clk to use. * * Read the current divisor register value for @clk that is programmed * into the hardware, convert it into the actual divisor value, and * return it; or return 0 on error. */ static u32 _read_divisor(struct clk *clk) { u32 v; if (!clk->clksel || !clk->clksel_mask) return 0; v = __raw_readl(clk->clksel_reg); v &= clk->clksel_mask; v >>= __ffs(clk->clksel_mask); return _clksel_to_divisor(clk, v); }
/** * _read_divisor() - get current divisor applied to parent clock (from hdwr) * @clk: OMAP struct clk to use. * @mul: Output parameter. Multiplier for current rate. Typically 0. * * Read the current divisor register value for @clk that is programmed * into the hardware, convert it into the actual divisor value, and * return it; or return 0 on error. */ static u32 _read_divisor(struct clk *clk, u32 *mul) { u32 v, div; if (!clk->clksel || !clk->clksel_mask || !mul) return 0; v = __raw_readl(clk->clksel_reg); v &= clk->clksel_mask; v >>= __ffs(clk->clksel_mask); div = _clksel_to_divisor(clk, v, mul); return div; }