void up_enable_irq(int irq)
{
if ((unsigned)irq < NR_IRQS)
{
_irq_enable(irq, 1);
}
}
/* Open WSS for usage */
boolean wss_open()
{
__dpmi_meminfo struct_info;
if (!wss.ok)
if (!wss_detect())
return FALSE;
if (wss.open)
return FALSE;
/* Now lock the wss structure in memory */
struct_info.address = __djgpp_base_address + (unsigned long)&wss;
struct_info.size = sizeof(wss);
if (__dpmi_lock_linear_region(&struct_info))
return FALSE;
/* Hook the WSS IRQ */
wss.irq_handle =
irq_hook(wss.irq, wss_irq, (long)wss_irq_end - (long)wss_irq);
if (!wss.irq_handle) {
__dpmi_unlock_linear_region(&struct_info);
return FALSE;
}
/* Enable the interrupt */
irq_enable(wss.irq_handle);
if (wss.irq > 7)
_irq_enable(2);
wss.open++;
return TRUE;
}
/**
* @brief Setup the given timer
*/
int timer_init(tim_t dev, unsigned long freq, timer_cb_t cb, void *arg)
{
/* at the moment, the timer can only run at 1MHz */
if (freq != 1000000ul) {
return -1;
}
/* configure GCLK0 to feed TC0 & TC1*/;
GCLK->PCHCTRL[TC0_GCLK_ID].reg |= GCLK_PCHCTRL_CHEN | GCLK_PCHCTRL_GEN_GCLK0;
while (!(GCLK->PCHCTRL[TC0_GCLK_ID].reg & GCLK_PCHCTRL_CHEN)) {}
/* select the timer and enable the timer specific peripheral clocks */
switch (dev) {
#if TIMER_0_EN
case TIMER_0:
if (TIMER_0_DEV.CTRLA.bit.ENABLE) {
return 0;
}
MCLK->APBCMASK.reg |= MCLK_APBCMASK_TC0;
/* reset timer */
TIMER_0_DEV.CTRLA.bit.SWRST = 1;
while (TIMER_0_DEV.SYNCBUSY.bit.SWRST) {}
TIMER_0_DEV.CTRLA.reg |= TC_CTRLA_MODE_COUNT32 | /* choosing 32 bit mode */
TC_CTRLA_PRESCALER(4) | /* sourced by 4MHz with Presc 4 results in 1MHz*/
TC_CTRLA_PRESCSYNC_RESYNC; /* initial prescaler resync */
break;
#endif
case TIMER_UNDEFINED:
default:
return -1;
}
/* save callback */
config[dev].cb = cb;
config[dev].arg = arg;
/* enable interrupts for given timer */
_irq_enable(dev);
timer_start(dev);
return 0;
}
/**
* @brief Setup the given timer
*
*/
int timer_init(tim_t dev, unsigned long freq, timer_cb_t cb, void *arg)
{
cc2538_gptimer_t *gptimer = timer_config[dev].dev;
unsigned int gptimer_num;
uint32_t chan_mode;
DEBUG("%s(%u, %lu, %p, %p)\n", __FUNCTION__, dev, freq, cb, arg);
if (dev >= TIMER_NUMOF) {
return -1;
}
gptimer_num = GPTIMER_GET_NUM(gptimer);
/* Save the callback function: */
assert(gptimer_num < GPTIMER_NUMOF);
config[gptimer_num].cb = cb;
config[gptimer_num].arg = arg;
/* Enable the clock for this timer: */
SYS_CTRL_RCGCGPT |= (1 << gptimer_num);
/* Disable this timer before configuring it: */
gptimer->cc2538_gptimer_ctl.CTL = 0;
if (timer_config[dev].cfg == GPTMCFG_32_BIT_TIMER) {
/* Count up in periodic mode */
chan_mode = TnCMIE | TnCDIR | GPTIMER_PERIODIC_MODE;
if (timer_config[dev].channels > 1) {
DEBUG("Invalid timer_config. Multiple channels are available only in 16-bit mode.");
return -1;
}
if (freq != sys_clock_freq()) {
DEBUG("In 32-bit mode, the GPTimer frequency must equal the system clock frequency (%u).", sys_clock_freq());
return -1;
}
} else {
/* Count down in periodic mode */
chan_mode = TnCMIE | GPTIMER_PERIODIC_MODE;
}
gptimer->CFG = timer_config[dev].cfg;
gptimer->cc2538_gptimer_tamr.TAMR = chan_mode;
switch (timer_config[dev].channels) {
case 1:
/* Enable the timer: */
gptimer->cc2538_gptimer_ctl.CTL = TAEN;
break;
case 2:
gptimer->cc2538_gptimer_tbmr.TBMR = chan_mode;
gptimer->TAILR = LOAD_VALUE;
gptimer->TBILR = LOAD_VALUE;
uint32_t prescaler = sys_clock_freq();
prescaler += freq / 2;
prescaler /= freq;
if (prescaler > 0) prescaler--;
if (prescaler > 255) prescaler = 255;
gptimer->TAPR = prescaler;
gptimer->TBPR = prescaler;
/* Enable the timer: */
gptimer->cc2538_gptimer_ctl.CTL = TBEN | TAEN;
break;
}
/* Enable interrupts for given timer: */
_irq_enable(dev);
return 0;
}
/**
* @brief Setup the given timer
*
*/
int timer_init(tim_t tim, unsigned long freq, timer_cb_t cb, void *arg)
{
DEBUG("%s(%u, %lu, %p, %p)\n", __FUNCTION__, tim, freq, cb, arg);
if (tim >= TIMER_NUMOF) {
return -1;
}
/* Save the callback function: */
isr_ctx[tim].cb = cb;
isr_ctx[tim].arg = arg;
/* Enable the clock for this timer: */
SYS_CTRL->RCGCGPT |= (1 << tim);
/* Disable this timer before configuring it: */
dev(tim)->CTL = 0;
uint32_t prescaler = 0;
uint32_t chan_mode = TNMIE | GPTIMER_PERIODIC_MODE;
if (timer_config[tim].cfg == GPTMCFG_32_BIT_TIMER) {
/* Count up in periodic mode */
chan_mode |= TNCDIR ;
if (timer_config[tim].chn > 1) {
DEBUG("Invalid timer_config. Multiple channels are available only in 16-bit mode.");
return -1;
}
if (freq != sys_clock_freq()) {
DEBUG("In 32-bit mode, the GPTimer frequency must equal the system clock frequency (%u).\n",
(unsigned)sys_clock_freq());
return -1;
}
}
else if (timer_config[tim].cfg == GPTMCFG_16_BIT_TIMER) {
prescaler = sys_clock_freq();
prescaler += freq / 2;
prescaler /= freq;
if (prescaler > 0) prescaler--;
if (prescaler > 255) prescaler = 255;
dev(tim)->TAPR = prescaler;
dev(tim)->TAILR = LOAD_VALUE;
}
else {
DEBUG("timer_init: invalid timer config must be 16 or 32Bit mode!\n");
return -1;
}
dev(tim)->CFG = timer_config[tim].cfg;
dev(tim)->CTL = TAEN;
dev(tim)->TAMR = chan_mode;
if (timer_config[tim].chn > 1) {
dev(tim)->TBMR = chan_mode;
dev(tim)->TBPR = prescaler;
dev(tim)->TBILR = LOAD_VALUE;
/* Enable the timer: */
dev(tim)->CTL = TBEN | TAEN;
}
/* Enable interrupts for given timer: */
_irq_enable(tim);
return 0;
}
void up_disable_irq(int irq)
{
if((unsigned)irq < NR_IRQS)
_irq_enable(irq, 0);
}
void irq_disable(enum irq_nr nr)
{
_irq_enable(nr, 0);
}
void irq_enable(enum irq_nr nr)
{
_irq_enable(nr, 1);
}