void setup_PIC(){
_Cli();
_outb(0x21,0xFC);
_outb(0xA1,0xFF);
_Sti();
return;
}
unsigned char read_temperature() {
if( !wait_ec(_WRITE) )
_outb(0x66, 0x80);
if( !wait_ec(_WRITE) )
_outb(0x62, TEMPERATURE);
if( !wait_ec(_READ) )
return(_inb(0x62));
}
void set_fan(unsigned char speed) {
if( !wait_ec(_WRITE) )
_outb(0x66, 0x81);
if( !wait_ec(_WRITE) )
_outb(0x62, FAN);
if( !wait_ec(_WRITE) )
_outb(0x62, speed);
}
void update_cursor(SHELL* current_shell)
{
unsigned short position = current_shell->cursor;
if (position != 0) {
_outb(0x3D4, 0x0F);
_outb(0x3D5, (unsigned char)(position/2));
_outb(0x3D4, 0x0E);
_outb(0x3D5, (unsigned char )(((position/2)>>8)));
}
int play_speaker(uint16_t f) {
int freq = 1193182 / f;
_outb(0xb6, 0x43); /* sets the mode of the PIT. 0xb6 = 10/11/011/0 */
_outb((short int)freq, 0x42); /* sets frec on channel 2 of the PIT */
_outb((short int)(freq >> 8), 0x42);
uint8_t tmp = _inb(0x61);
tmp = tmp | 3;
_outb(tmp, 0x61);
return 1;
}
void remapIRQ(){
_outb(0x20, 0x11);
_outb(0xA0, 0x11);
// PIC 1 Vector Offset 0x20
_outb(0x21, 0x20);
// PIC 2 Vector Offset 0x28
_outb(0xA1, 0x28);
_outb(0x21, 0x04);
_outb(0xA1, 0x02);
_outb(0x21, 0x01);
_outb(0xA1, 0x01);
_outb(0x21, 0x0);
_outb(0xA1, 0x0);
return;
}
void
_dense_outb(char val, unsigned long port)
{
if ((port & ~0xffff) == 0) return _outb(val, port);
write_mem_barrier();
*(volatile CARD8 *)port = val;
}
/**
* Initialize disk device driver. Reserves memory for data structures
* and register driver to the interrupt handler.
*
* @param desc Pointer to the PCI IO device descriptor of the controller
*
* @return Pointer to the device structure of the controller
*/
void ide_write(uint8_t channel, uint8_t reg, uint8_t data)
{
/* */
if(reg > 0x07 && reg < 0x0C)
ide_write(channel, IDE_REGISTER_CTRL, 0x80 | ide_channels[channel].irq);
/* */
if(reg < 0x08)
_outb((uint16_t)(ide_channels[channel].base + reg), data);
else if(reg < 0x0C)
_outb((uint16_t)(ide_channels[channel].base + reg - 0x06), data);
else if(reg < 0x0E)
_outb((uint16_t)(ide_channels[channel].ctrl + reg - 0x0A), data);
else if(reg < 0x16)
_outb((uint16_t)(ide_channels[channel].busm + reg - 0x0E), data);
if(reg > 0x07 && reg < 0x0C)
ide_write(channel, IDE_REGISTER_CTRL, ide_channels[channel].irq);
}
/*************************************************************
*initialize_pics
* Inicializa los PICS, el 1 como Master el 2 como slave
* y les coloca los offset enviados
* Recibe: Offset1 para el PIC1
* Offset2 para el PIC2
**************************************************************/
void initialize_pics(int offset_pic1, int offset_pic2){
unsigned char mask1 = _inb(PIC1_DATA);
unsigned char mask2 = _inb(PIC2_DATA);
_outb(PIC1_COMMAND, ICW1);
_outb(PIC2_COMMAND, ICW1);
_outb(PIC1_DATA, offset_pic1);
_outb(PIC2_DATA, offset_pic2);
_outb(PIC1_DATA, 4);
_outb(PIC2_DATA, 2);
_outb(PIC1_DATA, ICW4_8086);
_outb(PIC2_DATA, ICW4_8086);
_outb(PIC1_DATA, mask1);
_outb(PIC2_DATA, mask2);
}
void VM_setreg(int index, VMVALUE value)
{
switch (index) {
case RG_DIRA:
_dirb(0xffffffff, value);
break;
case RG_OUTA:
_outb(0xffffffff, value);
break;
}
}
void send_departing_buffer(int cursor) {
while (is_transmit_empty() == 0)
;
int i = 0;
for (i = 0; i < cursor; i++) {
_Cli();
_outb(SERIAL_PORT, departing_buffer[i]); //no quiero ser interrumpido mientras escribo en el P.S
_Sti();
}
}
int32_t ide_pio_readwrite(uint8_t rw, uint8_t drive, uint64_t lba,
uint8_t *buf, uint32_t numsectors)
{
/* Sanity */
if(rw > 1 || buf == 0)
return 0;
/* Vars */
uint64_t addr = lba;
uint8_t lba_mode = 1; /* 1 - 28, 2 - 48 */
uint8_t cmd = 0;
uint8_t channel = ide_devices[drive].channel;
uint32_t slave = ide_devices[drive].drive;
uint32_t bus = ide_channels[channel].base;
uint32_t words = (numsectors * 512) / 2;
/* Make sure IRQs are disabled */
_outb(bus + IDE_REGISTER_CTRL, 0x02);
/* Wait for it to acknowledge */
ide_wait(channel, 0);
/* Determine LBA mode */
if(ide_devices[drive].flags & 0x1)
lba_mode = 2;
/* Read or write? */
if(rw == IDE_READ)
cmd = IDE_COMMAND_PIO_READ;
else
cmd = IDE_COMMAND_PIO_WRITE;
/* Reset IRQ counter */
ide_channels[channel].irq_wait = 0;
/* Now, send the command */
if(lba_mode == 2)
{
/* LBA48 */
cmd += 0x04;
/* Send it */
ide_write(channel, IDE_REGISTER_HDDSEL, (0x40 | (slave << 4)));
ide_wait(channel, 0);
ide_write(channel, IDE_REGISTER_SECCOUNT0, 0x00);
ide_write(channel, IDE_REGISTER_LBA0, (uint8_t)((addr >> 24) & 0xFF));
ide_write(channel, IDE_REGISTER_LBA1, (uint8_t)((addr >> 32) & 0xFF));
ide_write(channel, IDE_REGISTER_LBA2, (uint8_t)((addr >> 40) & 0xFF));
}
void outb(unsigned long port, unsigned char val)
{
int fd = ia64_port_to_fd(port);
if (!fd) {
_outb(val, port & 0xffff);
goto out;
}
if (lseek(fd, port & 0xffff, SEEK_SET) == -1) {
ErrorF("I/O lseek failed\n");
goto out;
}
if (write(fd, &val, 1) != 1) {
ErrorF("I/O write failed\n");
goto out;
}
out:
return;
}
/**********************************************
kmain()
Punto de entrada de código C.
*************************************************/
kmain() {
int i, num;
// Paging.start(0x200000);
// init_malloc();
initialize_pics(0x20,0x70);
setup_IDT_entry(&idt[0x70], 0x08, (dword) & _rtc, ACS_INT, 0);
_cache_init();
hdd_init();
/* CARGA DE IDT CON LA RUTINA DE ATENCION DE IRQ0 */
setup_IDT_entry (&idt[0x00], 0x08, (dword)&_int_00_hand, ACS_INT, 0);
setup_IDT_entry (&idt[0x01], 0x08, (dword)&_int_01_hand, ACS_INT, 0);
setup_IDT_entry (&idt[0x02], 0x08, (dword)&_int_02_hand, ACS_INT, 0);
setup_IDT_entry (&idt[0x03], 0x08, (dword)&_int_03_hand, ACS_INT, 0);
setup_IDT_entry (&idt[0x04], 0x08, (dword)&_int_04_hand, ACS_INT, 0);
setup_IDT_entry (&idt[0x05], 0x08, (dword)&_int_05_hand, ACS_INT, 0);
setup_IDT_entry (&idt[0x06], 0x08, (dword)&_int_06_hand, ACS_INT, 0);
setup_IDT_entry (&idt[0x07], 0x08, (dword)&_int_07_hand, ACS_INT, 0);
setup_IDT_entry (&idt[0x08], 0x08, (dword)&_int_08_hand, ACS_INT, 0);
setup_IDT_entry (&idt[0x09], 0x08, (dword)&_int_09_hand, ACS_INT, 0);
setup_IDT_entry (&idt[0x0A], 0x08, (dword)&_int_0A_hand, ACS_INT, 0);
setup_IDT_entry (&idt[0x0B], 0x08, (dword)&_int_0B_hand, ACS_INT, 0);
setup_IDT_entry (&idt[0x0C], 0x08, (dword)&_int_0C_hand, ACS_INT, 0);
setup_IDT_entry (&idt[0x0D], 0x08, (dword)&_int_0D_hand, ACS_INT, 0);
setup_IDT_entry (&idt[0x0E], 0x08, (dword)&_int_0E_hand, ACS_INT, 0);
setup_IDT_entry (&idt[0x0F], 0x08, (dword)&_int_0F_hand, ACS_INT, 0);
setup_IDT_entry (&idt[0x10], 0x08, (dword)&_int_10_hand, ACS_INT, 0);
setup_IDT_entry (&idt[0x11], 0x08, (dword)&_int_11_hand, ACS_INT, 0);
setup_IDT_entry (&idt[0x12], 0x08, (dword)&_int_12_hand, ACS_INT, 0);
setup_IDT_entry (&idt[0x13], 0x08, (dword)&_int_13_hand, ACS_INT, 0);
setup_IDT_entry (&idt[0x14], 0x08, (dword)&_int_14_hand, ACS_INT, 0);
setup_IDT_entry (&idt[0x15], 0x08, (dword)&_int_15_hand, ACS_INT, 0);
setup_IDT_entry (&idt[0x16], 0x08, (dword)&_int_16_hand, ACS_INT, 0);
setup_IDT_entry (&idt[0x17], 0x08, (dword)&_int_17_hand, ACS_INT, 0);
setup_IDT_entry (&idt[0x18], 0x08, (dword)&_int_18_hand, ACS_INT, 0);
setup_IDT_entry (&idt[0x19], 0x08, (dword)&_int_19_hand, ACS_INT, 0);
setup_IDT_entry (&idt[0x1A], 0x08, (dword)&_int_1A_hand, ACS_INT, 0);
setup_IDT_entry (&idt[0x1B], 0x08, (dword)&_int_1B_hand, ACS_INT, 0);
setup_IDT_entry (&idt[0x1C], 0x08, (dword)&_int_1C_hand, ACS_INT, 0);
setup_IDT_entry (&idt[0x1D], 0x08, (dword)&_int_1D_hand, ACS_INT, 0);
setup_IDT_entry (&idt[0x1E], 0x08, (dword)&_int_1E_hand, ACS_INT, 0);
setup_IDT_entry (&idt[0x1F], 0x08, (dword)&_int_1F_hand, ACS_INT, 0);
// setup_IDT_entry (&idt[0x20], 0x08, (dword)&_int_20_hand, ACS_INT, 0);
// setup_IDT_entry (&idt[0x21], 0x08, (dword)&_int_21_hand, ACS_INT, 0);
setup_IDT_entry(&idt[0x20], 0x08, (dword) & _timer_tick_hand, ACS_INT, 0);
/* CARGA DE IDT CON LA RUTINA DE ATENCION DE IRQ1 */
setup_IDT_entry(&idt[0x21], 0x08, (dword) & _KB_hand, ACS_INT, 0);
/* CARGA DE IDT CON LA RUTINA DE ATENCION DE int80h */
setup_IDT_entry(&idt[0x80], 0x08, (dword) & _int_80_hand, ACS_INT, 0);
/* CARGA DE IDT CON LA RUTINA DE ATENCION DE int79h */
setup_IDT_entry(&idt[0x79], 0x08, (dword) & _int_79_hand, ACS_INT, 0);
/* Carga de IDTR */
idtr.base = 0;
idtr.base += (dword) & idt;
idtr.limit = sizeof(idt) - 1;
_lidt(&idtr);
Cli();
int rate = 0x06;
_outb(0x70, 0x0A); //set index to register A
char prev=_inb(0x71); //get initial value of register A
_outb(0x70, 0x0A); //reset index to A
_outb(0x71, (prev & 0xF0) | rate); //write only our rate to A. Note, rate is the bottom 4 bits.
init_paging();
scheduler_init();
/* Habilito interrupcion de timer tick*/
_mascaraPIC1(0xFC);
_mascaraPIC2(0xFE);
_outb(0x70, 0x0B); //set the index to register B
prev= _inb(0x71); //read the current value of register B
_outb(0x70, 0x0B); //set the index again(a read will reset the index to register D)
_outb(0x71, prev | 0x40); //write the previous value or'd with 0x40. This turns on bit 6 of register B
Sti();
idle = create_process("idle", idle_main, 0, 0, 0, 0, 0, 0, 0, NULL, 0);
// We soon exit out of here :)
while (1);
}
void stop_speaker() {
uint8_t tmp = _inb(0x61);
tmp = tmp | 252;
_outb(tmp, 0x61);
}
/**********************************************
kmain()
Punto de entrada de código C.
*************************************************/
kmain() {
int i, num;
setup_IDT_entry(&idt[0x70], 0x08, (dword) & _rtc, ACS_INT, 0);
/* CARGA DE IDT CON LA RUTINA DE ATENCION DE IRQ0 */
setup_IDT_entry(&idt[0x08], 0x08, (dword) & _int_08_hand, ACS_INT, 0);
/* CARGA DE IDT CON LA RUTINA DE ATENCION DE IRQ1 */
setup_IDT_entry(&idt[0x09], 0x08, (dword) & _int_09_hand, ACS_INT, 0);
/* CARGA DE IDT CON LA RUTINA DE ATENCION DE int80h */
setup_IDT_entry(&idt[0x80], 0x08, (dword) & _int_80_hand, ACS_INT, 0);
/* CARGA DE IDT CON LA RUTINA DE ATENCION DE int79h */
setup_IDT_entry(&idt[0x79], 0x08, (dword) & _int_79_hand, ACS_INT, 0);
/* Carga de IDTR */
idtr.base = 0;
idtr.base += (dword) & idt;
idtr.limit = sizeof(idt) - 1;
_lidt(&idtr);
Cli();
int rate = 0x06;
_outb(0x70, 0x0A); //set index to register A
char prev=_inb(0x71); //get initial value of register A
_outb(0x70, 0x0A); //reset index to A
_outb(0x71, (prev & 0xF0) | rate); //write only our rate to A. Note, rate is the bottom 4 bits.
scheduler_init();
/* Habilito interrupcion de timer tick*/
_mascaraPIC1(0x00);
_mascaraPIC2(0x00);
_outb(0x70, 0x0B); //set the index to register B
prev= _inb(0x71); //read the current value of register B
_outb(0x70, 0x0B); //set the index again(a read will reset the index to register D)
_outb(0x71, prev | 0x40); //write the previous value or'd with 0x40. This turns on bit 6 of register B
Sti();
idle = create_process("idle", idle_main, 0, 0, 0, 0, 0, 0, 0, NULL, 0);
// We soon exit out of here :)
while (1);
}
void k_reboot(){
k_disable();
k_rebootanimation();
_outb(0x64, 0xFE);
return;
}
void k_reboot(){
_outb(0x64, 0xFE);
return;
}
