static int cs75xx_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
int value)
{
_set_gpio_direction(chip, offset, GPIO_CFG_OUT);
cs75xx_gpio_set(chip, offset, value);
return 0;
}
static int gemini_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
int value)
{
_set_gpio_direction(chip, offset, 1);
gemini_gpio_set(chip, offset, value);
return 0;
}
/*!
* Release ownership for a GPIO pin
* @param pin a name defined by \b iomux_pin_name_t
*/
void mxc_free_gpio(iomux_pin_name_t pin)
{
struct gpio_port *port;
u32 index, gpio = IOMUX_TO_GPIO(pin);
if (check_gpio(gpio) < 0)
return;
port = get_gpio_port(gpio);
index = GPIO_TO_INDEX(gpio);
spin_lock(&port->lock);
if ((!(port->reserved_map & (1 << index)))) {
printk(KERN_ERR "GPIO port %d, pin %d wasn't reserved!\n",
port->num, index);
dump_stack();
spin_unlock(&port->lock);
return;
}
port->reserved_map &= ~(1 << index);
port->irq_is_level_map &= ~(1 << index);
_set_gpio_direction(port, index, 1);
_set_gpio_irqenable(port, index, 0);
_clear_gpio_irqstatus(port, index);
spin_unlock(&port->lock);
}
void omap_set_gpio_direction(int gpio, int is_input)
{
struct gpio_bank *bank;
if (check_gpio(gpio) < 0)
return;
bank = get_gpio_bank(gpio);
_set_gpio_direction(bank, get_gpio_index(gpio), is_input);
}
static int gpio_input(struct gpio_chip *chip, unsigned offset)
{
struct gpio_bank *bank;
unsigned long flags;
bank = container_of(chip, struct gpio_bank, chip);
spin_lock_irqsave(&bank->lock, flags);
_set_gpio_direction(bank, offset, 1);
spin_unlock_irqrestore(&bank->lock, flags);
return 0;
}
/**
* Set gpio direction as input
*/
int gpio_direction_input(unsigned gpio)
{
const struct gpio_bank *bank;
if (check_gpio(gpio) < 0)
return -1;
bank = get_gpio_bank(gpio);
_set_gpio_direction(bank, get_gpio_index(gpio), 1);
return 0;
}
/*!
* Exported function to set a GPIO pin's direction
* @param pin a name defined by \b iomux_pin_name_t
* @param is_input 1 (or non-zero) for input; 0 for output
*/
void mxc_set_gpio_direction(iomux_pin_name_t pin, int is_input)
{
struct gpio_port *port;
u32 gpio = IOMUX_TO_GPIO(pin);
if (check_gpio(gpio) < 0)
return;
port = get_gpio_port(gpio);
spin_lock(&port->lock);
_set_gpio_direction(port, GPIO_TO_INDEX(gpio), is_input);
spin_unlock(&port->lock);
}
/**
* Set gpio direction as output
*/
int gpio_direction_output(unsigned gpio, int value)
{
const struct gpio_bank *bank;
if (check_gpio(gpio) < 0)
return -1;
bank = get_gpio_bank(gpio);
_set_gpio_dataout(bank, get_gpio_index(gpio), value);
_set_gpio_direction(bank, get_gpio_index(gpio), 0);
return 0;
}
int pnx_gpio_set_direction(int gpio, int is_input)
{
unsigned long flags, index;
struct gpio_bank *bank;
if (!check_gpio(gpio))
return -EINVAL;
bank = get_gpio_bank(gpio);
index = get_gpio_index(gpio);
if (!check_gpio_requested(bank, index))
return -EINVAL;
spin_lock_irqsave(&bank->lock, flags);
_set_gpio_direction(bank, index, is_input);
spin_unlock_irqrestore(&bank->lock, flags);
return 0;
}
static void _reset_gpio(struct gpio_bank *bank, int gpio)
{
_set_gpio_direction(bank, get_gpio_index(gpio), 1);
}
static int gemini_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
{
_set_gpio_direction(chip, offset, 0);
return 0;
}
static int __init pnx_gpio_probe(struct platform_device *pdev)
{
int i,j;
int gpio = 0;
struct gpio_bank *bank;
struct gpio_data *data = pdev->dev.platform_data;
unsigned long flags;
initialized = 1;
printk(KERN_INFO "PNX GPIO\n");
gpio_bank_desc = data->gpio_bank_desc;
gpio_bank_count = data->nb_banks;
for (i = 0; i < gpio_bank_count; i++) {
int gpio_count = 32; /* 32 GPIO per bank */
bank = &gpio_bank_desc[i];
bank->reserved_map = 0; /* must always be initialized */
spin_lock_init(&bank->lock);
/* check if bank is managed by PNX GPIO driver */
if ((bank->gpio_base != 0) && (bank->mux_base != 0)) {
bank->chip.request = pnx_gpio_acquire;
bank->chip.free = pnx_gpio_release;
bank->chip.direction_input = gpio_input;
bank->chip.get = gpio_get;
bank->chip.direction_output = gpio_output;
bank->chip.set = gpio_set;
bank->chip.to_irq = gpio_2irq;
bank->chip.label = "gpio";
bank->chip.base = gpio;
bank->chip.ngpio = gpio_count;
gpiochip_add(&bank->chip);
}
gpio += gpio_count;
}
#ifdef CONFIG_MODEM_BLACK_BOX
/* set init value */
printk(KERN_INFO "PNX GPIO initialize SCON\n");
/* configure MUX and PAD settings */
for (i = 0; i< SCON_REGISTER_NB; i++)
__raw_writel(pnx_scon_init_config[i].scon_reg_value,
pnx_scon_init_config[i].scon_reg_addr);
/* configure GPIO direction and value */
for (i=0; i < gpio_to_configure; i++) {
int index;
bank = get_gpio_bank(pnx_gpio_init_config[i].gpio);
index = get_gpio_index(pnx_gpio_init_config[i].gpio);
_set_gpio_direction(bank, index, pnx_gpio_init_config[i].dir);
_write_gpio_pin(bank, index, pnx_gpio_init_config[i].value);
}
/* reserve GPIO used by Modem */
for (i = 0; i < pnx_modem_gpio_reserved_nb; i++) {
int index;
bank = get_gpio_bank(pnx_modem_gpio_reserved[i]);
index = get_gpio_index(pnx_modem_gpio_reserved[i]);
bank->reserved_map |= (1 << index);
}
/* configure EXTINT used by modem */
for (i = 0; i< pnx_modem_extint_nb; i++)
__raw_writel(pnx_extint_init_config[i].reg_value,
pnx_extint_init_config[i].reg_addr);
printk(KERN_INFO "PNX GPIO Driver\n");
#endif
/* for extint */
for (j = IRQ_COUNT; j < IRQ_COUNT + NR_EXTINT; j++) {
set_irq_chip(j, &gpio_irq_chip);
set_irq_handler(j, handle_simple_irq);
set_irq_flags(j, IRQF_VALID);
}
hw_raw_local_irq_save ( flags );
/* mask all EXT IRQ sources before registring handler */
/* read status */
j = __raw_readl(EXTINT_STATUS_REG) & __raw_readl(EXTINT_ENABLE3_REG);
/* clear IRQ source(s)*/
__raw_writel(j, EXTINT_STATUS_REG);
__raw_writel(0, EXTINT_ENABLE3_REG);
/* set irq in low level */
set_irq_type(IRQ_EXTINT3, IRQF_TRIGGER_LOW);
/* chained GPIO-IRQ on EXTINT3 */
set_irq_chained_handler(IRQ_EXTINT3, gpio_irq_handler);
hw_raw_local_irq_restore ( flags );
return 0;
}
static int cs75xx_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
{
_set_gpio_direction(chip, offset, GPIO_CFG_IN);
return 0;
}
