void MAT_Multiply2(float A[8][8],
float B[8][8], float C[8][8])
{_ssdm_SpecArrayDimSize(A,8);_ssdm_SpecArrayDimSize(B,8);_ssdm_SpecArrayDimSize(C,8);
_ssdm_op_SpecDataflowPipeline(-1, "");
#33 "dct/matrixmath.c"
_ssdm_SpecArrayPartition( B, 1, "COMPLETE", 0, "");
#33 "dct/matrixmath.c"
unsigned char i, j, k;
float temp;
float A_cached_row[8];
_ssdm_SpecArrayPartition( A_cached_row, 0, "COMPLETE", 0, "");
#36 "dct/matrixmath.c"
Row: for (i=0; i<8; i++)
//Cache the whole row of matrix A
RowCaching: for (k=0;k<8;k++)
_ssdm_op_SpecPipeline(1, 1, 1, 0, "");
#41 "dct/matrixmath.c"
A_cached_row[k]=A[i][k];
Col: for (j=0; j<8; j++)
{
_ssdm_op_SpecPipeline(1, 1, 1, 0, "");
#44 "dct/matrixmath.c"
//Make sure the data is fully cached to avoid multiple read.
temp = 0;
// if (j==0)
// {
//Cache the whole row of matrix A
// RowCaching: for (k=0;k<MAT_SIZE;k++)
// A_cached_row[k]=A[i][k];
// }
Product: for (k=0; k<8; k++)
{
temp += A_cached_row[k] * B[k][j];
}
C[i][j] = temp;
}
}
void adder_top(int *a, int *b, int *c, int n)
{
_ssdm_op_SpecInterface(a, "ap_fifo", 0, 0, 0, 0, "", "", "");
#5 "hls_demo/.settings/adder.c"
_ssdm_op_SpecInterface(a, "ap_fifo", 0, 0, 0, 0, "", "", "");
_ssdm_op_SpecInterface(b, "ap_fifo", 0, 0, 0, 0, "", "", "");
_ssdm_op_SpecInterface(c, "ap_fifo", 0, 0, 0, 0, "", "", "");
int i;
int arrayA[1000];
_ssdm_SpecArrayPartition( arrayA, 1, "CYCLIC", 10, "");
#10 "hls_demo/.settings/adder.c"
int arrayB[1000];
_ssdm_SpecArrayPartition( arrayB, 1, "CYCLIC", 10, "");
#11 "hls_demo/.settings/adder.c"
int arrayC[1000];
_ssdm_SpecArrayPartition( arrayC, 1, "CYCLIC", 10, "");
#12 "hls_demo/.settings/adder.c"
loop_read: for (i=0;i<1000;i++)
{
if (i<n)
{
arrayA[i] = a[i];
arrayB[i] = b[i];
arrayC[i] = 0;
}
}
loop_add: for (i=0;i<1000;i++)
{
_ssdm_Unroll(1, 0, 10, "");
_ssdm_op_SpecPipeline(1, 1, 1, 0, "");
if (i<n)
arrayC[i] = (arrayA[i]+arrayB[i]);
}
loop_write: for (i=0;i<1000;i++)
{
_ssdm_op_SpecPipeline(1, 1, 1, 0, "");
if (i<n)
c[i] = arrayC[i];
}
}
int multi_axim(int *x, int *y){
_ssdm_op_SpecInterface(y, "m_axi", 0, 0, 0, 10, "", "slave", "");
_ssdm_op_SpecInterface(x, "m_axi", 0, 0, 0, 10, "", "slave", "");
_ssdm_op_SpecInterface(0, "s_axilite", 0, 0, 0, 0, "", "", "");
for (int i=0; i<10; i++){
_ssdm_op_SpecPipeline(1, 1, 1, 0, "");
y[i] = x[i] * (x[i] + 1);
}
return 0;
}
int fully_connected_single(int *w, int *b, int *x, int num_inputs, int output)
{
int offset = num_inputs * output;
int layer_out=0;
_ssdm_op_SpecPipeline(1, 1, 1, 0, "");
for(int i=0; i<num_inputs; i++)
layer_out += (w[offset+i]*x[i]) + b[offset+i];
return layer_out;
}
void MAT_Multiply(float A[8][8],
float B[8][8], float C[8][8])
{_ssdm_SpecArrayDimSize(A,8);_ssdm_SpecArrayDimSize(B,8);_ssdm_SpecArrayDimSize(C,8);
_ssdm_op_SpecDataflowPipeline(-1, "");
#6 "dct/matrixmath.c"
_ssdm_SpecArrayPartition( A, 1, "COMPLETE", 0, "");
#6 "dct/matrixmath.c"
unsigned char i, j, k;
float temp;
float B_cached[8][8];
_ssdm_SpecArrayPartition( B_cached, 0, "COMPLETE", 0, "");
#9 "dct/matrixmath.c"
LoadRow: for (i=0; i<8; i++){
LoadCol: for (j=0; j<8; j++){
_ssdm_op_SpecPipeline(1, 1, 1, 0, "");
#12 "dct/matrixmath.c"
B_cached[i][j]=B[i][j];
}
}
Row: for (i=0; i<8; i++)
Col: for (j=0; j<8; j++)
{
_ssdm_op_SpecPipeline(1, 1, 1, 0, "");
#19 "dct/matrixmath.c"
//Make sure the data is fully cached to avoid multiple read.
temp = 0;
Product: for (k=0; k<8; k++)
{
temp += A[i][k] * B_cached[k][j];
}
C[i][j] = temp;
}
}
void dma_filter(volatile unsigned int input_config[0x58], volatile unsigned int output_config[0x58],
volatile unsigned minAddress, bool reset){_ssdm_SpecArrayDimSize(input_config,0x58);_ssdm_SpecArrayDimSize(output_config,0x58);
_ssdm_op_SpecWire(&reset, "ap_none", 0, 0, 0, 1, "", "", "");
_ssdm_op_SpecWire(&minAddress, "s_axilite", 0, 0, 0, 0, "", "", "");
_ssdm_op_SpecWire(output_config, "m_axi", 0, 0, 0, 0, "", "", "");
_ssdm_op_SpecWire(input_config, "s_axilite", 0, 0, 0, 0, "", "", "");
if(!reset){
bool wait = true;
int i;
INITIAL_LOOP: for(i=0; i<0x58; i++){_ssdm_op_SpecLoopName("INITIAL_LOOP");_ssdm_RegionBegin("INITIAL_LOOP");
_ssdm_op_SpecPipeline(1, 1, 1, 0, "");
input_config[i] = 0;
_ssdm_RegionEnd("INITIAL_LOOP");}
bool read_ready = false;
bool write_ready = false;
unsigned read_config = 0;
bool read_enable = false;
bool read_interrupts = false;
unsigned read_address = 0;
unsigned read_length = 0;
unsigned write_config = 0;
bool write_enable = false;
bool write_interrupts = false;
unsigned write_address = 0;
unsigned write_length = 0;
WAIT_LOOP: while(wait){_ssdm_op_SpecLoopName("WAIT_LOOP");_ssdm_RegionBegin("WAIT_LOOP");
bool clear = false;
unsigned read_config = input_config[0];
bool read_enable = read_config &= 1;
bool read_interrupts = read_config &= 4096;
unsigned read_address = input_config[6];
unsigned read_length = input_config[10];
unsigned write_config = input_config[12];
bool write_enable = write_config &= 1;
bool write_interrupts = write_config &= 4096;
unsigned write_address = input_config[18];
unsigned write_length = input_config[22];
if(!read_enable && !write_enable){
continue;
} else if(read_address == 0 && write_address==0){
continue;
}
if(read_address > 0 && read_address < minAddress){
continue;
} else if(read_length == 0){
continue;
} else{
read_ready = true;
}
if(write_address > 0 && write_address < minAddress){
continue;
} else if(write_length == 0){
continue;
} else{
write_ready = true;
}
if(read_ready){
//enable read dma block
output_config[0] |= 1;
//enable read interupts
if(read_interrupts){
output_config[0] |= 4096;
}
//write source address
output_config[6] = read_address;
output_config[10] = read_length;
clear = true;
}
if(write_ready){
//enable s2mm on write dma block
output_config[12] |= 1;
//enable write interrupts
if(write_enable){
output_config[12] |= 4096;
}
//write dest address
output_config[18] = write_address;
output_config[22] = write_length;
clear = true;
}
if(clear){
CLEAR_LOOP: for(i=0; i<0x58; i++){_ssdm_op_SpecLoopName("CLEAR_LOOP");_ssdm_RegionBegin("CLEAR_LOOP");
_ssdm_op_SpecPipeline(1, 1, 1, 0, "");
input_config[i] = 0;
_ssdm_RegionEnd("CLEAR_LOOP");}
}
_ssdm_RegionEnd("WAIT_LOOP");}
}
}
