/* Return 0, 3, or 5 to indicate the previous sleep state. */ static int chipset_prev_sleep_state(struct chipset_power_state *ps) { /* Default to S0. */ int prev_sleep_state = ACPI_S0; if (ps->pm1_sts & WAK_STS) { switch (acpi_sleep_from_pm1(ps->pm1_cnt)) { case ACPI_S3: if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)) prev_sleep_state = ACPI_S3; break; case ACPI_S5: prev_sleep_state = ACPI_S5; break; } /* Clear SLP_TYP. */ outl(ps->pm1_cnt & ~(SLP_TYP), ACPI_BASE_ADDRESS + PM1_CNT); } if (ps->gen_pmcon1 & (PWR_FLR | SUS_PWR_FLR)) { prev_sleep_state = ACPI_S5; } return prev_sleep_state; }
int vboot_platform_is_resuming(void) { if (!(inw(ACPI_BASE_ADDRESS + PM1_STS) & WAK_STS)) return 0; return acpi_sleep_from_pm1(inl(ACPI_BASE_ADDRESS + PM1_CNT)) == ACPI_S3; }
enum acpi_sleep_state chipset_prev_sleep_state(void) { u32 pm1_sts; u32 pm1_cnt; u32 gen_pmcon1; enum acpi_sleep_state prev_sleep_state = ACPI_S0; /* Read Power State */ pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS); pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT); gen_pmcon1 = readl(PMC_BASE_ADDRESS + GEN_PMCON1); debug("PM1_STS = 0x%x PM1_CNT = 0x%x GEN_PMCON1 = 0x%x\n", pm1_sts, pm1_cnt, gen_pmcon1); if (pm1_sts & WAK_STS) prev_sleep_state = acpi_sleep_from_pm1(pm1_cnt); if (gen_pmcon1 & (PWR_FLR | SUS_PWR_FLR)) prev_sleep_state = ACPI_S5; return prev_sleep_state; }