static void r6532_write(int n, offs_t offset, UINT8 data) { if (offset & 4) { if (offset & 0x10) { r6532[n]->cleared = 0; switch (offset & 3) { case 0: r6532[n]->shift = 0; break; case 1: r6532[n]->shift = 3; break; case 2: r6532[n]->shift = 6; break; case 3: r6532[n]->shift = 10; break; } r6532[n]->target = activecpu_gettotalcycles() + (data << r6532[n]->shift); } else { r6532[n]->pa7_enable = (offset & 2) >> 1; r6532[n]->pa7_direction = offset & 1; } } else {
static READ8_HANDLER( tp84_sh_timer_r ) { /* main xtal 14.318MHz, divided by 4 to get the CPU clock, further */ /* divided by 2048 to get this timer */ /* (divide by (2048/2), and not 1024, because the CPU cycle counter is */ /* incremented every other state change of the clock) */ return (activecpu_gettotalcycles() / (2048/2)) & 0x0f; }
static READ8_HANDLER( mikie_sh_timer_r ) { int clock; #define TIMER_RATE 512 clock = activecpu_gettotalcycles() / TIMER_RATE; return clock; }
static UINT8 r6532_read_timer(int n, int enable) { int count = r6532[n]->target - activecpu_gettotalcycles(); if (count >= 0) { return count >> r6532[n]->shift; } else { if (count != -1)
static void r6532_write(int n, offs_t offset, UINT8 data) { if (offset & 4) { if (offset & 16) { r6532[n]->cleared = 0; switch (offset & 3) { case 0: r6532[n]->shift = 0; break; case 1: r6532[n]->shift = 3; break; case 2: r6532[n]->shift = 6; break; case 3: r6532[n]->shift = 10; break; } r6532[n]->target = activecpu_gettotalcycles() + (data << r6532[n]->shift); } else { logerror("Write to unimplemented 6532 #%d edge detect control\n", n); } } else { offset &= 3; switch (offset) { case 0: r6532_write_portA(n, data); break; case 1: r6532[n]->DDRA = data; break; case 2: r6532_write_portB(n, data); break; case 3: r6532[n]->DDRB = data; break; } } }
static READ_HANDLER( tempest_IN0_r ) { int res = readinputport(0); if (avgdvg_done()) res |= 0x40; /* Emulate the 3kHz source on bit 7 (divide 1.5MHz by 512) */ if (activecpu_gettotalcycles() & 0x100) res |= 0x80; return res; }
static void tms7000_service_timer1( void ) { if( --tms7000.t1_prescaler < 0 ) /* Decrement prescaler and check for underflow */ { tms7000.t1_prescaler = tms7000.pf[3] & 0x1f; /* Reload prescaler (5 bit) */ if( --tms7000.t1_decrementer < 0 ) /* Decrement timer1 register and check for underflow */ { tms7000.t1_decrementer = tms7000.pf[2]; /* Reload decrementer (8 bit) */ cpunum_set_input_line( cpu_getactivecpu(), TMS7000_IRQ2_LINE, HOLD_LINE); LOG( ("tms7000: trigger int2 (cycles: %d)\t%d\tdelta %d\n", activecpu_gettotalcycles(), activecpu_gettotalcycles() - tick, tms7000_cycles_per_INT2-(activecpu_gettotalcycles() - tick) ); tick = activecpu_gettotalcycles() ); /* Also, cascade out to timer 2 - timer 2 unimplemented */ }
static READ8_HANDLER( timeplt_portB_r ) { /* need to protect from totalcycles overflow */ static int last_totalcycles = 0; /* number of Z80 clock cycles to count */ static int clock; int current_totalcycles; current_totalcycles = activecpu_gettotalcycles(); clock = (clock + (current_totalcycles-last_totalcycles)) % 5120; last_totalcycles = current_totalcycles; return timeplt_timer[clock/512]; }
static READ8_HANDLER( megazone_portA_r ) { int clock,timer; /* main xtal 14.318MHz, divided by 8 to get the AY-3-8910 clock, further */ /* divided by 1024 to get this timer */ /* The base clock for the CPU and 8910 is NOT the same, so we have to */ /* compensate. */ /* (divide by (1024/2), and not 1024, because the CPU cycle counter is */ /* incremented every other state change of the clock) */ clock = activecpu_gettotalcycles() * 7159/12288; /* = (14318/8)/(18432/6) */ timer = (clock / (1024/2)) & 0x0f; /* low three bits come from the 8039 */ return (timer << 4) | i8039_status; }
static READ8_HANDLER( circusc_sh_timer_r ) { /* This port reads the output of a counter clocked from the CPU clock. * The CPU XTAL is 14.31818MHz divided by 4. It then goes through 10 * /2 stages to clock a 4 bit counter. The output of the counter goes * to D1-D4. * * The following: * clock = activecpu_gettotalcycles() >> 10; * return (clock & 0x0f) << 1; * Can be shortened to: */ int clock; clock = activecpu_gettotalcycles() >> 9; return clock & 0x1e; }
static WRITE32_HANDLER( speedup_w ) { COMBINE_DATA(speedup_data); /* see if the PC matches */ if ((activecpu_get_previouspc() & 0x1fffffff) == speedup_pc) { UINT32 curr_cycles = activecpu_gettotalcycles(); /* if less than 50 cycles from the last time, count it */ if (curr_cycles - last_cycles < 50) { loop_count++; /* more than 2 in a row and we spin */ if (loop_count > 2) cpu_spinuntil_int(); } else loop_count = 0; last_cycles = curr_cycles; } }
static READ8_HANDLER( pandoras_portB_r ) { return (activecpu_gettotalcycles() / 512) & 0x0f; }