Splitter::Splitter(MemorySystem* current ,const char *section ,const char *name)
/* constructor {{{1 */
: MemObj(section, name)
{
//routerLeft = new MRouter(this);
//lower_level = NULL;
//lower_levelLeft = NULL;
I(current);
SescConf->isInt(section, "numBanks");
numBanks = SescConf->getInt(section, "numBanks");
SescConf->isPower2(section,"numBanks");
numBankMask = numBanks -1;
scratchPort = (PortGeneric **)malloc(sizeof(PortGeneric *)*numBanks);
char cadena[1024];
for(size_t i=0;i<numBanks;i++) {
sprintf(cadena,"%s_%zu",name,i);
scratchPort[i] = PortGeneric::create(cadena, 1, 1);
}
lower_level = current->declareMemoryObj(section, "lowerLevel");
I(lower_level);
addLowerLevel(lower_level);
// FERMI specific...
lower_levelLeft = current->declareMemoryObj(section, "lowerLevelLeft");
I(lower_levelLeft);
addLowerLevel(lower_levelLeft);
}
AddressPrefetcher::AddressPrefetcher(MemorySystem* current
,const char *section
,const char *name)
: MemObj(section, name)
,bsize(SescConf->getLong(section, "bsize"))
,gms(current)
{
MemObj *lower_level = NULL;
SescConf->isLong(section, "numPorts");
SescConf->isLong(section, "portOccp");
SescConf->isLong(section, "bsize");
NumUnits_t num = SescConf->getLong(section, "numPorts");
TimeDelta_t occ = SescConf->getLong(section, "portOccp");
cachePort = PortGeneric::create(name, num, occ);
const char *cacheSection = SescConf->getCharPtr(section, "cache");
cache = CacheType::create(cacheSection, "", name);
SescConf->isLong(cacheSection, "hitDelay");
hitDelay = SescConf->getLong(cacheSection, "hitDelay");
SescConf->isLong(cacheSection, "missDelay");
missDelay = SescConf->getLong(cacheSection, "missDelay");
I(current);
lower_level = current->declareMemoryObj(section, k_lowerLevel);
if (lower_level != NULL)
addLowerLevel(lower_level);
}
MemCtrl::MemCtrl(MemorySystem* current, const char *device_descr_section,
const char *device_name)
: MemObj(device_descr_section, device_name),
busyUntil(0),
chWait("%s:chWait", device_name)
{
SescConf->isInt(device_descr_section, k_rowDelay);
SescConf->isInt(device_descr_section, k_dataXfer);
SescConf->isInt(device_descr_section, k_pagesPerBank);
SescConf->isInt(device_descr_section, k_numBanks);
SescConf->isInt(device_descr_section, k_numChips);
SescConf->isGT(device_descr_section, k_pagesPerBank, 0);
SescConf->isGT(device_descr_section, k_numBanks, 0);
SescConf->isGT(device_descr_section, k_numChips, 0);
rowAccessDelay = SescConf->getInt(device_descr_section, k_rowDelay);
hitDelay = SescConf->getInt(device_descr_section, k_dataXfer);
pagesPerBank = SescConf->getInt(device_descr_section, k_pagesPerBank);
numBanksPerChip= SescConf->getInt(device_descr_section, k_numBanks);
numChips = SescConf->getInt(device_descr_section, k_numChips);
if (!numChips)
numChips = 1;
numBanks = numChips * numBanksPerChip;
I(numBanks);
I(current);
for (uint16_t i = 0; i < numBanks; i++)
addLowerLevel(current->declareMemoryObj(device_descr_section, "bankType"));
}
Bus::Bus(MemorySystem* current ,const char *section ,const char *name)
/* constructor {{{1 */
: MemObj(section, name)
,delay(SescConf->getInt(section, "delay"))
{
//busyUpto = 0;
MemObj *lower_level = NULL;
SescConf->isInt(section, "numPorts");
SescConf->isInt(section, "portOccp");
SescConf->isInt(section, "delay");
NumUnits_t num = SescConf->getInt(section, "numPorts");
TimeDelta_t occ = SescConf->getInt(section, "portOccp");
char cadena[100];
sprintf(cadena,"Data%s", name);
dataPort = PortGeneric::create(cadena, num, occ);
sprintf(cadena,"Cmd%s", name);
cmdPort = PortGeneric::create(cadena, num, 1);
I(current);
lower_level = current->declareMemoryObj(section, "lowerLevel");
if (lower_level)
addLowerLevel(lower_level);
#ifdef ENABLE_NBSD
dcache = name[0]=='I'?false:true;
I(name[0] == 'I' || name[0] == 'D');
#endif
}
SMPSystemBus::SMPSystemBus(SMemorySystem *dms, const char *section, const char *name)
: MemObj(section, name)
{
MemObj *ll = NULL;
I(dms);
ll = dms->declareMemoryObj(section, "lowerLevel");
if (ll != NULL)
addLowerLevel(ll);
SescConf->isInt(section, "numPorts");
SescConf->isInt(section, "portOccp");
SescConf->isInt(section, "delay");
delay = SescConf->getInt(section, "delay");
char portName[100];
sprintf(portName, "%s_bus", name);
busPort = PortGeneric::create(portName,
SescConf->getInt(section, "numPorts"),
SescConf->getInt(section, "portOccp"));
#ifdef SESC_ENERGY
busEnergy = new GStatsEnergy("busEnergy", "SMPSystemBus", 0,
MemPower,
EnergyMgr::get(section,"BusEnergy",0));
#endif
}
ELM::ELM(MemorySystem *gms, const char *section, const char *name)
: MemObj(section, name)
,writeMiss("%s:writeMiss", name)
,readMiss("%s:readMiss", name)
,readHit("%s:readHit", name)
,writeHit("%s:writeHit", name)
,avgMissLat("%s_avgMissLat", name)
{
MemObj *lower_level = NULL;
lower_level = gms->declareMemoryObj(section, k_lowerLevel);
int32_t elmNumPorts = SescConf->getInt(section, k_numPorts);
int32_t elmPortOccp = SescConf->getInt(section, k_portOccp);
elmPort = PortGeneric::create(name, elmNumPorts, elmPortOccp);
SescConf->isInt(section, k_hitDelay);
hitDelay = SescConf->getInt(section, k_hitDelay);
SescConf->isInt(section, k_missDelay);
missDelay = SescConf->getInt(section, k_missDelay);
if (lower_level != NULL)
addLowerLevel(lower_level);
// char* elmPtr = (char*)malloc(K(nPage)*sizeof(char));
// memset(elmPtr,0,sizeof(char));
// baseAddr = (PAddr)elmPtr;
}
AlwaysPrefetch::AlwaysPrefetch(MemorySystem* current
,const char *section
,const char *name)
: MemObj(section, name)
,gms(current)
,halfMiss("%s:halfMiss", name)
,miss("%s:miss", name)
,hit("%s:hits", name)
,predictions("%s:predictions", name)
,accesses("%s:accesses", name)
{
MemObj *lower_level = NULL;
const char *Section = SescConf->getCharPtr(section, "nextLevel");
if (Section) {
lineSize = SescConf->getInt(Section, "bsize");
}
I(current);
lower_level = current->declareMemoryObj(section, k_lowerLevel);
const char *buffSection = SescConf->getCharPtr(section, "buffCache");
if (buffSection) {
buff = BuffType::create(buffSection, "", name);
SescConf->isInt(buffSection, "numPorts");
numBuffPorts = SescConf->getInt(buffSection, "numPorts");
SescConf->isInt(buffSection, "portOccp");
buffPortOccp = SescConf->getInt(buffSection, "portOccp");
}
defaultMask = ~(buff->getLineSize()-1);
char portName[128];
sprintf(portName, "%s_buff", name);
buffPort = PortGeneric::create(portName, numBuffPorts, buffPortOccp);
sprintf(portName, "%s_table", name);
tablePort = PortGeneric::create(portName, numTablePorts, tablePortOccp);
if (lower_level != NULL)
addLowerLevel(lower_level);
}
PriorityBus::PriorityBus(MemorySystem* current, const char *section,
const char *name)
: MemObj(section, name)
,enablePrio(SescConf->getBool(section, "enablePrio"))
,delay(SescConf->getInt(section, "delay"))
,nBypassDown("PBusPort%s_nBypassDown", name)
,nBypassUp("PBusPort%s_nBypassUp", name)
,nBypassDirection("PBusPort%s_nBypassDirection", name)
,processQCB(this)
{
MemObj *lower_level = NULL;
NumUnits_t num = SescConf->getInt(section, "numPorts");
dataOcc = SescConf->getInt(section, "dataOccp");
controlOcc = SescConf->getInt(section, "controlOccp");
char portName[256];
sprintf(portName, "PBusPort%s", name);
busPort = new PortNPipe(portName, num, dataOcc);
avgTime[upHighP] = new GStatsAvg("PBus%s_upHighAvgTime", name);
avgTime[downHighP] = new GStatsAvg("PBus%s_downHighAvgTime", name);
avgTime[upLowP] = new GStatsAvg("PBus%s_upLowAvgTime", name);
avgTime[downLowP] = new GStatsAvg("PBus%s_downLowAvgTime", name);
tHist[upHighP] = new GStatsTimingHist("PBus%s_upHighOcc", name);
tHist[downHighP] = new GStatsTimingHist("PBus%s_downHighOcc", name);
tHist[upLowP] = new GStatsTimingHist("PBus%s_upLowOcc", name);
tHist[downLowP] = new GStatsTimingHist("PBus%s_downLowOcc", name);
for(int32_t q = 0; q < LastQ; q++) {
reqQs[q].clear();
timeQs[q].clear();
}
I(current);
lower_level = current->declareMemoryObj(section, k_lowerLevel);
if (lower_level != NULL)
addLowerLevel(lower_level);
}
MemXBar::MemXBar(MemorySystem* current ,const char *section ,const char *name)
/* constructor */
: GXBar(section, name)
{/*{{{*/
I(current);
char * tmp;
lower_level_banks = NULL;
MSG("building a memXbar named:%s\n",name);
setParam(section, name);
lower_level_banks = new MemObj*[numLowerLevelBanks];
XBar_rw_req = new GStatsCntr* [numLowerLevelBanks];
std::vector<char *> vPars = SescConf->getSplitCharPtr(section, "lowerLevel");
//size_t size = strlen(vPars[0]);
for(size_t i=0;i<numLowerLevelBanks;i++) {
//lower_level_banks[i] = current->declareMemoryObj(section, "lowerLevel");
tmp = (char*)malloc(255);
sprintf(tmp,"%s(%lu)",vPars[1],i);
lower_level_banks[i] = current->declareMemoryObj_uniqueName(tmp,vPars[0]);
addLowerLevel(lower_level_banks[i]);
XBar_rw_req[i] = new GStatsCntr("%s_to_%s:rw_req",name,lower_level_banks[i]->getName());
}
if(Xbar_unXbar_balance !=0){
printf("ERROR: Crossbars and UnCrossbars are unbalanced: %d\n",Xbar_unXbar_balance);
exit(1);
}
//free(tmp);
}
StridePrefetcher::StridePrefetcher(MemorySystem* current ,const char *section ,const char *name)
/* constructor {{{1 */
:MemObj(section, name)
,halfMiss("%s:halfMiss", name)
,miss("%s:miss", name)
,hit("%s:hits", name)
,predictions("%s:predictions", name)
,accesses("%s:accesses", name)
{
MemObj *lower_level = NULL;
// If MemLatency is 200 and busOcc is 10, then there can be at most 20
// requests without saturating the bus. (VERIFY???) something like half sound
// conservative (10 pending requests)
MaxPendingRequests = 8; // FIXME: SescConf
SescConf->isInt(section, "depth");
depth = SescConf->getInt(section, "depth");
SescConf->isInt(section, "missWindow");
missWindow = SescConf->getInt(section, "missWindow");
SescConf->isInt(section, "maxStride");
maxStride = SescConf->getInt(section, "maxStride");
SescConf->isInt(section, "hitDelay");
hitDelay = SescConf->getInt(section, "hitDelay");
SescConf->isInt(section, "missDelay");
missDelay = SescConf->getInt(section, "missDelay");
SescConf->isInt(section, "learnHitDelay");
learnHitDelay = SescConf->getInt(section, "learnHitDelay");
SescConf->isInt(section, "learnMissDelay");
learnMissDelay = SescConf->getInt(section, "learnMissDelay");
const char *buffSection = SescConf->getCharPtr(section, "buffCache");
if (buffSection) {
buff = BuffType::create(buffSection, "", name);
lineSize = buff->getLineSize();
SescConf->isInt(buffSection, "bkNumPorts");
numBuffPorts = SescConf->getInt(buffSection, "bkNumPorts");
SescConf->isInt(buffSection, "bkPortOccp");
buffPortOccp = SescConf->getInt(buffSection, "bkPortOccp");
//SescConf->isInt(buffSection, "bsize");
//lineSize = SescConf->getInt(buffSection,"bsize");
}
//defaultMask = ~(lineSize-1);
numBuffPorts = SescConf->getInt(buffSection, "bkNumPorts");
buffPortOccp = SescConf->getInt(buffSection, "bkPortOccp");
/*
char cadena[100];
sprintf(cadena,"Data%s", name);
dataPort = PortGeneric::create(cadena, num, occ);
sprintf(cadena,"Cmd%s", name);
cmdPort = PortGeneric::create(cadena, num, 1);
*/
char portName[128];
sprintf(portName, "%s_buff", name);
dataPort = PortGeneric::create(portName, numBuffPorts, buffPortOccp);
cmdPort = PortGeneric::create(portName, numBuffPorts, 1);
I(current);
lower_level = current->declareMemoryObj(section, "lowerLevel");
if (lower_level != NULL)
addLowerLevel(lower_level);
}
CCache::CCache(MemorySystem *gms, const char *section, const char *name)
// Constructor {{{1
:MemObj(section, name)
,hitDelay (SescConf->getInt(section,"hitDelay"))
,missDelay (SescConf->getInt(section,"missDelay"))
,displaced ("%s:displaced", name)
,invAll ("%s:invAll", name)
,invOne ("%s:invOne", name)
,invNone ("%s:invNone", name)
,writeBack ("%s:writeBack", name)
,lineFill ("%s:lineFill", name)
,avgMissLat ("%s_avgMissLat", name)
,avgMemLat ("%s_avgMemLat", name)
,capInvalidateHit ("%s_capInvalidateHit", name)
,capInvalidateMiss ("%s_capInvalidateMiss", name)
,invalidateHit ("%s_invalidateHit", name)
,invalidateMiss ("%s_invalidateMiss", name)
,writeExclusive ("%s:writeExclusive", name)
{
SescConf->isInt(section, "hitDelay");
SescConf->isInt(section, "missDelay");
SescConf->isGT(section, "hitDelay" ,0);
SescConf->isGT(section, "missDelay",0);
s_reqHit[ma_setInvalid] = new GStatsCntr("%s:setInvalidHit",name);
s_reqHit[ma_setValid] = new GStatsCntr("%s:readHit",name);
s_reqHit[ma_setDirty] = new GStatsCntr("%s:writeHit",name);
s_reqHit[ma_setShared] = new GStatsCntr("%s:setSharedHit",name);
s_reqHit[ma_setExclusive] = new GStatsCntr("%s:setExclusiveHit",name);
s_reqHit[ma_MMU] = new GStatsCntr("%s:MMUHit",name);
s_reqHit[ma_VPCWU] = new GStatsCntr("%s:VPCMUHit",name);
s_reqMiss[ma_setInvalid] = new GStatsCntr("%s:setInvalidMiss",name);
s_reqMiss[ma_setValid] = new GStatsCntr("%s:readMiss",name);
s_reqMiss[ma_setDirty] = new GStatsCntr("%s:writeMiss",name);
s_reqMiss[ma_setShared] = new GStatsCntr("%s:setSharedMiss",name);
s_reqMiss[ma_setExclusive] = new GStatsCntr("%s:setExclusiveMiss",name);
s_reqMiss[ma_MMU] = new GStatsCntr("%s:MMUMiss",name);
s_reqMiss[ma_VPCWU] = new GStatsCntr("%s:VPCMUMiss",name);
s_reqHalfMiss[ma_setInvalid] = new GStatsCntr("%s:setInvalidHalfMiss",name);
s_reqHalfMiss[ma_setValid] = new GStatsCntr("%s:readHalfMiss",name);
s_reqHalfMiss[ma_setDirty] = new GStatsCntr("%s:writeHalfMiss",name);
s_reqHalfMiss[ma_setShared] = new GStatsCntr("%s:setSharedHalfMiss",name);
s_reqHalfMiss[ma_setExclusive] = new GStatsCntr("%s:setExclusiveHalfMiss",name);
s_reqHalfMiss[ma_MMU] = new GStatsCntr("%s:MMUHalfMiss",name);
s_reqHalfMiss[ma_VPCWU] = new GStatsCntr("%s:VPCMUHalfMiss",name);
s_reqAck[ma_setInvalid] = new GStatsCntr("%s:setInvalidAck",name);
s_reqAck[ma_setValid] = new GStatsCntr("%s:setValidAck",name);
s_reqAck[ma_setDirty] = new GStatsCntr("%s:setDirtyAck",name);
s_reqAck[ma_setShared] = new GStatsCntr("%s:setSharedAck",name);
s_reqAck[ma_setExclusive] = new GStatsCntr("%s:setExclusiveAck",name);
s_reqAck[ma_MMU] = new GStatsCntr("%s:MMUAck",name);
s_reqAck[ma_VPCWU] = new GStatsCntr("%s:VPCMUAck",name);
s_reqSetState[ma_setInvalid] = new GStatsCntr("%s:setInvalidsetState",name);
s_reqSetState[ma_setValid] = new GStatsCntr("%s:setValidsetState",name);
s_reqSetState[ma_setDirty] = new GStatsCntr("%s:setDirtysetState",name);
s_reqSetState[ma_setShared] = new GStatsCntr("%s:setSharedsetState",name);
s_reqSetState[ma_setExclusive] = new GStatsCntr("%s:setExclusivesetState",name);
s_reqSetState[ma_MMU] = new GStatsCntr("%s:MMUsetState",name);
s_reqSetState[ma_VPCWU] = new GStatsCntr("%s:VPCMUsetState",name);
dyn_hitDelay = hitDelay; // DVFS managed
dyn_missDelay = missDelay;
// TODO: add support for coreCoupledFreq as part of mreq
//if(SescConf->checkBool(section,"coreCoupledFreq")) {
//MSG("WARNING: coreCoupledFreq does not work yet");
//}
coreCoupledFreq = false;
//if (coreCoupledFreq) {
// BootLoader::getPowerModelPtr()->addTurboCoupledMemory(this);
//}
const char* mshrSection = SescConf->getCharPtr(section,"MSHR");
char tmpName[512];
sprintf(tmpName, "%s", name);
cacheBank = CacheType::create(section, "", tmpName);
lineSize = cacheBank->getLineSize();
lineSizeBits = log2i(lineSize);
mshr = MSHR::create(tmpName, mshrSection, lineSize);
I(getLineSize() < 4096); // To avoid bank selection conflict (insane CCache line)
I(gms);
SescConf->checkBool(section, "inclusive");
SescConf->checkBool(section, "directory");
inclusive = SescConf->getBool(section, "inclusive");
directory = SescConf->getBool(section, "directory");
if (directory && !inclusive) {
I(0);
MSG("ERROR: %s CCache can not have a 'directory' without being 'inclusive'",section);
SescConf->notCorrect();
}
MemObj *lower_level = gms->declareMemoryObj(section, "lowerLevel");
if(lower_level)
addLowerLevel(lower_level);
port = PortManager::create(section, this);
}
StridePrefetcher::StridePrefetcher(MemorySystem* current ,const char *section ,const char *name)
/* constructor {{{1 */
:MemObj(section, name)
,halfMiss("%s:halfMiss", name)
,miss("%s:miss", name)
,hit("%s:hits", name)
,predictions("%s:predictions", name)
,accesses("%s:accesses", name)
,unitStrideStreams("%s:unitStrideStreams", name)
,nonUnitStrideStreams("%s:nonUnitStrideStreams", name)
,ignoredStreams("%s:ignoredStreams", name)
{
MemObj *lower_level = NULL;
// If MemLatency is 200 and busOcc is 10, then there can be at most 20
// requests without saturating the bus. (VERIFY???) something like half sound
// conservative (10 pending requests)
MaxPendingRequests = 8; // FIXME: SescConf
SescConf->isInt(section, "depth");
depth = SescConf->getInt(section, "depth");
SescConf->isInt(section, "missWindow");
missWindow = SescConf->getInt(section, "missWindow");
SescConf->isInt(section, "maxStride");
maxStride = SescConf->getInt(section, "maxStride");
SescConf->isInt(section, "hitDelay");
hitDelay = SescConf->getInt(section, "hitDelay");
SescConf->isInt(section, "missDelay");
missDelay = SescConf->getInt(section, "missDelay");
SescConf->isInt(section, "learnHitDelay");
learnHitDelay = SescConf->getInt(section, "learnHitDelay");
SescConf->isInt(section, "learnMissDelay");
learnMissDelay = SescConf->getInt(section, "learnMissDelay");
I(depth > 0);
const char *buffSection = SescConf->getCharPtr(section, "buffCache");
if (buffSection) {
buff = BuffType::create(buffSection, "", name);
SescConf->isInt(buffSection, "bknumPorts");
numBuffPorts = SescConf->getInt(buffSection, "bknumPorts");
SescConf->isInt(buffSection, "bkportOccp");
buffPortOccp = SescConf->getInt(buffSection, "bkportOccp");
}
const char *streamSection = SescConf->getCharPtr(section, "streamCache");
if (streamSection) {
char tableName[128];
sprintf(tableName, "%sPrefTable", name);
table = PfTable::create(streamSection, "", tableName);
GMSG(pEntrySize != SescConf->getInt(streamSection, "BSize"),
"The prefetch buffer streamBSize field in the configuration file should be %d.", pEntrySize);
SescConf->isInt(streamSection, "bknumPorts");
numTablePorts = SescConf->getInt(streamSection, "bknumPorts");
SescConf->isInt(streamSection, "bkportOccp");
tablePortOccp = SescConf->getInt(streamSection, "bkportOccp");
}
char portName[128];
sprintf(portName, "%s_buff", name);
buffPort = PortGeneric::create(portName, numBuffPorts, buffPortOccp);
sprintf(portName, "%s_table", name);
tablePort = PortGeneric::create(portName, numTablePorts, tablePortOccp);
defaultMask = ~(buff->getLineSize()-1);
I(current);
lower_level = current->declareMemoryObj(section, "lowerLevel");
if (lower_level != NULL)
addLowerLevel(lower_level);
//Is this the memory
isMemoryBus = false;
}
StridePrefetcher::StridePrefetcher(MemorySystem* current
,const char *section
,const char *name)
: MemObj(section, name)
,halfMiss("%s:halfMiss", name)
,miss("%s:miss", name)
,hit("%s:hits", name)
,predictions("%s:predictions", name)
,accesses("%s:accesses", name)
,unitStrideStreams("%s:unitStrideStreams", name)
,nonUnitStrideStreams("%s:nonUnitStrideStreams", name)
,ignoredStreams("%s:ignoredStreams", name)
{
MemObj *lower_level = NULL;
SescConf->isInt(section, "depth");
depth = SescConf->getInt(section, "depth");
SescConf->isInt(section, "missWindow");
missWindow = SescConf->getInt(section, "missWindow");
SescConf->isInt(section, "maxStride");
maxStride = SescConf->getInt(section, "maxStride");
SescConf->isInt(section, "hitDelay");
hitDelay = SescConf->getInt(section, "hitDelay");
SescConf->isInt(section, "missDelay");
missDelay = SescConf->getInt(section, "missDelay");
SescConf->isInt(section, "learnHitDelay");
learnHitDelay = SescConf->getInt(section, "learnHitDelay");
SescConf->isInt(section, "learnMissDelay");
learnMissDelay = SescConf->getInt(section, "learnMissDelay");
I(depth > 0);
const char *buffSection = SescConf->getCharPtr(section, "buffCache");
if (buffSection) {
buff = BuffType::create(buffSection, "", name);
SescConf->isInt(buffSection, "numPorts");
numBuffPorts = SescConf->getInt(buffSection, "numPorts");
SescConf->isInt(buffSection, "portOccp");
buffPortOccp = SescConf->getInt(buffSection, "portOccp");
}
const char *streamSection = SescConf->getCharPtr(section, "streamCache");
if (streamSection) {
char tableName[128];
sprintf(tableName, "%sPrefTable", name);
table = PfTable::create(streamSection, "", tableName);
GMSG(pEntrySize != SescConf->getInt(streamSection, "BSize"),
"The prefetch buffer streamBSize field in the configuration file should be %d.", pEntrySize);
SescConf->isInt(streamSection, "numPorts");
numTablePorts = SescConf->getInt(streamSection, "numPorts");
SescConf->isInt(streamSection, "portOccp");
tablePortOccp = SescConf->getInt(streamSection, "portOccp");
}
char portName[128];
sprintf(portName, "%s_buff", name);
buffPort = PortGeneric::create(portName, numBuffPorts, buffPortOccp);
sprintf(portName, "%s_table", name);
tablePort = PortGeneric::create(portName, numTablePorts, tablePortOccp);
defaultMask = ~(buff->getLineSize()-1);
I(current);
lower_level = current->declareMemoryObj(section, k_lowerLevel);
if (lower_level != NULL)
addLowerLevel(lower_level);
}
MarkovPrefetcher::MarkovPrefetcher(MemorySystem* current
,const char *section
,const char *name)
: MemObj(section, name)
,gms(current)
,halfMiss("%s:halfMiss", name)
,miss("%s:miss", name)
,hit("%s:hits", name)
,predictions("%s:predictions", name)
,accesses("%s:accesses", name)
{
MemObj *lower_level = NULL;
SescConf->isInt(section, "depth");
depth = SescConf->getInt(section, "depth");
SescConf->isInt(section, "width");
width = SescConf->getInt(section, "width");
const char *Section = SescConf->getCharPtr(section, "nextLevel");
if (Section) {
lineSize = SescConf->getInt(Section, "bsize");
}
const char *buffSection = SescConf->getCharPtr(section, "buffCache");
if (buffSection) {
buff = BuffType::create(buffSection, "", name);
SescConf->isInt(buffSection, "numPorts");
numBuffPorts = SescConf->getInt(buffSection, "numPorts");
SescConf->isInt(buffSection, "portOccp");
buffPortOccp = SescConf->getInt(buffSection, "portOccp");
}
const char *streamSection = SescConf->getCharPtr(section, "streamCache");
if (streamSection) {
char tableName[128];
sprintf(tableName, "%sPrefTable", name);
table = MarkovTable::create(streamSection, "", tableName);
GMSG(tEntrySize != SescConf->getInt(streamSection, "BSize"),
"The prefetch buffer streamBSize field in the configuration file should be %d.", tEntrySize);
SescConf->isInt(streamSection, "numPorts");
numTablePorts = SescConf->getInt(streamSection, "numPorts");
SescConf->isInt(streamSection, "portOccp");
tablePortOccp = SescConf->getInt(streamSection, "portOccp");
}
defaultMask = ~(buff->getLineSize()-1);
char portName[128];
sprintf(portName, "%s_buff", name);
buffPort = PortGeneric::create(portName, numBuffPorts, buffPortOccp);
sprintf(portName, "%s_table", name);
tablePort = PortGeneric::create(portName, numTablePorts, tablePortOccp);
ptr = 0;
lastAddr = 0;
I(current);
lower_level = current->declareMemoryObj(section, k_lowerLevel);
if (lower_level != NULL)
addLowerLevel(lower_level);
}
SMPCache::SMPCache(SMemorySystem *dms,const char *section, const char *name)
: MemObj(section, name)
, readHit("%s:readHit", name)
, writeHit("%s:writeHit", name)
, readMiss("%s:readMiss", name)
, writeMiss("%s:writeMiss", name)
, readHalfMiss("%s:readHalfMiss", name)
, writeHalfMiss("%s:writeHalfMiss", name)
, writeBack("%s:writeBack", name)
, linePush("%s:linePush", name)
, lineFill("%s:lineFill", name)
, readRetry("%s:readRetry", name)
, writeRetry("%s:writeRetry", name)
, invalDirty("%s:invalDirty", name)
, allocDirty("%s:allocDirty", name)
#ifdef TLS
,epochMissW("%s:Write Miss due to Epoch Missmatch",name)
,epochMissR("%s:Read Miss due to Epoch Missmatch",name)
,sharedWrites("%s:L2 Shared Writes",name)
,writeHitProp("%s:Write hits sent down to system bus",name)
,readHitProp("%s:Read hits sent down to system bus",name)
,squashes("%s:Backend squashes",name)
#endif
{
MemObj *lowerLevel = NULL;
I(dms);
lowerLevel = dms->declareMemoryObj(section, "lowerLevel");
if (lowerLevel != NULL)
addLowerLevel(lowerLevel);
cache = CacheType::create(section, "", name);
I(cache);
const char *prot = SescConf->getCharPtr(section, "protocol");
if(!strcasecmp(prot, "MESI")) {
protocol = new MESIProtocol(this);
} else {
MSG("unknown protocol, using MESI");
protocol = new MESIProtocol(this);
}
SescConf->isInt(section, "numPorts");
SescConf->isInt(section, "portOccp");
cachePort = PortGeneric::create(name,
SescConf->getInt(section, "numPorts"),
SescConf->getInt(section, "portOccp"));
// MSHR is used as an outstanding request buffer
// even hits are added to MSHR
char *outsReqName = (char *) malloc(strlen(name) + 2);
sprintf(outsReqName, "%s", name);
const char *mshrSection = SescConf->getCharPtr(section,"MSHR");
outsReq = MSHR<PAddr,SMPCache>::create(outsReqName, mshrSection);
if (mutExclBuffer == NULL)
mutExclBuffer = MSHR<PAddr,SMPCache>::create("mutExclBuffer",
SescConf->getCharPtr(mshrSection, "type"),
32000,
SescConf->getInt(mshrSection, "bsize"));
SescConf->isInt(section, "hitDelay");
hitDelay = SescConf->getInt(section, "hitDelay");
SescConf->isInt(section, "missDelay");
missDelay = SescConf->getInt(section, "missDelay");
}