static int ti_aintc_attach(device_t dev) { struct ti_aintc_softc *sc = device_get_softc(dev); uint32_t x; sc->sc_dev = dev; if (ti_aintc_sc) return (ENXIO); if (bus_alloc_resources(dev, ti_aintc_spec, sc->aintc_res)) { device_printf(dev, "could not allocate resources\n"); return (ENXIO); } sc->aintc_bst = rman_get_bustag(sc->aintc_res[0]); sc->aintc_bsh = rman_get_bushandle(sc->aintc_res[0]); ti_aintc_sc = sc; x = aintc_read_4(INTC_REVISION); device_printf(dev, "Revision %u.%u\n",(x >> 4) & 0xF, x & 0xF); /* SoftReset */ aintc_write_4(INTC_SYSCONFIG, 2); /* Wait for reset to complete */ while(!(aintc_read_4(INTC_SYSSTATUS) & 1)); /*Set Priority Threshold */ aintc_write_4(INTC_THRESHOLD, 0xFF); return (0); }
void arm_mask_irq(uintptr_t nb) { uint32_t bit, block, value; bit = (nb % 32); block = (nb / 32); value = aintc_read_4(SW_INT_ENABLE_REG(block)); value &= ~(1 << bit); aintc_write_4(SW_INT_ENABLE_REG(block), value); value = aintc_read_4(SW_INT_MASK_REG(block)); value |= (1 << bit); aintc_write_4(SW_INT_MASK_REG(block), value); }
static void a10_intr_mask(struct a10_aintc_softc *sc, u_int irq) { uint32_t bit, block, value; bit = (irq % 32); block = (irq / 32); mtx_lock_spin(&sc->mtx); value = aintc_read_4(sc, SW_INT_ENABLE_REG(block)); value &= ~(1 << bit); aintc_write_4(sc, SW_INT_ENABLE_REG(block), value); value = aintc_read_4(sc, SW_INT_MASK_REG(block)); value |= (1 << bit); aintc_write_4(sc, SW_INT_MASK_REG(block), value); mtx_unlock_spin(&sc->mtx); }
int arm_get_next_irq(int last_irq) { uint32_t active_irq; if (last_irq != -1) { aintc_write_4(INTC_ISR_CLEAR(last_irq >> 5), 1UL << (last_irq & 0x1F)); aintc_write_4(INTC_CONTROL,1); }
void arm_unmask_irq(uintptr_t nb) { uint32_t bit, block, value; bit = (nb % 32); block = (nb / 32); value = aintc_read_4(SW_INT_ENABLE_REG(block)); value |= (1 << bit); aintc_write_4(SW_INT_ENABLE_REG(block), value); value = aintc_read_4(SW_INT_MASK_REG(block)); value &= ~(1 << bit); aintc_write_4(SW_INT_MASK_REG(block), value); if(nb == SW_INT_IRQNO_ENMI) /* must clear pending bit when enabled */ aintc_write_4(SW_INT_IRQ_PENDING_REG(0), (1 << SW_INT_IRQNO_ENMI)); }
static int a10_aintc_attach(device_t dev) { struct a10_aintc_softc *sc = device_get_softc(dev); int rid = 0; int i; sc->sc_dev = dev; sc->aintc_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); if (!sc->aintc_res) { device_printf(dev, "could not allocate resource\n"); goto error; } sc->aintc_bst = rman_get_bustag(sc->aintc_res); sc->aintc_bsh = rman_get_bushandle(sc->aintc_res); mtx_init(&sc->mtx, "A10 AINTC lock", "", MTX_SPIN); /* Disable & clear all interrupts */ for (i = 0; i < 3; i++) { aintc_write_4(sc, SW_INT_ENABLE_REG(i), 0); aintc_write_4(sc, SW_INT_MASK_REG(i), 0xffffffff); } /* enable protection mode*/ aintc_write_4(sc, SW_INT_PROTECTION_REG, 0x01); /* config the external interrupt source type*/ aintc_write_4(sc, SW_INT_NMI_CTRL_REG, 0x00); if (a10_intr_pic_attach(sc) != 0) { device_printf(dev, "could not attach PIC\n"); return (ENXIO); } return (0); error: bus_release_resource(dev, SYS_RES_MEMORY, rid, sc->aintc_res); return (ENXIO); }
static __inline void a10_intr_eoi(struct a10_aintc_softc *sc, u_int irq) { if (irq != SW_INT_IRQNO_ENMI) return; mtx_lock_spin(&sc->mtx); aintc_write_4(sc, SW_INT_IRQ_PENDING_REG(0), (1 << SW_INT_IRQNO_ENMI)); mtx_unlock_spin(&sc->mtx); }
static int a10_aintc_attach(device_t dev) { struct a10_aintc_softc *sc = device_get_softc(dev); int rid = 0; int i; sc->sc_dev = dev; if (a10_aintc_sc) return (ENXIO); sc->aintc_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); if (!sc->aintc_res) { device_printf(dev, "could not allocate resource\n"); return (ENXIO); } sc->aintc_bst = rman_get_bustag(sc->aintc_res); sc->aintc_bsh = rman_get_bushandle(sc->aintc_res); a10_aintc_sc = sc; /* Disable & clear all interrupts */ for (i = 0; i < 3; i++) { aintc_write_4(SW_INT_ENABLE_REG(i), 0); aintc_write_4(SW_INT_MASK_REG(i), 0xffffffff); } /* enable protection mode*/ aintc_write_4(SW_INT_PROTECTION_REG, 0x01); /* config the external interrupt source type*/ aintc_write_4(SW_INT_NMI_CTRL_REG, 0x00); return (0); }