void gendsub() { #ifdef INTERPRET_DSUB gencallinterp((unsigned long)DSUB, 0); #else int rs1 = allocate_64_register1((unsigned long *)dst->f.r.rs); int rs2 = allocate_64_register2((unsigned long *)dst->f.r.rs); int rt1 = allocate_64_register1((unsigned long *)dst->f.r.rt); int rt2 = allocate_64_register2((unsigned long *)dst->f.r.rt); int rd1 = allocate_64_register1_w((unsigned long *)dst->f.r.rd); int rd2 = allocate_64_register2_w((unsigned long *)dst->f.r.rd); if (rt1 != rd1 && rs1 != rd1) { mov_reg32_reg32(rd1, rs1); mov_reg32_reg32(rd2, rs2); sub_reg32_reg32(rd1, rt1); sbb_reg32_reg32(rd2, rt2); } else { int temp = lru_register(); free_register(temp); mov_reg32_reg32(temp, rs1); sub_reg32_reg32(temp, rt1); mov_reg32_reg32(rd1, temp); mov_reg32_reg32(temp, rs2); sbb_reg32_reg32(temp, rt2); mov_reg32_reg32(rd2, temp); } #endif }
void gendsub(usf_state_t * state) { #ifdef INTERPRET_DSUB gencallinterp(state, (unsigned int)state->current_instruction_table.DSUB, 0); #else int rs1 = allocate_64_register1(state, (unsigned int *)state->dst->f.r.rs); int rs2 = allocate_64_register2(state, (unsigned int *)state->dst->f.r.rs); int rt1 = allocate_64_register1(state, (unsigned int *)state->dst->f.r.rt); int rt2 = allocate_64_register2(state, (unsigned int *)state->dst->f.r.rt); int rd1 = allocate_64_register1_w(state, (unsigned int *)state->dst->f.r.rd); int rd2 = allocate_64_register2_w(state, (unsigned int *)state->dst->f.r.rd); if (rt1 != rd1 && rs1 != rd1) { mov_reg32_reg32(state, rd1, rs1); mov_reg32_reg32(state, rd2, rs2); sub_reg32_reg32(state, rd1, rt1); sbb_reg32_reg32(state, rd2, rt2); } else { int temp = lru_register(state); free_register(state, temp); mov_reg32_reg32(state, temp, rs1); sub_reg32_reg32(state, temp, rt1); mov_reg32_reg32(state, rd1, temp); mov_reg32_reg32(state, temp, rs2); sbb_reg32_reg32(state, temp, rt2); mov_reg32_reg32(state, rd2, temp); } #endif }
void gendsub(void) { #ifdef INTERPRET_DSUB gencallinterp((unsigned int)cached_interpreter_table.DSUB, 0); #else int rs1 = allocate_64_register1((unsigned int *)g_dev.r4300.recomp.dst->f.r.rs); int rs2 = allocate_64_register2((unsigned int *)g_dev.r4300.recomp.dst->f.r.rs); int rt1 = allocate_64_register1((unsigned int *)g_dev.r4300.recomp.dst->f.r.rt); int rt2 = allocate_64_register2((unsigned int *)g_dev.r4300.recomp.dst->f.r.rt); int rd1 = allocate_64_register1_w((unsigned int *)g_dev.r4300.recomp.dst->f.r.rd); int rd2 = allocate_64_register2_w((unsigned int *)g_dev.r4300.recomp.dst->f.r.rd); if (rt1 != rd1 && rs1 != rd1) { mov_reg32_reg32(rd1, rs1); mov_reg32_reg32(rd2, rs2); sub_reg32_reg32(rd1, rt1); sbb_reg32_reg32(rd2, rt2); } else { int temp = lru_register(); free_register(temp); mov_reg32_reg32(temp, rs1); sub_reg32_reg32(temp, rt1); mov_reg32_reg32(rd1, temp); mov_reg32_reg32(temp, rs2); sbb_reg32_reg32(temp, rt2); mov_reg32_reg32(rd2, temp); } #endif }
void gendaddu(void) { #ifdef INTERPRET_DADDU gencallinterp((unsigned int)cached_interpreter_table.DADDU, 0); #else int rs1 = allocate_64_register1((unsigned int *)dst->f.r.rs); int rs2 = allocate_64_register2((unsigned int *)dst->f.r.rs); int rt1 = allocate_64_register1((unsigned int *)dst->f.r.rt); int rt2 = allocate_64_register2((unsigned int *)dst->f.r.rt); int rd1 = allocate_64_register1_w((unsigned int *)dst->f.r.rd); int rd2 = allocate_64_register2_w((unsigned int *)dst->f.r.rd); if (rt1 != rd1 && rs1 != rd1) { mov_reg32_reg32(rd1, rs1); mov_reg32_reg32(rd2, rs2); add_reg32_reg32(rd1, rt1); adc_reg32_reg32(rd2, rt2); } else { int temp = lru_register(); free_register(temp); mov_reg32_reg32(temp, rs1); add_reg32_reg32(temp, rt1); mov_reg32_reg32(rd1, temp); mov_reg32_reg32(temp, rs2); adc_reg32_reg32(temp, rt2); mov_reg32_reg32(rd2, temp); } #endif }
static void genbltz_test(void) { int rs_64bit = is64((unsigned int *)dst->f.i.rs); if (!rs_64bit) { int rs = allocate_register((unsigned int *)dst->f.i.rs); cmp_reg32_imm32(rs, 0); jge_rj(12); mov_m32_imm32((unsigned int *)(&branch_taken), 1); // 10 jmp_imm_short(10); // 2 mov_m32_imm32((unsigned int *)(&branch_taken), 0); // 10 } else if (rs_64bit == -1) { cmp_m32_imm32(((unsigned int *)dst->f.i.rs)+1, 0); jge_rj(12); mov_m32_imm32((unsigned int *)(&branch_taken), 1); // 10 jmp_imm_short(10); // 2 mov_m32_imm32((unsigned int *)(&branch_taken), 0); // 10 } else { int rs2 = allocate_64_register2((unsigned int *)dst->f.i.rs); cmp_reg32_imm32(rs2, 0); jge_rj(12); mov_m32_imm32((unsigned int *)(&branch_taken), 1); // 10 jmp_imm_short(10); // 2 mov_m32_imm32((unsigned int *)(&branch_taken), 0); // 10 } }
void gensltu(usf_state_t * state) { #ifdef INTERPRET_SLTU gencallinterp(state, (unsigned int)state->current_instruction_table.SLTU, 0); #else int rs1 = allocate_64_register1(state, (unsigned int *)state->dst->f.r.rs); int rs2 = allocate_64_register2(state, (unsigned int *)state->dst->f.r.rs); int rt1 = allocate_64_register1(state, (unsigned int *)state->dst->f.r.rt); int rt2 = allocate_64_register2(state, (unsigned int *)state->dst->f.r.rt); int rd = allocate_register_w(state, (unsigned int *)state->dst->f.r.rd); cmp_reg32_reg32(state, rs2, rt2); jb_rj(state, 13); jne_rj(state, 4); // 2 cmp_reg32_reg32(state, rs1, rt1); // 2 jb_rj(state, 7); // 2 mov_reg32_imm32(state, rd, 0); // 5 jmp_imm_short(state, 5); // 2 mov_reg32_imm32(state, rd, 1); // 5 #endif }
void gendsra32() { #ifdef INTERPRET_DSRA32 gencallinterp((unsigned long)DSRA32, 0); #else int rt2 = allocate_64_register2((unsigned long *)dst->f.r.rt); int rd = allocate_register_w((unsigned long *)dst->f.r.rd); mov_reg32_reg32(rd, rt2); sar_reg32_imm8(rd, dst->f.r.sa); #endif }
static void genbltz_test(void) { int rs_64bit = is64((unsigned int *)dst->f.i.rs); if (rs_64bit == 0) { #ifdef __x86_64__ int rs = allocate_register_32((unsigned int *)dst->f.i.rs); #else int rs = allocate_register((unsigned int *)dst->f.i.rs); #endif cmp_reg32_imm32(rs, 0); #ifdef __x86_64__ setl_m8rel((unsigned char *) &branch_taken); #else jge_rj(12); mov_m32_imm32((unsigned int *)(&branch_taken), 1); // 10 jmp_imm_short(10); // 2 mov_m32_imm32((unsigned int *)(&branch_taken), 0); // 10 #endif } else if (rs_64bit == -1) { #ifdef __x86_64__ cmp_m32rel_imm32(((unsigned int *)dst->f.i.rs)+1, 0); setl_m8rel((unsigned char *) &branch_taken); #else cmp_m32_imm32(((unsigned int *)dst->f.i.rs)+1, 0); jge_rj(12); mov_m32_imm32((unsigned int *)(&branch_taken), 1); // 10 jmp_imm_short(10); // 2 mov_m32_imm32((unsigned int *)(&branch_taken), 0); // 10 #endif } else { #ifdef __x86_64__ int rs = allocate_register_64((uint64_t*)dst->f.i.rs); cmp_reg64_imm8(rs, 0); setl_m8rel((unsigned char *) &branch_taken); #else int rs2 = allocate_64_register2((unsigned int *)dst->f.i.rs); cmp_reg32_imm32(rs2, 0); jge_rj(12); mov_m32_imm32((unsigned int *)(&branch_taken), 1); // 10 jmp_imm_short(10); // 2 mov_m32_imm32((unsigned int *)(&branch_taken), 0); // 10 #endif } }
void gendsra32(void) { #ifdef INTERPRET_DSRA32 gencallinterp((unsigned int)cached_interpreter_table.DSRA32, 0); #else int rt2 = allocate_64_register2((unsigned int *)dst->f.r.rt); int rd = allocate_register_w((unsigned int *)dst->f.r.rd); mov_reg32_reg32(rd, rt2); sar_reg32_imm8(rd, dst->f.r.sa); #endif }
void gendsra32(usf_state_t * state) { #ifdef INTERPRET_DSRA32 gencallinterp(state, (unsigned int)state->current_instruction_table.DSRA32, 0); #else int rt2 = allocate_64_register2(state, (unsigned int *)state->dst->f.r.rt); int rd = allocate_register_w(state, (unsigned int *)state->dst->f.r.rd); mov_reg32_reg32(state, rd, rt2); sar_reg32_imm8(state, rd, state->dst->f.r.sa); #endif }
void genslt(void) { #ifdef INTERPRET_SLT gencallinterp((unsigned int)cached_interpreter_table.SLT, 0); #else int rs1 = allocate_64_register1((unsigned int *)dst->f.r.rs); int rs2 = allocate_64_register2((unsigned int *)dst->f.r.rs); int rt1 = allocate_64_register1((unsigned int *)dst->f.r.rt); int rt2 = allocate_64_register2((unsigned int *)dst->f.r.rt); int rd = allocate_register_w((unsigned int *)dst->f.r.rd); cmp_reg32_reg32(rs2, rt2); jl_rj(13); jne_rj(4); // 2 cmp_reg32_reg32(rs1, rt1); // 2 jl_rj(7); // 2 mov_reg32_imm32(rd, 0); // 5 jmp_imm_short(5); // 2 mov_reg32_imm32(rd, 1); // 5 #endif }
void gensltu() { #ifdef INTERPRET_SLTU gencallinterp((unsigned long)SLTU, 0); #else int rs1 = allocate_64_register1((unsigned long *)dst->f.r.rs); int rs2 = allocate_64_register2((unsigned long *)dst->f.r.rs); int rt1 = allocate_64_register1((unsigned long *)dst->f.r.rt); int rt2 = allocate_64_register2((unsigned long *)dst->f.r.rt); int rd = allocate_register_w((unsigned long *)dst->f.r.rd); cmp_reg32_reg32(rs2, rt2); jb_rj(13); jne_rj(4); // 2 cmp_reg32_reg32(rs1, rt1); // 2 jb_rj(7); // 2 mov_reg32_imm32(rd, 0); // 5 jmp_imm_short(5); // 2 mov_reg32_imm32(rd, 1); // 5 #endif }
void genmflo(void) { #ifdef INTERPRET_MFLO gencallinterp((unsigned int)cached_interpreter_table.MFLO, 0); #else int rd1 = allocate_64_register1_w((unsigned int*)dst->f.r.rd); int rd2 = allocate_64_register2_w((unsigned int*)dst->f.r.rd); int lo1 = allocate_64_register1((unsigned int*)&lo); int lo2 = allocate_64_register2((unsigned int*)&lo); mov_reg32_reg32(rd1, lo1); mov_reg32_reg32(rd2, lo2); #endif }
void genmthi(void) { #ifdef INTERPRET_MTHI gencallinterp((unsigned int)cached_interpreter_table.MTHI, 0); #else int hi1 = allocate_64_register1_w((unsigned int*)&hi); int hi2 = allocate_64_register2_w((unsigned int*)&hi); int rs1 = allocate_64_register1((unsigned int*)dst->f.r.rs); int rs2 = allocate_64_register2((unsigned int*)dst->f.r.rs); mov_reg32_reg32(hi1, rs1); mov_reg32_reg32(hi2, rs2); #endif }
void genmfhi(void) { #ifdef INTERPRET_MFHI gencallinterp((unsigned int)cached_interpreter_table.MFHI, 0); #else int rd1 = allocate_64_register1_w((unsigned int*)dst->f.r.rd); int rd2 = allocate_64_register2_w((unsigned int*)dst->f.r.rd); int hi1 = allocate_64_register1((unsigned int*)&hi); int hi2 = allocate_64_register2((unsigned int*)&hi); mov_reg32_reg32(rd1, hi1); mov_reg32_reg32(rd2, hi2); #endif }
void genmtlo(usf_state_t * state) { #ifdef INTERPRET_MTLO gencallinterp(state, (unsigned int)state->current_instruction_table.MTLO, 0); #else int lo1 = allocate_64_register1_w(state, (unsigned int*)&state->lo); int lo2 = allocate_64_register2_w(state, (unsigned int*)&state->lo); int rs1 = allocate_64_register1(state, (unsigned int*)state->dst->f.r.rs); int rs2 = allocate_64_register2(state, (unsigned int*)state->dst->f.r.rs); mov_reg32_reg32(state, lo1, rs1); mov_reg32_reg32(state, lo2, rs2); #endif }
void genmfhi(usf_state_t * state) { #ifdef INTERPRET_MFHI gencallinterp(state, (unsigned int)state->current_instruction_table.MFHI, 0); #else int rd1 = allocate_64_register1_w(state, (unsigned int*)state->dst->f.r.rd); int rd2 = allocate_64_register2_w(state, (unsigned int*)state->dst->f.r.rd); int hi1 = allocate_64_register1(state, (unsigned int*)&state->hi); int hi2 = allocate_64_register2(state, (unsigned int*)&state->hi); mov_reg32_reg32(state, rd1, hi1); mov_reg32_reg32(state, rd2, hi2); #endif }
void genmtlo(void) { #ifdef INTERPRET_MTLO gencallinterp((unsigned int)cached_interpreter_table.MTLO, 0); #else int lo1 = allocate_64_register1_w((unsigned int*)&lo); int lo2 = allocate_64_register2_w((unsigned int*)&lo); int rs1 = allocate_64_register1((unsigned int*)dst->f.r.rs); int rs2 = allocate_64_register2((unsigned int*)dst->f.r.rs); mov_reg32_reg32(lo1, rs1); mov_reg32_reg32(lo2, rs2); #endif }
void gendsrl32(void) { #ifdef INTERPRET_DSRL32 gencallinterp((unsigned int)cached_interpreter_table.DSRL32, 0); #else int rt2 = allocate_64_register2((unsigned int *)g_dev.r4300.recomp.dst->f.r.rt); int rd1 = allocate_64_register1_w((unsigned int *)g_dev.r4300.recomp.dst->f.r.rd); int rd2 = allocate_64_register2_w((unsigned int *)g_dev.r4300.recomp.dst->f.r.rd); mov_reg32_reg32(rd1, rt2); shr_reg32_imm8(rd1, g_dev.r4300.recomp.dst->f.r.sa); xor_reg32_reg32(rd2, rd2); #endif }
void genmtlo() { #ifdef INTERPRET_MTLO gencallinterp((unsigned long)MTLO, 0); #else int lo1 = allocate_64_register1_w((unsigned long*)&lo); int lo2 = allocate_64_register2_w((unsigned long*)&lo); int rs1 = allocate_64_register1((unsigned long*)dst->f.r.rs); int rs2 = allocate_64_register2((unsigned long*)dst->f.r.rs); mov_reg32_reg32(lo1, rs1); mov_reg32_reg32(lo2, rs2); #endif }
void genmthi() { #ifdef INTERPRET_MTHI gencallinterp((unsigned long)MTHI, 0); #else int hi1 = allocate_64_register1_w((unsigned long*)&hi); int hi2 = allocate_64_register2_w((unsigned long*)&hi); int rs1 = allocate_64_register1((unsigned long*)dst->f.r.rs); int rs2 = allocate_64_register2((unsigned long*)dst->f.r.rs); mov_reg32_reg32(hi1, rs1); mov_reg32_reg32(hi2, rs2); #endif }
void genmflo() { #ifdef INTERPRET_MFLO gencallinterp((unsigned long)MFLO, 0); #else int rd1 = allocate_64_register1_w((unsigned long*)dst->f.r.rd); int rd2 = allocate_64_register2_w((unsigned long*)dst->f.r.rd); int lo1 = allocate_64_register1((unsigned long*)&lo); int lo2 = allocate_64_register2((unsigned long*)&lo); mov_reg32_reg32(rd1, lo1); mov_reg32_reg32(rd2, lo2); #endif }
void genmfhi() { #ifdef INTERPRET_MFHI gencallinterp((unsigned long)MFHI, 0); #else int rd1 = allocate_64_register1_w((unsigned long*)dst->f.r.rd); int rd2 = allocate_64_register2_w((unsigned long*)dst->f.r.rd); int hi1 = allocate_64_register1((unsigned long*)&hi); int hi2 = allocate_64_register2((unsigned long*)&hi); mov_reg32_reg32(rd1, hi1); mov_reg32_reg32(rd2, hi2); #endif }
void gendsrl32() { #ifdef INTERPRET_DSRL32 gencallinterp((unsigned long)DSRL32, 0); #else int rt2 = allocate_64_register2((unsigned long *)dst->f.r.rt); int rd1 = allocate_64_register1_w((unsigned long *)dst->f.r.rd); int rd2 = allocate_64_register2_w((unsigned long *)dst->f.r.rd); mov_reg32_reg32(rd1, rt2); shr_reg32_imm8(rd1, dst->f.r.sa); xor_reg32_reg32(rd2, rd2); #endif }
void gendsrav(usf_state_t * state) { #ifdef INTERPRET_DSRAV gencallinterp(state, (unsigned int)state->current_instruction_table.DSRAV, 0); #else int rt1, rt2, rd1, rd2; allocate_register_manually(state, ECX, (unsigned int *)state->dst->f.r.rs); rt1 = allocate_64_register1(state, (unsigned int *)state->dst->f.r.rt); rt2 = allocate_64_register2(state, (unsigned int *)state->dst->f.r.rt); rd1 = allocate_64_register1_w(state, (unsigned int *)state->dst->f.r.rd); rd2 = allocate_64_register2_w(state, (unsigned int *)state->dst->f.r.rd); if (rd1 != ECX && rd2 != ECX) { mov_reg32_reg32(state, rd1, rt1); mov_reg32_reg32(state, rd2, rt2); shrd_reg32_reg32_cl(state, rd1,rd2); sar_reg32_cl(state, rd2); test_reg32_imm32(state, ECX, 0x20); je_rj(state, 5); mov_reg32_reg32(state, rd1, rd2); // 2 sar_reg32_imm8(state, rd2, 31); // 3 } else { int temp1, temp2; force_32(state, ECX); temp1 = lru_register(state); temp2 = lru_register_exc1(state, temp1); free_register(state, temp1); free_register(state, temp2); mov_reg32_reg32(state, temp1, rt1); mov_reg32_reg32(state, temp2, rt2); shrd_reg32_reg32_cl(state, temp1, temp2); sar_reg32_cl(state, temp2); test_reg32_imm32(state, ECX, 0x20); je_rj(state, 5); mov_reg32_reg32(state, temp1, temp2); // 2 sar_reg32_imm8(state, temp2, 31); // 3 mov_reg32_reg32(state, rd1, temp1); mov_reg32_reg32(state, rd2, temp2); } #endif }
void gendsrav() { #ifdef INTERPRET_DSRAV gencallinterp((unsigned long)DSRAV, 0); #else int rt1, rt2, rd1, rd2; allocate_register_manually(ECX, (unsigned long *)dst->f.r.rs); rt1 = allocate_64_register1((unsigned long *)dst->f.r.rt); rt2 = allocate_64_register2((unsigned long *)dst->f.r.rt); rd1 = allocate_64_register1_w((unsigned long *)dst->f.r.rd); rd2 = allocate_64_register2_w((unsigned long *)dst->f.r.rd); if (rd1 != ECX && rd2 != ECX) { mov_reg32_reg32(rd1, rt1); mov_reg32_reg32(rd2, rt2); shrd_reg32_reg32_cl(rd1,rd2); sar_reg32_cl(rd2); test_reg32_imm32(ECX, 0x20); je_rj(5); mov_reg32_reg32(rd1, rd2); // 2 sar_reg32_imm8(rd2, 31); // 3 } else { int temp1, temp2; force_32(ECX); temp1 = lru_register(); temp2 = lru_register_exc1(temp1); free_register(temp1); free_register(temp2); mov_reg32_reg32(temp1, rt1); mov_reg32_reg32(temp2, rt2); shrd_reg32_reg32_cl(temp1, temp2); sar_reg32_cl(temp2); test_reg32_imm32(ECX, 0x20); je_rj(5); mov_reg32_reg32(temp1, temp2); // 2 sar_reg32_imm8(temp2, 31); // 3 mov_reg32_reg32(rd1, temp1); mov_reg32_reg32(rd2, temp2); } #endif }
void gendsrlv(void) { #ifdef INTERPRET_DSRLV gencallinterp((unsigned int)cached_interpreter_table.DSRLV, 0); #else int rt1, rt2, rd1, rd2; allocate_register_manually(ECX, (unsigned int *)dst->f.r.rs); rt1 = allocate_64_register1((unsigned int *)dst->f.r.rt); rt2 = allocate_64_register2((unsigned int *)dst->f.r.rt); rd1 = allocate_64_register1_w((unsigned int *)dst->f.r.rd); rd2 = allocate_64_register2_w((unsigned int *)dst->f.r.rd); if (rd1 != ECX && rd2 != ECX) { mov_reg32_reg32(rd1, rt1); mov_reg32_reg32(rd2, rt2); shrd_reg32_reg32_cl(rd1,rd2); shr_reg32_cl(rd2); test_reg32_imm32(ECX, 0x20); je_rj(4); mov_reg32_reg32(rd1, rd2); // 2 xor_reg32_reg32(rd2, rd2); // 2 } else { int temp1, temp2; force_32(ECX); temp1 = lru_register(); temp2 = lru_register_exc1(temp1); free_register(temp1); free_register(temp2); mov_reg32_reg32(temp1, rt1); mov_reg32_reg32(temp2, rt2); shrd_reg32_reg32_cl(temp1, temp2); shr_reg32_cl(temp2); test_reg32_imm32(ECX, 0x20); je_rj(4); mov_reg32_reg32(temp1, temp2); // 2 xor_reg32_reg32(temp2, temp2); // 2 mov_reg32_reg32(rd1, temp1); mov_reg32_reg32(rd2, temp2); } #endif }
void gendsra(usf_state_t * state) { #ifdef INTERPRET_DSRA gencallinterp(state, (unsigned int)state->current_instruction_table.DSRA, 0); #else int rt1 = allocate_64_register1(state, (unsigned int *)state->dst->f.r.rt); int rt2 = allocate_64_register2(state, (unsigned int *)state->dst->f.r.rt); int rd1 = allocate_64_register1_w(state, (unsigned int *)state->dst->f.r.rd); int rd2 = allocate_64_register2_w(state, (unsigned int *)state->dst->f.r.rd); mov_reg32_reg32(state, rd1, rt1); mov_reg32_reg32(state, rd2, rt2); shrd_reg32_reg32_imm8(state, rd1, rd2, state->dst->f.r.sa); sar_reg32_imm8(state, rd2, state->dst->f.r.sa); if (state->dst->f.r.sa & 0x20) { mov_reg32_reg32(state, rd1, rd2); sar_reg32_imm8(state, rd2, 31); } #endif }
void gendsrl(void) { #ifdef INTERPRET_DSRL gencallinterp((unsigned int)cached_interpreter_table.DSRL, 0); #else int rt1 = allocate_64_register1((unsigned int *)dst->f.r.rt); int rt2 = allocate_64_register2((unsigned int *)dst->f.r.rt); int rd1 = allocate_64_register1_w((unsigned int *)dst->f.r.rd); int rd2 = allocate_64_register2_w((unsigned int *)dst->f.r.rd); mov_reg32_reg32(rd1, rt1); mov_reg32_reg32(rd2, rt2); shrd_reg32_reg32_imm8(rd1, rd2, dst->f.r.sa); shr_reg32_imm8(rd2, dst->f.r.sa); if (dst->f.r.sa & 0x20) { mov_reg32_reg32(rd1, rd2); xor_reg32_reg32(rd2, rd2); } #endif }
void gendsra() { #ifdef INTERPRET_DSRA gencallinterp((unsigned long)DSRA, 0); #else int rt1 = allocate_64_register1((unsigned long *)dst->f.r.rt); int rt2 = allocate_64_register2((unsigned long *)dst->f.r.rt); int rd1 = allocate_64_register1_w((unsigned long *)dst->f.r.rd); int rd2 = allocate_64_register2_w((unsigned long *)dst->f.r.rd); mov_reg32_reg32(rd1, rt1); mov_reg32_reg32(rd2, rt2); shrd_reg32_reg32_imm8(rd1, rd2, dst->f.r.sa); sar_reg32_imm8(rd2, dst->f.r.sa); if (dst->f.r.sa & 0x20) { mov_reg32_reg32(rd1, rd2); sar_reg32_imm8(rd2, 31); } #endif }