void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; /* Must come first to enable PCI MMCONF. */ amd_initmmio(); hudson_lpc_port80(); if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); post_code(0x31); console_init(); } /* Halt if there was a built in self test failure */ post_code(0x34); report_bist_failure(bist); /* Load MPB */ val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); post_code(0x37); agesawrapper_amdinitreset(); post_code(0x39); agesawrapper_amdinitearly(); int s3resume = acpi_is_wakeup_s3(); if (!s3resume) { post_code(0x40); agesawrapper_amdinitpost(); post_code(0x41); agesawrapper_amdinitenv(); disable_cache_as_ram(); } else { /* S3 detect */ printk(BIOS_INFO, "S3 detected\n"); post_code(0x60); agesawrapper_amdinitresume(); amd_initcpuio(); agesawrapper_amds3laterestore(); post_code(0x61); prepare_for_resume(); } post_code(0x50); copy_and_run(); post_code(0x54); /* Should never see this post code. */ }
AGESA_STATUS agesawrapper_amdinitmid(void) { AGESA_STATUS status; AMD_INTERFACE_PARAMS AmdParamStruct; AMD_MID_PARAMS *MidParam; /* Enable MMIO on AMD CPU Address Map Controller */ amd_initcpuio (); LibAmdMemFill (&AmdParamStruct, 0, sizeof (AMD_INTERFACE_PARAMS), &(AmdParamStruct.StdHeader)); AmdParamStruct.AgesaFunctionName = AMD_INIT_MID; AmdParamStruct.AllocationMethod = PostMemDram; AmdParamStruct.StdHeader.AltImageBasePtr = 0; AmdParamStruct.StdHeader.CalloutPtr = &GetBiosCallout; AmdParamStruct.StdHeader.Func = 0; AmdParamStruct.StdHeader.ImageBasePtr = 0; AmdCreateStruct (&AmdParamStruct); MidParam = (AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr; MidParam->GnbMidConfiguration.iGpuVgaMode = 0;/* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ MidParam->GnbMidConfiguration.GnbIoapicAddress = 0xFEC20000; MidParam->FchInterface.AzaliaController = AzEnable; MidParam->FchInterface.SataClass = CONFIG_HUDSON_SATA_MODE; MidParam->FchInterface.SataEnable = !((CONFIG_HUDSON_SATA_MODE == 0) || (CONFIG_HUDSON_SATA_MODE == 3)); MidParam->FchInterface.IdeEnable = (CONFIG_HUDSON_SATA_MODE == 0) || (CONFIG_HUDSON_SATA_MODE == 3); MidParam->FchInterface.SataIdeMode = (CONFIG_HUDSON_SATA_MODE == 3); status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr); if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); AmdReleaseStruct (&AmdParamStruct); return status; }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; u8 byte; pci_devfn_t dev; amd_initmmio(); /* Set LPC decode enables. */ dev = PCI_DEV(0, 0x14, 3); pci_write_config32(dev, 0x44, 0xff03ffd5); hudson_lpc_port80(); byte = pci_read_config8(dev, 0x48); byte |= 3; /* 2e, 2f */ pci_write_config8(dev, 0x48, byte); if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); post_code(0x31); lpc47n217_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); outb(0x24, 0xcd6); outb(0x1, 0xcd7); outb(0xea, 0xcd6); outb(0x1, 0xcd7); *(u8 *)0xfed80101 = 0x98; console_init(); } /* Halt if there was a built in self test failure */ post_code(0x34); report_bist_failure(bist); /* Load MPB */ val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); post_code(0x37); agesawrapper_amdinitreset(); post_code(0x39); agesawrapper_amdinitearly(); int s3resume = acpi_is_wakeup_s3(); if (!s3resume) { post_code(0x40); agesawrapper_amdinitpost(); post_code(0x41); agesawrapper_amdinitenv(); disable_cache_as_ram(); } else { /* S3 detect */ printk(BIOS_INFO, "S3 detected\n"); post_code(0x60); agesawrapper_amdinitresume(); amd_initcpuio(); agesawrapper_amds3laterestore(); post_code(0x61); prepare_for_resume(); } post_code(0x50); copy_and_run(); post_code(0x54); /* Should never see this post code. */ }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; amd_initmmio(); /* Set LPC decode enables. */ pci_devfn_t dev = PCI_DEV(0, 0x14, 3); pci_write_config32(dev, 0x44, 0xff03ffd5); hudson_lpc_port80(); if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); post_code(0x31); fintek_enable_serial(SERIAL_DEV1, CONFIG_TTYS0_BASE); console_init(); } /* Halt if there was a built in self test failure */ post_code(0x34); report_bist_failure(bist); /* Load MPB */ val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); /* On Larne, after LpcClkDrvSth is set, it needs some time to be stable, because of the buffer ICS551M */ int i; for(i = 0; i < 200000; i++) val = inb(0xcd6); post_code(0x37); agesawrapper_amdinitreset(); post_code(0x38); printk(BIOS_DEBUG, "Got past yangtze_early_setup\n"); post_code(0x39); agesawrapper_amdinitearly(); int s3resume = acpi_is_wakeup_s3(); if (!s3resume) { post_code(0x40); agesawrapper_amdinitpost(); post_code(0x41); agesawrapper_amdinitenv(); /* TODO: Disable cache is not ok. */ disable_cache_as_ram(); } else { /* S3 detect */ printk(BIOS_INFO, "S3 detected\n"); post_code(0x60); agesawrapper_amdinitresume(); amd_initcpuio(); agesawrapper_amds3laterestore(); post_code(0x61); prepare_for_resume(); } outb(0xEA, 0xCD6); outb(0x1, 0xcd7); post_code(0x50); copy_and_run(); post_code(0x54); /* Should never see this post code. */ }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; u8 byte; device_t dev; #if IS_ENABLED(CONFIG_POST_DEVICE_PCI_PCIE) hudson_pci_port80(); #endif #if IS_ENABLED(CONFIG_POST_DEVICE_LPC) hudson_lpc_port80(); #endif amd_initmmio(); post_code(0x29); if (!cpu_init_detectedx && boot_cpu()) { /* enable SIO LPC decode */ dev = PCI_DEV(0, 0x14, 3); byte = pci_read_config8(dev, 0x48); byte |= 3; /* 2e, 2f */ pci_write_config8(dev, 0x48, byte); /* enable serial decode */ byte = pci_read_config8(dev, 0x44); byte |= (1 << 6); /* 0x3f8 */ pci_write_config8(dev, 0x44, byte); post_code(0x30); /* enable SB MMIO space */ outb(0x24, 0xcd6); outb(0x1, 0xcd7); /* enable SIO clock */ sbxxx_enable_48mhzout(); /* Enable serial console */ fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); /* turn on secondary smbus at b20 */ outb(0x28, 0xcd6); byte = inb(0xcd7); byte |= 1; outb(byte, 0xcd7); /* set DDR3 voltage */ byte = CONFIG_BOARD_MSI_MS7721_DDR3_VOLT_VAL; /* default is byte = 0x0, so no need to set it in this case */ if (byte) do_smbus_write_byte(0xb20, 0x15, 0x3, byte); } /* Halt if there was a built in self test failure */ post_code(0x34); report_bist_failure(bist); /* Load MPB */ val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x (cpu_init_detectedx: %08lx)\n", val, cpu_init_detectedx); post_code(0x37); printk(BIOS_DEBUG, "agesawrapper_amdinitreset()\n"); agesawrapper_amdinitreset(); post_code(0x39); printk(BIOS_DEBUG, "agesawrapper_amdinitearly()\n"); agesawrapper_amdinitearly(); post_code(0x42); int s3resume = acpi_is_wakeup_s3(); if (!s3resume) { printk(BIOS_DEBUG, "Cold boot\n"); post_code(0x40); agesawrapper_amdinitpost(); post_code(0x41); agesawrapper_amdinitenv(); disable_cache_as_ram(); } else { /* S3 detect */ printk(BIOS_INFO, "S3 detected\n"); post_code(0x60); agesawrapper_amdinitresume(); amd_initcpuio(); agesawrapper_amds3laterestore(); post_code(0x61); prepare_for_resume(); } post_code(0x50); printk(BIOS_DEBUG, "Copy and run...\n"); copy_and_run(); post_code(0x54); /* Should never see this post code. */ }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val, t32; u32 *addr32; /* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for * LpcClk[1:0]". To be consistent with Parmer, setting to 4mA * even though the register is not documented in the Kabini BKDG. * Otherwise the serial output is bad code. */ //outb(0xD2, 0xcd6); //outb(0x00, 0xcd7); amd_initmmio(); /* Set LPC decode enables. */ pci_devfn_t dev = PCI_DEV(0, 0x14, 3); pci_write_config32(dev, 0x44, 0xff03ffd5); hudson_lpc_port80(); /* Enable the AcpiMmio space */ outb(0x24, 0xcd6); outb(0x1, 0xcd7); /* Set auxiliary output clock frequency on OSCOUT1 pin to be 48MHz */ addr32 = (u32 *)0xfed80e28; t32 = *addr32; t32 &= 0xfff8ffff; *addr32 = t32; /* Enable Auxiliary Clock1, disable FCH 14 MHz OscClk */ addr32 = (u32 *)0xfed80e40; t32 = *addr32; t32 &= 0xffffbffb; *addr32 = t32; if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); post_code(0x31); /* w83627uhg has a default clk of 48MHz, p.9 of data-sheet */ winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); } /* Halt if there was a built in self test failure */ post_code(0x34); report_bist_failure(bist); /* Load MPB */ val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); /* On Larne, after LpcClkDrvSth is set, it needs some time to be stable, because of the buffer ICS551M */ int i; for(i = 0; i < 200000; i++) val = inb(0xcd6); post_code(0x37); agesawrapper_amdinitreset(); post_code(0x38); printk(BIOS_DEBUG, "Got past yangtze_early_setup\n"); post_code(0x39); agesawrapper_amdinitearly(); int s3resume = acpi_is_wakeup_s3(); if (!s3resume) { post_code(0x40); agesawrapper_amdinitpost(); post_code(0x41); agesawrapper_amdinitenv(); /* TODO: Disable cache is not ok. */ disable_cache_as_ram(); } else { /* S3 detect */ printk(BIOS_INFO, "S3 detected\n"); post_code(0x60); agesawrapper_amdinitresume(); amd_initcpuio(); agesawrapper_amds3laterestore(); post_code(0x61); prepare_for_resume(); } outb(0xEA, 0xCD6); outb(0x1, 0xcd7); post_code(0x50); copy_and_run(); post_code(0x54); /* Should never see this post code. */ }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; /* Must come first to enable PCI MMCONF. */ amd_initmmio(); /* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for * LpcClk[1:0]". To be consistent with Parmer, setting to 4mA * even though the register is not documented in the Kabini BKDG. * Otherwise the serial output is bad code. */ outb(0xD2, 0xcd6); outb(0x00, 0xcd7); /* Set LPC decode enables. */ pci_devfn_t dev = PCI_DEV(0, 0x14, 3); pci_write_config32(dev, 0x44, 0xff03ffd5); hudson_lpc_port80(); if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); post_code(0x31); console_init(); } /* Halt if there was a built in self test failure */ post_code(0x34); report_bist_failure(bist); /* Load MPB */ val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); /* On Larne, after LpcClkDrvSth is set, it needs some time to be stable, because of the buffer ICS551M */ int i; for(i = 0; i < 200000; i++) val = inb(0xcd6); post_code(0x37); agesawrapper_amdinitreset(); post_code(0x38); printk(BIOS_DEBUG, "Got past yangtze_early_setup\n"); post_code(0x39); agesawrapper_amdinitearly(); int s3resume = acpi_is_wakeup_s3(); if (!s3resume) { post_code(0x40); agesawrapper_amdinitpost(); post_code(0x41); agesawrapper_amdinitenv(); /* TODO: Disable cache is not ok. */ disable_cache_as_ram(); } else { /* S3 detect */ printk(BIOS_INFO, "S3 detected\n"); post_code(0x60); agesawrapper_amdinitresume(); amd_initcpuio(); agesawrapper_amds3laterestore(); post_code(0x61); prepare_for_resume(); } outb(0xEA, 0xCD6); outb(0x1, 0xcd7); post_code(0x50); copy_and_run(); post_code(0x54); /* Should never see this post code. */ }