static int vi_set_uvd_clock(struct amdgpu_device *adev, u32 clock, u32 cntl_reg, u32 status_reg) { int r, i; struct atom_clock_dividers dividers; uint32_t tmp; r = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, clock, false, ÷rs); if (r) return r; tmp = RREG32_SMC(cntl_reg); tmp &= ~(CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK | CG_DCLK_CNTL__DCLK_DIVIDER_MASK); tmp |= dividers.post_divider; WREG32_SMC(cntl_reg, tmp); for (i = 0; i < 100; i++) { if (RREG32_SMC(status_reg) & CG_DCLK_STATUS__DCLK_STATUS_MASK) break; mdelay(10); } if (i == 100) return -ETIMEDOUT; return 0; }
static int vi_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) { int r, i; struct atom_clock_dividers dividers; u32 tmp; r = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, ecclk, false, ÷rs); if (r) return r; for (i = 0; i < 100; i++) { if (RREG32_SMC(ixCG_ECLK_STATUS) & CG_ECLK_STATUS__ECLK_STATUS_MASK) break; mdelay(10); } if (i == 100) return -ETIMEDOUT; tmp = RREG32_SMC(ixCG_ECLK_CNTL); tmp &= ~(CG_ECLK_CNTL__ECLK_DIR_CNTL_EN_MASK | CG_ECLK_CNTL__ECLK_DIVIDER_MASK); tmp |= dividers.post_divider; WREG32_SMC(ixCG_ECLK_CNTL, tmp); for (i = 0; i < 100; i++) { if (RREG32_SMC(ixCG_ECLK_STATUS) & CG_ECLK_STATUS__ECLK_STATUS_MASK) break; mdelay(10); } if (i == 100) return -ETIMEDOUT; return 0; }