void
acinit(void)
{
Mach *mp;
Proc *pp;
/*
* Lower the priority of the apic to 0,
* to accept interrupts.
* Raise it later if needed to disable them.
*/
apicpri(0);
/*
* Be sure a few assembler assumptions still hold.
* Someone moved m->stack and I had fun debugging...
*/
mp = 0;
pp = 0;
assert((uintptr)&mp->proc == 16);
assert((uintptr)&pp->dbgreg == 24);
assert((uintptr)&mp->stack == 24);
}
void
squidboy(int apicno)
{
char *n[] = {
[NIXAC] "AC",
[NIXTC] "TC",
[NIXKC] "KC"
};
vlong hz;
sys->machptr[m->machno] = m;
setmachsched(m);
/*
* Need something for initial delays
* until a timebase is worked out.
*/
m->cpuhz = 2000000000ll;
m->cpumhz = 2000;
m->perf.period = 1;
m->nixtype = NIXAC;
DBG("Hello Squidboy %d %d\n", apicno, m->machno);
vsvminit(MACHSTKSZ, m->nixtype);
/*
* Beware the Curse of The Non-Interruptable Were-Temporary.
*/
hz = archhz();
if(hz == 0)
ndnr();
m->cpuhz = hz;
m->cyclefreq = hz;
m->cpumhz = hz/1000000ll;
mmuinit();
if(!apiconline())
ndnr();
fpuinit();
acmodeset(m->nixtype);
m->splpc = 0;
m->online = 1;
/*
* CAUTION: no time sync done, etc.
*/
DBG("Wait for the thunderbirds!\n");
while(!active.thunderbirdsarego)
;
wrmsr(0x10, sys->epoch);
m->rdtsc = rdtsc();
print("cpu%d color %d role %s tsc %lld\n",
m->machno, corecolor(m->machno), n[m->nixtype], m->rdtsc);
switch(m->nixtype){
case NIXAC:
acmmuswitch();
acinit();
adec(&active.nbooting);
ainc(&active.nonline); /* this was commented out */
acsched();
panic("squidboy");
break;
case NIXTC:
/*
* We only need the idt and syscall entry point actually.
* At boot time the boot processor might set our role after
* we have decided to become an AC.
*/
vsvminit(MACHSTKSZ, NIXTC);
/*
* Enable the timer interrupt.
*/
apicpri(0);
timersinit();
adec(&active.nbooting);
ainc(&active.nonline); /* this was commented out */
schedinit();
break;
}
panic("squidboy returns (type %d)", m->nixtype);
}
void
squidboy(int apicno, Mach *m)
{
// FIX QEMU. extern int64_t hz;
int64_t hz;
sys->machptr[m->machno] = m;
/*
* Need something for initial delays
* until a timebase is worked out.
*/
m->cpuhz = 2000000000ll;
m->cpumhz = 2000;
m->perf.period = 1;
m->nixtype = NIXAC;
// no NIXAC for now.
m->nixtype = NIXTC;
// NOTE: you can't do ANYTHING here before vsvminit.
// PRINT WILL PANIC. So wait.
vsvminit(MACHSTKSZ, m->nixtype, m);
//DBG("Hello squidboy %d %d\n", apicno, m->machno);
/*
* Beware the Curse of The Non-Interruptable Were-Temporary.
*/
hz = archhz();
/* Intel cpu's in archk10 must be reviewed */
if(hz == 0)
hz = 2000000000ll;
m->cpuhz = hz;
m->cyclefreq = hz;
m->cpumhz = hz/1000000ll;
mmuinit();
if(!apiconline())
ndnr();
fpuinit();
acmodeset(m->nixtype);
m->splpc = 0;
m->online = 1;
/*
* CAUTION: no time sync done, etc.
* Stupid print to avoid up = nil or
* last cpu couldn't start in nixquids.
*/
DBG("Wait for the thunderbirds!\n");
while(!active.thunderbirdsarego)
;
wrmsr(0x10, sys->epoch);
m->rdtsc = rdtsc();
print("cpu%d color %d role %s tsc %lld\n",
m->machno, corecolor(m->machno), rolename[m->nixtype], m->rdtsc);
switch(m->nixtype){
case NIXAC:
acmmuswitch();
acinit();
adec(&active.nbooting);
ainc(&active.nonline); /* this was commented out */
acsched();
panic("squidboy");
break;
case NIXTC:
/*
* We only need the idt and syscall entry point actually.
* At boot time the boot processor might set our role after
* we have decided to become an AC.
*/
vsvminit(MACHSTKSZ, NIXTC, m);
/*
* Enable the timer interrupt.
*/
apictimerenab();
apicpri(0);
timersinit();
adec(&active.nbooting);
ainc(&active.nonline);
/* Ready? steady? going to timer */
ndnr();
schedinit();
break;
}
panic("squidboy returns (type %d)", m->nixtype);
}