static void
jmpata_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa)
{
struct jmide_softc *jmidesc = (struct jmide_softc *)sc;
int channel;
pcireg_t interface;
struct pciide_channel *cp;
if (pciide_chipen(sc, pa) == 0)
return;
aprint_verbose("%s: bus-master DMA support present", JM_NAME(jmidesc));
pciide_mapreg_dma(sc, pa);
aprint_verbose("\n");
sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
if (sc->sc_dma_ok) {
sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA;
sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
}
sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
sc->sc_wdcdev.sc_atac.atac_set_modes = jmpata_setup_channel;
sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS;
sc->sc_wdcdev.wdc_maxdrives = 2;
wdc_allocate_regs(&sc->sc_wdcdev);
/*
* can't rely on the PCI_CLASS_REG content if the chip was in raid
* mode. We have to fake interface
*/
interface = PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1);
for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
channel++) {
cp = &sc->pciide_channels[channel];
if (pciide_chansetup(sc, channel, interface) == 0)
continue;
aprint_normal("%s: %s channel is ", JM_NAME(jmidesc),
PCIIDE_CHANNEL_NAME(channel));
switch(jmidesc->sc_chan_type[channel]) {
case TYPE_PATA:
aprint_normal("PATA");
break;
case TYPE_SATA:
aprint_normal("SATA");
break;
case TYPE_NONE:
aprint_normal("unused");
break;
default:
aprint_normal("impossible");
panic("jmide: wrong/uninitialised channel type");
}
aprint_normal("\n");
if (jmidesc->sc_chan_type[channel] == TYPE_NONE) {
cp->ata_channel.ch_flags |= ATACH_DISABLED;
continue;
}
pciide_mapchan(pa, cp, interface, pciide_pci_intr);
}
}
static void
artisea_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa)
{
struct pciide_channel *cp;
bus_size_t cmdsize, ctlsize;
pcireg_t interface;
int channel;
if (pciide_chipen(sc, pa) == 0)
return;
interface = PCI_INTERFACE(pa->pa_class);
if (interface == 0) {
artisea_chip_map_dpa (sc, pa);
return;
}
aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev,
"bus-master DMA support present");
#ifdef PCIIDE_I31244_DISABLEDMA
if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_31244 &&
PCI_REVISION(pa->pa_class) == 0) {
aprint_verbose(" but disabled due to rev. 0");
sc->sc_dma_ok = 0;
} else
#endif
pciide_mapreg_dma(sc, pa);
aprint_verbose("\n");
/*
* XXX Configure LEDs to show activity.
*/
sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
if (sc->sc_dma_ok) {
sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA;
sc->sc_wdcdev.irqack = pciide_irqack;
sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
}
sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel;
sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS;
wdc_allocate_regs(&sc->sc_wdcdev);
for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
channel++) {
cp = &sc->pciide_channels[channel];
if (pciide_chansetup(sc, channel, interface) == 0)
continue;
pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize,
pciide_pci_intr);
}
}
static void
makeonenode(char *buf, size_t len, devmajor_t blk, devmajor_t chr,
devminor_t dmin, const char *base, int c1, int c2)
{
char cstr1[2] = {0,0}, cstr2[2] = {0,0};
register_t rv;
int error;
if (c1 != -1) {
cstr1[0] = '0' + c1;
cstr1[1] = '\0';
}
if (c2 != -1) {
cstr2[0] = 'a' + c2;
cstr2[1] = '\0';
}
/* block device */
snprintf(buf, len, "/dev/%s%s%s", base, cstr1, cstr2);
if (blk != NODEVMAJOR) {
switch (doesitexist(buf, true, blk, dmin)) {
case DIFFERENT:
aprint_verbose("mkdevnodes: block device %s "
"already exists\n", buf);
break;
case NOTEXIST:
if ((error = do_sys_mknod(curlwp, buf, 0600 | S_IFBLK,
makedev(blk, dmin), &rv, UIO_SYSSPACE)) != 0)
aprint_verbose("mkdevnodes: failed to "
"create %s: %d\n", buf, error);
break;
case SAME:
/* done */
break;
}
snprintf(buf, len, "/dev/r%s%s%s", base, cstr1, cstr2);
}
switch (doesitexist(buf, true, chr, dmin)) {
case DIFFERENT:
aprint_verbose("mkdevnodes: character device %s "
"already exists\n", buf);
break;
case NOTEXIST:
if ((error = do_sys_mknod(curlwp, buf, 0600 | S_IFCHR,
makedev(chr, dmin), &rv, UIO_SYSSPACE)) != 0)
aprint_verbose("mkdevnodes: failed to "
"create %s: %d\n", buf, error);
break;
case SAME:
/* yeehaa */
break;
}
}
static void
ibm82660_print(struct pci_attach_args *pa, struct device *self)
{
pcireg_t reg1;
#ifdef PREP_BUS_SPACE_IO
pcireg_t reg2;
#endif
const char *s1, *s2;
reg1 = pci_conf_read(pa->pa_pc, pa->pa_tag,
IBM_82660_CACHE_STATUS);
#ifdef PREP_BUS_SPACE_IO
reg2 = in32rb(PREP_BUS_SPACE_IO+IBM_82660_SYSTEM_CTRL);
if (reg2 & IBM_82660_SYSTEM_CTRL_L2_EN) {
if (reg1 & IBM_82660_CACHE_STATUS_L2_EN)
s1 = "internal enabled";
else
s1 = "enabled";
if (reg2 & IBM_82660_SYSTEM_CTRL_L2_MI)
s2 = "(normal operation)";
else
s2 = "(miss updates inhibited)";
} else {
s1 = "disabled";
s2 = "";
}
#else
if (reg1 & IBM_82660_CACHE_STATUS_L2_EN)
s1 = "enabled";
else
s1 = "disabled";
s2 = "";
#endif
aprint_normal("%s: L1: %s L2: %s %s\n", self->dv_xname,
(reg1 & IBM_82660_CACHE_STATUS_L1_EN) ? "enabled" : "disabled",
s1, s2);
reg1 = pci_conf_read(pa->pa_pc, pa->pa_tag, IBM_82660_OPTIONS_1);
aprint_verbose("%s: MCP# assertion %s "
"TEA# assertion %s\n", self->dv_xname,
(reg1 & IBM_82660_OPTIONS_1_MCP) ? "enabled" : "disabled",
(reg1 & IBM_82660_OPTIONS_1_TEA) ? "enabled" : "disabled");
aprint_verbose("%s: PCI/ISA I/O mapping %s\n", self->dv_xname,
(reg1 & IBM_82660_OPTIONS_1_ISA) ? "contiguous" : "non-contiguous");
reg1 = pci_conf_read(pa->pa_pc, pa->pa_tag, IBM_82660_OPTIONS_3);
aprint_normal("%s: DRAM %s (%s) SRAM %s\n", self->dv_xname,
(reg1 & IBM_82660_OPTIONS_3_DRAM) ? "EDO" : "standard",
(reg1 & IBM_82660_OPTIONS_3_ECC) ? "ECC" : "parity",
(reg1 & IBM_82660_OPTIONS_3_SRAM) ? "sync" : "async");
aprint_verbose("%s: Snoop mode %s\n", self->dv_xname,
(reg1 & IBM_82660_OPTIONS_3_SNOOP) ? "603" : "601/604");
}
static void
via_vt6421_mapreg_dma(struct pciide_softc *sc, const struct pci_attach_args *pa)
{
struct pciide_channel *pc;
int chan, reg;
bus_size_t size;
sc->sc_dma_ok = (pci_mapreg_map(pa, PCIIDE_REG_BUS_MASTER_DMA,
PCI_MAPREG_TYPE_IO, 0, &sc->sc_dma_iot, &sc->sc_dma_ioh,
NULL, &sc->sc_dma_ios) == 0);
sc->sc_dmat = pa->pa_dmat;
if (sc->sc_dma_ok == 0) {
aprint_verbose(", but unused (couldn't map registers)");
} else {
sc->sc_wdcdev.dma_arg = sc;
sc->sc_wdcdev.dma_init = pciide_dma_init;
sc->sc_wdcdev.dma_start = pciide_dma_start;
sc->sc_wdcdev.dma_finish = pciide_dma_finish;
}
if (device_cfdata(sc->sc_wdcdev.sc_atac.atac_dev)->cf_flags &
PCIIDE_OPTIONS_NODMA) {
aprint_verbose(
", but unused (forced off by config file)");
sc->sc_dma_ok = 0;
}
if (sc->sc_dma_ok == 0)
return;
for (chan = 0; chan < 4; chan++) {
pc = &sc->pciide_channels[chan];
for (reg = 0; reg < IDEDMA_NREGS; reg++) {
size = 4;
if (size > (IDEDMA_SCH_OFFSET - reg))
size = IDEDMA_SCH_OFFSET - reg;
if (bus_space_subregion(sc->sc_dma_iot, sc->sc_dma_ioh,
IDEDMA_SCH_OFFSET * chan + reg, size,
&pc->dma_iohs[reg]) != 0) {
sc->sc_dma_ok = 0;
aprint_verbose(", but can't subregion offset "
"%d size %lu",
reg, (u_long)size);
return;
}
}
}
}
/* this could/should be mi_attach_cpu? */
void
rump_cpus_bootstrap(int *nump)
{
struct cpu_info *ci;
int num = *nump;
int i;
if (num > MAXCPUS) {
aprint_verbose("CPU limit: %d wanted, %d (MAXCPUS) "
"available (adjusted)\n", num, MAXCPUS);
num = MAXCPUS;
}
for (i = 0; i < num; i++) {
ci = &rump_cpus[i];
ci->ci_index = i;
}
kcpuset_create(&kcpuset_attached, true);
kcpuset_create(&kcpuset_running, true);
/* attach first cpu for bootstrap */
rump_cpu_attach(&rump_cpus[0]);
ncpu = 1;
*nump = num;
}
static void
p160x_pci_intr_fixup(int bus, int dev, int *line)
{
aprint_verbose("p160x_pci_intr_fixup: bus=%d, dev=%d, line=%d\n",
bus, dev, *line);
}
/*
* We can obtain the information about MCA bus presence via
* GET CONFIGURATION BIOS call - int 0x15, function 0xc0.
* The call returns a pointer to memory place with the configuration block
* in es:bx (on AT-compatible, e.g. all we care about, computers).
*
* Configuration block contains block length (2 bytes), model
* number (1 byte), submodel number (1 byte), BIOS revision
* (1 byte) and up to 5 feature bytes. We only care about
* first feature byte.
*/
void
mca_busprobe(void)
{
struct bioscallregs regs;
struct bios_config *scp;
paddr_t paddr;
char buf[80];
memset(®s, 0, sizeof(regs));
regs.AH = 0xc0;
bioscall(0x15, ®s);
if ((regs.EFLAGS & PSL_C) || regs.AH != 0) {
aprint_verbose("BIOS CFG: Not supported. Not AT-compatible?\n");
return;
}
paddr = (regs.ES << 4) + regs.BX;
scp = (struct bios_config *)ISA_HOLE_VADDR(paddr);
bitmask_snprintf((scp->feature2 << 8) | scp->feature1,
"\20"
"\01MCA+ISA"
"\02MCA"
"\03EBDA"
"\04WAITEV"
"\05KBDINT"
"\06RTC"
"\07IC2"
"\010DMA3B"
"\011res"
"\012DSTR"
"\013n8042"
"\014CPUF"
"\015MMF"
"\016GPDF"
"\017KBDF"
"\020DMA32\n",
buf, sizeof(buf));
aprint_verbose("BIOS CFG: Model-SubM-Rev: %02x-%02x-%02x, 0x%s\n",
scp->model, scp->submodel, scp->bios_rev, buf);
MCA_system = (scp->feature1 & FEATURE_MCABUS) ? 1 : 0;
}
static int
allocif(int unit, struct shmif_sc **scp)
{
uint8_t enaddr[ETHER_ADDR_LEN] = { 0xb2, 0xa0, 0x00, 0x00, 0x00, 0x00 };
struct shmif_sc *sc;
struct ifnet *ifp;
uint32_t randnum;
int error;
randnum = cprng_fast32();
memcpy(&enaddr[2], &randnum, sizeof(randnum));
sc = kmem_zalloc(sizeof(*sc), KM_SLEEP);
sc->sc_memfd = -1;
sc->sc_unit = unit;
sc->sc_uuid = cprng_fast64();
ifp = &sc->sc_ec.ec_if;
snprintf(ifp->if_xname, sizeof(ifp->if_xname), "shmif%d", unit);
ifp->if_softc = sc;
ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
ifp->if_init = shmif_init;
ifp->if_ioctl = shmif_ioctl;
ifp->if_start = shmif_start;
ifp->if_stop = shmif_stop;
ifp->if_mtu = ETHERMTU;
ifp->if_dlt = DLT_EN10MB;
mutex_init(&sc->sc_mtx, MUTEX_DEFAULT, IPL_NONE);
cv_init(&sc->sc_cv, "shmifcv");
if_initialize(ifp);
ether_ifattach(ifp, enaddr);
if_register(ifp);
aprint_verbose("shmif%d: Ethernet address %s\n",
unit, ether_sprintf(enaddr));
if (scp)
*scp = sc;
error = 0;
if (rump_threads) {
error = kthread_create(PRI_NONE,
KTHREAD_MPSAFE | KTHREAD_MUSTJOIN, NULL,
shmif_rcv, ifp, &sc->sc_rcvl, "shmif");
} else {
printf("WARNING: threads not enabled, shmif NOT working\n");
}
if (error) {
shmif_unclone(ifp);
}
return error;
}
void
ata_print_modes(struct ata_channel *chp)
{
struct atac_softc *atac = chp->ch_atac;
int drive;
struct ata_drive_datas *drvp;
KASSERT(chp->ch_ndrives == 0 || chp->ch_drive != NULL);
for (drive = 0; drive < chp->ch_ndrives; drive++) {
drvp = &chp->ch_drive[drive];
if (drvp->drive_type == ATA_DRIVET_NONE ||
drvp->drv_softc == NULL)
continue;
aprint_verbose("%s(%s:%d:%d): using PIO mode %d",
device_xname(drvp->drv_softc),
device_xname(atac->atac_dev),
chp->ch_channel, drvp->drive, drvp->PIO_mode);
#if NATA_DMA
if (drvp->drive_flags & ATA_DRIVE_DMA)
aprint_verbose(", DMA mode %d", drvp->DMA_mode);
#if NATA_UDMA
if (drvp->drive_flags & ATA_DRIVE_UDMA) {
aprint_verbose(", Ultra-DMA mode %d", drvp->UDMA_mode);
if (drvp->UDMA_mode == 2)
aprint_verbose(" (Ultra/33)");
else if (drvp->UDMA_mode == 4)
aprint_verbose(" (Ultra/66)");
else if (drvp->UDMA_mode == 5)
aprint_verbose(" (Ultra/100)");
else if (drvp->UDMA_mode == 6)
aprint_verbose(" (Ultra/133)");
}
#endif /* NATA_UDMA */
#endif /* NATA_DMA */
#if NATA_DMA || NATA_PIOBM
if (0
#if NATA_DMA
|| (drvp->drive_flags & (ATA_DRIVE_DMA | ATA_DRIVE_UDMA))
#endif
#if NATA_PIOBM
/* PIOBM capable controllers use DMA for PIO commands */
|| (atac->atac_cap & ATAC_CAP_PIOBM)
#endif
)
aprint_verbose(" (using DMA)");
#endif /* NATA_DMA || NATA_PIOBM */
aprint_verbose("\n");
}
}
static int
systm_aprint_verbose(lua_State *L)
{
const char *s;
s = lua_tostring(L, -1);
if (s)
aprint_verbose("%s", s);
return 0;
}
static int
adm1026_ident(struct adm1026_softc *sc)
{
uint8_t val;
int err;
/* Manufacturer ID and revision/stepping */
err = adm1026_read_reg(sc, ADM1026_ID, &val);
if (err || val != ADM1026_MANF_ID) {
aprint_verbose("adm1026_ident: "
"manufacturer ID invalid or missing\n");
return 0;
}
err = adm1026_read_reg(sc, ADM1026_REV, &sc->sc_rev);
if (err || ADM1026_REVISION(sc->sc_rev) != ADM1026_MANF_REV) {
aprint_verbose("adm1026_ident: "
"manufacturer revision invalid or missing\n");
return 0;
}
return 1;
}
void
cninit(void)
{
char name[32];
ofwoea_bootstrap_console();
OFPRINTF("console node: %08x\n", console_node);
if (console_node == -1)
goto nocons;
memset(name, 0, sizeof(name));
if (OF_getprop(console_node, "device_type", name, sizeof(name)) == -1)
goto nocons;
OFPRINTF("console type: %s\n", name);
if (strcmp(name, "serial") == 0) {
struct consdev *cp;
#ifdef PMAC_G5
/* The MMU hasn't been initialized yet, use failsafe for now */
extern struct consdev failsafe_cons;
cp = &failsafe_cons;
cn_tab = cp;
(*cp->cn_probe)(cp);
(*cp->cn_init)(cp);
aprint_verbose("Early G5 console initialized\n");
return;
#endif /* PMAC_G5 */
#if (NZSTTY > 0) && !defined(MAMBO)
OF_getprop(console_node, "name", name, sizeof(name));
if (strcmp(name, "ch-a") == 0 || strcmp(name, "ch-b") == 0) {
cp = &consdev_zs;
(*cp->cn_probe)(cp);
(*cp->cn_init)(cp);
cn_tab = cp;
}
return;
#endif /* NZTTY */
/* fallback to OFW boot console */
cp = &consdev_ofwbootcons;
cn_tab = cp;
return;
}
else
cninit_kd();
nocons:
return;
}
static void
piixsata_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa)
{
struct pciide_channel *cp;
pcireg_t interface, cmdsts;
int channel;
if (pciide_chipen(sc, pa) == 0)
return;
aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev,
"bus-master DMA support present");
pciide_mapreg_dma(sc, pa);
aprint_verbose("\n");
sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
if (sc->sc_dma_ok) {
sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA;
sc->sc_wdcdev.irqack = pciide_irqack;
/* Do all revisions require DMA alignment workaround? */
sc->sc_wdcdev.dma_init = piix_dma_init;
sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
}
sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel;
sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS;
sc->sc_wdcdev.wdc_maxdrives = 2;
cmdsts = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG);
cmdsts &= ~PCI_COMMAND_INTERRUPT_DISABLE;
pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, cmdsts);
if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE &&
PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID)
sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID;
interface = PCI_INTERFACE(pa->pa_class);
wdc_allocate_regs(&sc->sc_wdcdev);
for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
channel++) {
cp = &sc->pciide_channels[channel];
if (pciide_chansetup(sc, channel, interface) == 0)
continue;
pciide_mapchan(pa, cp, interface, pciide_pci_intr);
}
}
static void
sis_sata_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa)
{
struct pciide_channel *cp;
pcireg_t interface = PCI_INTERFACE(pa->pa_class);
int channel;
if (pciide_chipen(sc, pa) == 0)
return;
if (interface == 0) {
ATADEBUG_PRINT(("sis_sata_chip_map interface == 0\n"),
DEBUG_PROBE);
interface = PCIIDE_INTERFACE_BUS_MASTER_DMA |
PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1);
}
aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev,
"Silicon Integrated Systems 180/96X SATA controller "
"(rev. 0x%02x)\n", PCI_REVISION(pa->pa_class));
aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev,
"bus-master DMA support present");
pciide_mapreg_dma(sc, pa);
aprint_verbose("\n");
if (sc->sc_dma_ok) {
sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA | ATAC_CAP_DMA;
sc->sc_wdcdev.irqack = pciide_irqack;
}
sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS;
sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel;
sc->sc_wdcdev.wdc_maxdrives = 2;
wdc_allocate_regs(&sc->sc_wdcdev);
for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
channel++) {
cp = &sc->pciide_channels[channel];
if (pciide_chansetup(sc, channel, interface) == 0)
continue;
pciide_mapchan(pa, cp, interface, pciide_pci_intr);
}
}
static void
piccolo_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa)
{
struct pciide_channel *cp;
pcireg_t interface;
int channel;
if (pciide_chipen(sc, pa) == 0)
return;
aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev,
"bus-master DMA support present");
pciide_mapreg_dma(sc, pa);
aprint_verbose("\n");
sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA32 | ATAC_CAP_DATA16;
sc->sc_wdcdev.sc_atac.atac_pio_cap = 5;
if (sc->sc_dma_ok) {
sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA;
sc->sc_wdcdev.irqack = pciide_irqack;
sc->sc_wdcdev.sc_atac.atac_dma_cap = 3;
sc->sc_wdcdev.sc_atac.atac_udma_cap = 2;
}
sc->sc_wdcdev.sc_atac.atac_set_modes = piccolo_setup_channel;
sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
sc->sc_wdcdev.sc_atac.atac_nchannels = 1;
sc->sc_wdcdev.wdc_maxdrives = 2;
/*
* XXX one for now. We'll figure out how to talk to the second channel
* later, hopefully! Second interface config is via the
* "alternate PCI Configuration Space" whatever that is!
*/
interface = PCI_INTERFACE(pa->pa_class);
wdc_allocate_regs(&sc->sc_wdcdev);
for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
channel++) {
cp = &sc->pciide_channels[channel];
if (pciide_chansetup(sc, channel, interface) == 0)
continue;
pciide_mapchan(pa, cp, interface, pciide_pci_intr);
}
}
/*
* This is called during pseudo-device attachment.
*/
void
md_attach_hook(int unit, struct md_conf *md)
{
char pbuf[9];
if (unit == 0 && md_is_root) {
/* Setup root ramdisk */
md->md_addr = (void *)md_root_image;
md->md_size = (size_t)md_root_size;
md->md_type = MD_KMEM_FIXED;
format_bytes(pbuf, sizeof(pbuf), md->md_size);
aprint_verbose("md%d: internal %s image area\n", unit, pbuf);
}
}
static void
upc1_attach(struct upc_softc *sc)
{
u_int8_t cr[16];
int i;
aprint_normal(": 82C710\n");
/* Dump configuration */
for (i = 0; i < 16; i++)
cr[i] = upc1_read_config(sc, i);
aprint_verbose_dev(&sc->sc_dev, "config state");
for (i = 0; i < 16; i++)
aprint_verbose(" %02x", cr[i]);
aprint_verbose("\n");
/* FDC */
if (cr[UPC1_CFGADDR_CRC] & UPC1_CRC_FDCEN)
upc_found(sc, "fdc", UPC_PORT_FDCBASE, 2, &sc->sc_fintr);
/* IDE */
if (cr[UPC1_CFGADDR_CRC] & UPC1_CRC_IDEEN)
upc_found2(sc, "wdc", UPC_PORT_IDECMDBASE, 8,
UPC_PORT_IDECTLBASE, 2, &sc->sc_wintr);
/* Parallel */
if (cr[UPC1_CFGADDR_CR0] & UPC1_CR0_PEN)
upc_found(sc, "lpt",
cr[UPC1_CFGADDR_PARBASE] << UPC1_PARBASE_SHIFT,
LPT_NPORTS, &sc->sc_pintr);
/* UART */
if (cr[UPC1_CFGADDR_CR0] & UPC1_CR0_SEN)
upc_found(sc, "com",
cr[UPC1_CFGADDR_UARTBASE] << UPC1_UARTBASE_SHIFT,
COM_NPORTS, &sc->sc_irq4);
/* Mouse */
/* XXX not yet supported */
}
/*
* Add wedges for a valid NetBSD disklabel.
*/
static void
addwedges(const mbr_args_t *a, const struct disklabel *lp)
{
int error, i;
for (i = 0; i < lp->d_npartitions; i++) {
struct dkwedge_info dkw;
const struct partition *p;
const char *ptype;
p = &lp->d_partitions[i];
if (p->p_fstype == FS_UNUSED)
continue;
if ((ptype = bsdlabel_fstype_to_str(p->p_fstype)) == NULL) {
/*
* XXX Should probably just add these...
* XXX maybe just have an empty ptype?
*/
aprint_verbose("%s: skipping partition %d, type %d\n",
a->pdk->dk_name, i, p->p_fstype);
continue;
}
strcpy(dkw.dkw_ptype, ptype);
strcpy(dkw.dkw_parent, a->pdk->dk_name);
dkw.dkw_offset = p->p_offset;
dkw.dkw_size = p->p_size;
/*
* These get historical disk naming style
* wedge names.
*/
snprintf((char *)&dkw.dkw_wname, sizeof(dkw.dkw_wname),
"%s%c", a->pdk->dk_name, 'a' + i);
error = dkwedge_add(&dkw);
if (error == EEXIST)
aprint_error("%s: wedge named '%s' already "
"exists, manual intervention required\n",
a->pdk->dk_name, dkw.dkw_wname);
else if (error)
aprint_error("%s: error %d adding partition "
"%d type %d\n", a->pdk->dk_name, error,
i, p->p_fstype);
}
}
static void
bthub_attach(device_t parent, device_t self, void *aux)
{
bdaddr_t *addr = aux;
prop_dictionary_t dict;
prop_object_t obj;
dict = device_properties(self);
obj = prop_data_create_data(addr, sizeof(*addr));
prop_dictionary_set(dict, BTDEVladdr, obj);
prop_object_release(obj);
aprint_verbose(" %s %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x",
BTDEVladdr,
addr->b[5], addr->b[4], addr->b[3],
addr->b[2], addr->b[1], addr->b[0]);
aprint_normal("\n");
pmf_device_register(self, NULL, NULL);
}
/* this could/should be mi_attach_cpu? */
void
rump_cpus_bootstrap(int *nump)
{
int num = *nump;
if (num > MAXCPUS) {
aprint_verbose("CPU limit: %d wanted, %d (MAXCPUS) "
"available (adjusted)\n", num, MAXCPUS);
num = MAXCPUS;
}
mutex_init(&cpu_lock, MUTEX_DEFAULT, IPL_NONE);
kcpuset_create(&kcpuset_attached, true);
kcpuset_create(&kcpuset_running, true);
/* attach first cpu for bootstrap */
rump_cpu_attach(&rump_bootcpu);
ncpu = 1;
*nump = num;
}
static void
fix_cardbus_bridge(int node, pci_chipset_tag_t pc, pcitag_t tag)
{
uint32_t bus_number = 0xffffffff;
pcireg_t bi;
int bus, dev, fn, ih, len;
char path[256];
#if PB3400_CARDBUS_HACK
int root_node;
root_node = OF_finddevice("/");
if (of_compatible(root_node, pb3400_compat) != -1) {
bus_number = cardbus_number;
cardbus_number++;
} else {
#endif
ih = OF_open(path);
OF_call_method("load-ata", ih, 0, 0);
OF_close(ih);
OF_getprop(node, "AAPL,bus-id", &bus_number,
sizeof(bus_number));
#if PB3400_CARDBUS_HACK
}
#endif
if (bus_number != 0xffffffff) {
len = OF_package_to_path(node, path, sizeof(path));
path[len] = 0;
aprint_verbose("\n%s: fixing bus number to %d", path, bus_number);
pci_decompose_tag(pc, tag, &bus, &dev, &fn);
bi = pci_conf_read(pc, tag, PPB_REG_BUSINFO);
bi &= 0xff000000;
/* XXX subordinate is always 32 here */
bi |= (bus & 0xff) | (bus_number << 8) | 0x200000;
pci_conf_write(pc, tag, PPB_REG_BUSINFO, bi);
}
}
static int
bthub_print(void *aux, const char *pnp)
{
prop_dictionary_t dict = aux;
prop_object_t obj;
const bdaddr_t *raddr;
if (pnp != NULL) {
obj = prop_dictionary_get(dict, BTDEVtype);
aprint_normal("%s: %s '%s',", pnp, BTDEVtype,
prop_string_cstring_nocopy(obj));
}
obj = prop_dictionary_get(dict, BTDEVraddr);
raddr = prop_data_data_nocopy(obj);
aprint_verbose(" %s %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x",
BTDEVraddr,
raddr->b[5], raddr->b[4], raddr->b[3],
raddr->b[2], raddr->b[1], raddr->b[0]);
return UNCONF;
}
static void
gcscide_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa)
{
pcireg_t interface;
bus_size_t cmdsize, ctlsize;
if (pciide_chipen(sc, pa) == 0)
return;
aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev,
"bus-master DMA support present");
pciide_mapreg_dma(sc, pa);
aprint_verbose("\n");
sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
if (sc->sc_dma_ok) {
sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA;
sc->sc_wdcdev.irqack = pciide_irqack;
}
sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
sc->sc_wdcdev.sc_atac.atac_udma_cap = 4;
sc->sc_wdcdev.sc_atac.atac_set_modes = gcscide_setup_channel;
sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
sc->sc_wdcdev.sc_atac.atac_nchannels = 1;
interface = PCI_INTERFACE(pa->pa_class);
wdc_allocate_regs(&sc->sc_wdcdev);
if (pciide_chansetup(sc, 0, interface) == 0)
return;
pciide_mapchan(pa, &sc->pciide_channels[0], interface,
&cmdsize, &ctlsize, pciide_pci_intr);
}
static void
stpc_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa)
{
struct pciide_channel *cp;
int channel;
pcireg_t interface = PCI_INTERFACE(pa->pa_class);
if (pciide_chipen(sc, pa) == 0)
return;
aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev,
"bus-master DMA support present");
pciide_mapreg_dma(sc, pa);
aprint_verbose("\n");
sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
if (sc->sc_dma_ok) {
sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA;
sc->sc_wdcdev.irqack = pciide_irqack;
}
sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
sc->sc_wdcdev.sc_atac.atac_udma_cap = 0;
sc->sc_wdcdev.sc_atac.atac_set_modes = stpc_setup_channel;
sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS;
sc->sc_wdcdev.wdc_maxdrives = 2;
wdc_allocate_regs(&sc->sc_wdcdev);
for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
channel++) {
cp = &sc->pciide_channels[channel];
if (pciide_chansetup(sc, channel, interface) == 0)
continue;
pciide_mapchan(pa, cp, interface, pciide_pci_intr);
}
}
int
prep_pci_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp)
{
struct genppc_pci_chipset_businfo *pbi;
prop_dictionary_t dict, devsub;
prop_object_t pinsub;
prop_number_t pbus;
int busno, bus, pin, line, swiz, dev, origdev, i;
char key[20];
pin = pa->pa_intrpin;
line = pa->pa_intrline;
bus = busno = pa->pa_bus;
swiz = pa->pa_intrswiz;
origdev = dev = pa->pa_device;
i = 0;
pbi = SIMPLEQ_FIRST(&genppc_pct->pc_pbi);
while (busno--)
pbi = SIMPLEQ_NEXT(pbi, next);
KASSERT(pbi != NULL);
dict = prop_dictionary_get(pbi->pbi_properties, "prep-pci-intrmap");
if (dict != NULL)
i = prop_dictionary_count(dict);
if (dict == NULL || i == 0) {
/* We have a non-PReP bus. now it gets hard */
pbus = prop_dictionary_get(pbi->pbi_properties,
"prep-pcibus-parent");
if (pbus == NULL)
goto bad;
busno = prop_number_integer_value(pbus);
pbus = prop_dictionary_get(pbi->pbi_properties,
"prep-pcibus-rawdevnum");
dev = prop_number_integer_value(pbus);
/* now that we know the parent bus, we need to find it's pbi */
pbi = SIMPLEQ_FIRST(&genppc_pct->pc_pbi);
while (busno--)
pbi = SIMPLEQ_NEXT(pbi, next);
KASSERT(pbi != NULL);
/* swizzle the pin */
pin = ((pin + origdev - 1) & 3) + 1;
/* now we have the pbi, ask for dict again */
dict = prop_dictionary_get(pbi->pbi_properties,
"prep-pci-intrmap");
if (dict == NULL)
goto bad;
}
/* No IRQ used. */
if (pin == 0)
goto bad;
if (pin > 4) {
aprint_error("pci_intr_map: bad interrupt pin %d\n", pin);
goto bad;
}
sprintf(key, "devfunc-%d", dev);
devsub = prop_dictionary_get(dict, key);
if (devsub == NULL)
goto bad;
sprintf(key, "pin-%c", 'A' + (pin-1));
pinsub = prop_dictionary_get(devsub, key);
if (pinsub == NULL)
goto bad;
line = prop_number_integer_value(pinsub);
/*
* Section 6.2.4, `Miscellaneous Functions', says that 255 means
* `unknown' or `no connection' on a PC. We assume that a device with
* `no connection' either doesn't have an interrupt (in which case the
* pin number should be 0, and would have been noticed above), or
* wasn't configured by the BIOS (in which case we punt, since there's
* no real way we can know how the interrupt lines are mapped in the
* hardware).
*
* XXX
* Since IRQ 0 is only used by the clock, and we can't actually be sure
* that the BIOS did its job, we also recognize that as meaning that
* the BIOS has not configured the device.
*/
if (line == 0 || line == 255) {
aprint_error("pci_intr_map: no mapping for pin %c\n",
'@' + pin);
goto bad;
} else {
if (line >= ICU_LEN) {
aprint_error("pci_intr_map: bad interrupt line %d\n",
line);
goto bad;
}
if (line == IRQ_SLAVE) {
aprint_verbose("pci_intr_map: changed line 2 to line 9\n");
line = 9;
}
}
*ihp = line;
return 0;
bad:
*ihp = -1;
return 1;
}
void
ums_attach(device_t parent, device_t self, void *aux)
{
struct ums_softc *sc = device_private(self);
struct uhidev_attach_arg *uha = aux;
struct wsmousedev_attach_args a;
int size;
void *desc;
uint32_t flags, quirks;
int i, hl;
struct hid_location *zloc;
bool isdigitizer;
aprint_naive("\n");
sc->sc_hdev.sc_dev = self;
sc->sc_hdev.sc_intr = ums_intr;
sc->sc_hdev.sc_parent = uha->parent;
sc->sc_hdev.sc_report_id = uha->reportid;
quirks = usbd_get_quirks(uha->parent->sc_udev)->uq_flags;
if (quirks & UQ_MS_REVZ)
sc->flags |= UMS_REVZ;
if (quirks & UQ_SPUR_BUT_UP)
sc->flags |= UMS_SPUR_BUT_UP;
uhidev_get_report_desc(uha->parent, &desc, &size);
isdigitizer = hid_is_collection(desc, size, uha->reportid,
HID_USAGE2(HUP_DIGITIZERS, 0x0002));
if (!pmf_device_register(self, NULL, NULL))
aprint_error_dev(self, "couldn't establish power handler\n");
if (!hid_locate(desc, size, HID_USAGE2(HUP_GENERIC_DESKTOP, HUG_X),
uha->reportid, hid_input, &sc->sc_loc_x, &flags)) {
aprint_error("\n%s: mouse has no X report\n",
device_xname(sc->sc_hdev.sc_dev));
return;
}
switch (flags & MOUSE_FLAGS_MASK) {
case 0:
sc->flags |= UMS_ABS;
break;
case HIO_RELATIVE:
break;
default:
aprint_error("\n%s: X report 0x%04x not supported\n",
device_xname(sc->sc_hdev.sc_dev), flags);
return;
}
if (!hid_locate(desc, size, HID_USAGE2(HUP_GENERIC_DESKTOP, HUG_Y),
uha->reportid, hid_input, &sc->sc_loc_y, &flags)) {
aprint_error("\n%s: mouse has no Y report\n",
device_xname(sc->sc_hdev.sc_dev));
return;
}
switch (flags & MOUSE_FLAGS_MASK) {
case 0:
sc->flags |= UMS_ABS;
break;
case HIO_RELATIVE:
break;
default:
aprint_error("\n%s: Y report 0x%04x not supported\n",
device_xname(sc->sc_hdev.sc_dev), flags);
return;
}
/* Try the wheel first as the Z activator since it's tradition. */
hl = hid_locate(desc,
size,
HID_USAGE2(HUP_GENERIC_DESKTOP, HUG_WHEEL),
uha->reportid,
hid_input,
&sc->sc_loc_z,
&flags);
zloc = &sc->sc_loc_z;
if (hl) {
if ((flags & MOUSE_FLAGS_MASK) != HIO_RELATIVE) {
aprint_verbose("\n%s: Wheel report 0x%04x not "
"supported\n", device_xname(sc->sc_hdev.sc_dev),
flags);
sc->sc_loc_z.size = 0; /* Bad Z coord, ignore it */
} else {
sc->flags |= UMS_Z;
/* Wheels need the Z axis reversed. */
sc->flags ^= UMS_REVZ;
/* Put Z on the W coordinate */
zloc = &sc->sc_loc_w;
}
}
hl = hid_locate(desc,
size,
HID_USAGE2(HUP_GENERIC_DESKTOP, HUG_Z),
uha->reportid,
hid_input,
zloc,
&flags);
/*
* The horizontal component of the scrollball can also be given by
* Application Control Pan in the Consumer page, so if we didnt see
* any Z then check that.
*/
if (!hl) {
hl = hid_locate(desc,
size,
HID_USAGE2(HUP_CONSUMER, HUC_AC_PAN),
uha->reportid,
hid_input,
zloc,
&flags);
}
if (hl) {
if ((flags & MOUSE_FLAGS_MASK) != HIO_RELATIVE) {
aprint_verbose("\n%s: Z report 0x%04x not supported\n",
device_xname(sc->sc_hdev.sc_dev), flags);
zloc->size = 0; /* Bad Z coord, ignore it */
} else {
if (sc->flags & UMS_Z)
sc->flags |= UMS_W;
else
sc->flags |= UMS_Z;
}
}
if (uha->uiaa->uiaa_vendor == USB_VENDOR_MICROSOFT) {
int fixpos;
/*
* The Microsoft Wireless Laser Mouse 6000 v2.0 and the
* Microsoft Comfort Mouse 2.0 report a bad position for
* the wheel and wheel tilt controls -- should be in bytes
* 3 & 4 of the report. Fix this if necessary.
*/
switch (uha->uiaa->uiaa_product) {
case USB_PRODUCT_MICROSOFT_24GHZ_XCVR10:
case USB_PRODUCT_MICROSOFT_24GHZ_XCVR20:
fixpos = 24;
break;
case USB_PRODUCT_MICROSOFT_CM6000:
fixpos = 40;
break;
default:
fixpos = 0;
break;
}
if (fixpos) {
if ((sc->flags & UMS_Z) && sc->sc_loc_z.pos == 0)
sc->sc_loc_z.pos = fixpos;
if ((sc->flags & UMS_W) && sc->sc_loc_w.pos == 0)
sc->sc_loc_w.pos = sc->sc_loc_z.pos + 8;
}
}
/* figure out the number of buttons */
for (i = 1; i <= MAX_BUTTONS; i++)
if (!hid_locate(desc, size, HID_USAGE2(HUP_BUTTON, i),
uha->reportid, hid_input, &sc->sc_loc_btn[i - 1], 0))
break;
if (isdigitizer) {
for (size_t j = 0; j < __arraycount(digbut); j++) {
if (hid_locate(desc, size, HID_USAGE2(HUP_DIGITIZERS,
digbut[j].feature), uha->reportid, hid_input,
&sc->sc_loc_btn[i - 1], 0)) {
if (i <= MAX_BUTTONS) {
i++;
sc->flags |= digbut[j].flag;
} else
aprint_error_dev(self,
"ran out of buttons\n");
}
}
}
sc->nbuttons = i - 1;
aprint_normal(": %d button%s%s%s%s%s%s%s%s%s\n",
sc->nbuttons, sc->nbuttons == 1 ? "" : "s",
sc->flags & UMS_W ? ", W" : "",
sc->flags & UMS_Z ? " and Z dir" : "",
sc->flags & UMS_W ? "s" : "",
isdigitizer ? " digitizer" : "",
sc->flags & UMS_TIP_SWITCH ? ", tip" : "",
sc->flags & UMS_SEC_TIP_SWITCH ? ", sec tip" : "",
sc->flags & UMS_BARREL_SWITCH ? ", barrel" : "",
sc->flags & UMS_ERASER ? ", eraser" : "");
#ifdef UMS_DEBUG
DPRINTF(("ums_attach: sc=%p\n", sc));
DPRINTF(("ums_attach: X\t%d/%d\n",
sc->sc_loc_x.pos, sc->sc_loc_x.size));
DPRINTF(("ums_attach: Y\t%d/%d\n",
sc->sc_loc_y.pos, sc->sc_loc_y.size));
if (sc->flags & UMS_Z)
DPRINTF(("ums_attach: Z\t%d/%d\n",
sc->sc_loc_z.pos, sc->sc_loc_z.size));
if (sc->flags & UMS_W)
DPRINTF(("ums_attach: W\t%d/%d\n",
sc->sc_loc_w.pos, sc->sc_loc_w.size));
for (i = 1; i <= sc->nbuttons; i++) {
DPRINTF(("ums_attach: B%d\t%d/%d\n",
i, sc->sc_loc_btn[i-1].pos,sc->sc_loc_btn[i-1].size));
}
#endif
a.accessops = &ums_accessops;
a.accesscookie = sc;
sc->sc_wsmousedev = config_found(self, &a, wsmousedevprint);
return;
}
static int
via_sata_chip_map_common(struct pciide_softc *sc,
const struct pci_attach_args *cpa)
{
pcireg_t csr;
int maptype, ret;
struct pci_attach_args pac, *pa = &pac;
pac = *cpa;
if (pciide_chipen(sc, pa) == 0)
return 0;
aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev,
"bus-master DMA support present");
pciide_mapreg_dma(sc, pa);
aprint_verbose("\n");
if (sc->sc_dma_ok) {
sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA | ATAC_CAP_DMA;
sc->sc_wdcdev.irqack = pciide_irqack;
}
sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS;
sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel;
sc->sc_wdcdev.wdc_maxdrives = 2;
if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE &&
PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID)
sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID;
wdc_allocate_regs(&sc->sc_wdcdev);
maptype = pci_mapreg_type(pa->pa_pc, pa->pa_tag,
PCI_MAPREG_START + 0x14);
switch(maptype) {
case PCI_MAPREG_TYPE_IO:
ret = pci_mapreg_map(pa, PCI_MAPREG_START + 0x14,
PCI_MAPREG_TYPE_IO, 0, &sc->sc_ba5_st, &sc->sc_ba5_sh,
NULL, &sc->sc_ba5_ss);
break;
case PCI_MAPREG_MEM_TYPE_32BIT:
/*
* Enable memory-space access if it isn't already there.
*/
csr = pci_conf_read(pa->pa_pc, pa->pa_tag,
PCI_COMMAND_STATUS_REG);
if ((csr & PCI_COMMAND_MEM_ENABLE) == 0 &&
(pa->pa_flags & PCI_FLAGS_MEM_OKAY) != 0) {
pci_conf_write(pa->pa_pc, pa->pa_tag,
PCI_COMMAND_STATUS_REG,
csr | PCI_COMMAND_MEM_ENABLE);
}
ret = pci_mapreg_map(pa, PCI_MAPREG_START + 0x14,
PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT,
0, &sc->sc_ba5_st, &sc->sc_ba5_sh,
NULL, &sc->sc_ba5_ss);
break;
default:
aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
"couldn't map sata regs, unsupported maptype (0x%x)\n",
maptype);
return 0;
}
if (ret != 0) {
aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
"couldn't map sata regs\n");
return 0;
}
return 1;
}
static void
via_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa)
{
struct pciide_channel *cp;
pcireg_t interface = PCI_INTERFACE(pa->pa_class);
pcireg_t vendor = PCI_VENDOR(pa->pa_id);
int channel;
u_int32_t ideconf;
pcireg_t pcib_id, pcib_class;
struct pci_attach_args pcib_pa;
if (pciide_chipen(sc, pa) == 0)
return;
switch (vendor) {
case PCI_VENDOR_VIATECH:
switch (PCI_PRODUCT(pa->pa_id)) {
case PCI_PRODUCT_VIATECH_VT6410_RAID:
aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev,
"VIA Technologies VT6410 IDE controller\n");
sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
interface = PCIIDE_INTERFACE_BUS_MASTER_DMA |
PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1);
break;
case PCI_PRODUCT_VIATECH_VX900_IDE:
aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev,
"VIA Technologies VX900 ATA133 controller\n");
sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
break;
default:
/*
* get a PCI tag for the ISA bridge.
*/
if (pci_find_device(&pcib_pa, via_pcib_match) == 0)
goto unknown;
pcib_id = pcib_pa.pa_id;
pcib_class = pcib_pa.pa_class;
aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev,
"VIA Technologies ");
switch (PCI_PRODUCT(pcib_id)) {
case PCI_PRODUCT_VIATECH_VT82C586_ISA:
aprint_normal("VT82C586 (Apollo VP) ");
if(PCI_REVISION(pcib_class) >= 0x02) {
aprint_normal("ATA33 controller\n");
sc->sc_wdcdev.sc_atac.atac_udma_cap = 2;
} else {
aprint_normal("controller\n");
sc->sc_wdcdev.sc_atac.atac_udma_cap = 0;
}
break;
case PCI_PRODUCT_VIATECH_VT82C596A:
aprint_normal("VT82C596A (Apollo Pro) ");
if (PCI_REVISION(pcib_class) >= 0x12) {
aprint_normal("ATA66 controller\n");
sc->sc_wdcdev.sc_atac.atac_udma_cap = 4;
} else {
aprint_normal("ATA33 controller\n");
sc->sc_wdcdev.sc_atac.atac_udma_cap = 2;
}
break;
case PCI_PRODUCT_VIATECH_VT82C686A_ISA:
aprint_normal("VT82C686A (Apollo KX133) ");
if (PCI_REVISION(pcib_class) >= 0x40) {
aprint_normal("ATA100 controller\n");
sc->sc_wdcdev.sc_atac.atac_udma_cap = 5;
} else {
aprint_normal("ATA66 controller\n");
sc->sc_wdcdev.sc_atac.atac_udma_cap = 4;
}
break;
case PCI_PRODUCT_VIATECH_VT8231:
aprint_normal("VT8231 ATA100 controller\n");
sc->sc_wdcdev.sc_atac.atac_udma_cap = 5;
break;
case PCI_PRODUCT_VIATECH_VT8233:
aprint_normal("VT8233 ATA100 controller\n");
sc->sc_wdcdev.sc_atac.atac_udma_cap = 5;
break;
case PCI_PRODUCT_VIATECH_VT8233A:
aprint_normal("VT8233A ATA133 controller\n");
sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
break;
case PCI_PRODUCT_VIATECH_VT8235:
aprint_normal("VT8235 ATA133 controller\n");
sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
break;
case PCI_PRODUCT_VIATECH_VT8237:
aprint_normal("VT8237 ATA133 controller\n");
sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
break;
case PCI_PRODUCT_VIATECH_VT8237A_ISA:
aprint_normal("VT8237A ATA133 controller\n");
sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
break;
case PCI_PRODUCT_VIATECH_CX700:
aprint_normal("CX700 ATA133 controller\n");
sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
break;
case PCI_PRODUCT_VIATECH_VT8251:
aprint_normal("VT8251 ATA133 controller\n");
sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
break;
default:
unknown:
aprint_normal("unknown VIA ATA controller\n");
sc->sc_wdcdev.sc_atac.atac_udma_cap = 0;
}
break;
}
sc->sc_apo_regbase = APO_VIA_REGBASE;
break;
case PCI_VENDOR_AMD:
switch (sc->sc_pp->ide_product) {
case PCI_PRODUCT_AMD_PBC8111_IDE:
sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
break;
case PCI_PRODUCT_AMD_CS5536_IDE:
case PCI_PRODUCT_AMD_PBC766_IDE:
case PCI_PRODUCT_AMD_PBC768_IDE:
sc->sc_wdcdev.sc_atac.atac_udma_cap = 5;
break;
default:
sc->sc_wdcdev.sc_atac.atac_udma_cap = 4;
}
sc->sc_apo_regbase = APO_AMD_REGBASE;
break;
case PCI_VENDOR_NVIDIA:
switch (sc->sc_pp->ide_product) {
case PCI_PRODUCT_NVIDIA_NFORCE_ATA100:
sc->sc_wdcdev.sc_atac.atac_udma_cap = 5;
break;
case PCI_PRODUCT_NVIDIA_NFORCE2_ATA133:
case PCI_PRODUCT_NVIDIA_NFORCE2_400_ATA133:
case PCI_PRODUCT_NVIDIA_NFORCE3_ATA133:
case PCI_PRODUCT_NVIDIA_NFORCE3_250_ATA133:
case PCI_PRODUCT_NVIDIA_NFORCE4_ATA133:
case PCI_PRODUCT_NVIDIA_NFORCE430_ATA133:
case PCI_PRODUCT_NVIDIA_MCP04_IDE:
case PCI_PRODUCT_NVIDIA_MCP55_IDE:
case PCI_PRODUCT_NVIDIA_MCP61_IDE:
case PCI_PRODUCT_NVIDIA_MCP65_IDE:
case PCI_PRODUCT_NVIDIA_MCP67_IDE:
case PCI_PRODUCT_NVIDIA_MCP73_IDE:
case PCI_PRODUCT_NVIDIA_MCP77_IDE:
sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
break;
}
sc->sc_apo_regbase = APO_NVIDIA_REGBASE;
break;
default:
panic("via_chip_map: unknown vendor");
}
aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev,
"bus-master DMA support present");
pciide_mapreg_dma(sc, pa);
aprint_verbose("\n");
sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
if (sc->sc_dma_ok) {
sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA;
sc->sc_wdcdev.irqack = pciide_irqack;
if (sc->sc_wdcdev.sc_atac.atac_udma_cap > 0)
sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA;
}
sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
sc->sc_wdcdev.sc_atac.atac_set_modes = via_setup_channel;
sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS;
sc->sc_wdcdev.wdc_maxdrives = 2;
if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE &&
PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID)
sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID;
wdc_allocate_regs(&sc->sc_wdcdev);
ATADEBUG_PRINT(("via_chip_map: old APO_IDECONF=0x%x, "
"APO_CTLMISC=0x%x, APO_DATATIM=0x%x, APO_UDMA=0x%x\n",
pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc)),
pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC(sc)),
pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)),
pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc))),
DEBUG_PROBE);
ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc));
for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
channel++) {
cp = &sc->pciide_channels[channel];
if (pciide_chansetup(sc, channel, interface) == 0)
continue;
if ((ideconf & APO_IDECONF_EN(channel)) == 0) {
aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev,
"%s channel ignored (disabled)\n", cp->name);
cp->ata_channel.ch_flags |= ATACH_DISABLED;
continue;
}
via_mapchan(pa, cp, interface, pciide_pci_intr);
}
}
static void
via_sata_chip_map_new(struct pciide_softc *sc,
const struct pci_attach_args *pa)
{
struct pciide_channel *cp;
struct ata_channel *wdc_cp;
struct wdc_regs *wdr;
int channel;
pci_intr_handle_t intrhandle;
const char *intrstr;
int i;
if (pciide_chipen(sc, pa) == 0)
return;
sc->sc_apo_regbase = APO_VIA_VT6421_REGBASE;
if (pci_mapreg_map(pa, PCI_BAR(5), PCI_MAPREG_TYPE_IO, 0,
&sc->sc_ba5_st, &sc->sc_ba5_sh, NULL, &sc->sc_ba5_ss) != 0) {
aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
"couldn't map SATA regs\n");
}
aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev,
"bus-master DMA support present");
via_vt6421_mapreg_dma(sc, pa);
aprint_verbose("\n");
sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
if (sc->sc_dma_ok) {
sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA;
sc->sc_wdcdev.irqack = pciide_irqack;
sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
}
sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel;
sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
sc->sc_wdcdev.sc_atac.atac_nchannels = 3;
sc->sc_wdcdev.wdc_maxdrives = 2;
wdc_allocate_regs(&sc->sc_wdcdev);
if (pci_intr_map(pa, &intrhandle) != 0) {
aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
"couldn't map native-PCI interrupt\n");
return;
}
intrstr = pci_intr_string(pa->pa_pc, intrhandle);
sc->sc_pci_ih = pci_intr_establish(pa->pa_pc,
intrhandle, IPL_BIO, pciide_pci_intr, sc);
if (sc->sc_pci_ih == NULL) {
aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
"couldn't establish native-PCI interrupt");
if (intrstr != NULL)
aprint_error(" at %s", intrstr);
aprint_error("\n");
return;
}
aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev,
"using %s for native-PCI interrupt\n",
intrstr ? intrstr : "unknown interrupt");
for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
channel++) {
cp = &sc->pciide_channels[channel];
if (via_vt6421_chansetup(sc, channel) == 0)
continue;
wdc_cp = &cp->ata_channel;
wdr = CHAN_TO_WDC_REGS(wdc_cp);
wdr->sata_iot = sc->sc_ba5_st;
wdr->sata_baseioh = sc->sc_ba5_sh;
if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh,
(wdc_cp->ch_channel << 6) + 0x0, 4,
&wdr->sata_status) != 0) {
aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
"couldn't map channel %d sata_status regs\n",
wdc_cp->ch_channel);
continue;
}
if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh,
(wdc_cp->ch_channel << 6) + 0x4, 4,
&wdr->sata_error) != 0) {
aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
"couldn't map channel %d sata_error regs\n",
wdc_cp->ch_channel);
continue;
}
if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh,
(wdc_cp->ch_channel << 6) + 0x8, 4,
&wdr->sata_control) != 0) {
aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
"couldn't map channel %d sata_control regs\n",
wdc_cp->ch_channel);
continue;
}
if (pci_mapreg_map(pa, PCI_BAR(wdc_cp->ch_channel),
PCI_MAPREG_TYPE_IO, 0, &wdr->cmd_iot, &wdr->cmd_baseioh,
NULL, &wdr->cmd_ios) != 0) {
aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
"couldn't map %s channel regs\n", cp->name);
}
wdr->ctl_iot = wdr->cmd_iot;
for (i = 0; i < WDC_NREG; i++) {
if (bus_space_subregion(wdr->cmd_iot,
wdr->cmd_baseioh, i, i == 0 ? 4 : 1,
&wdr->cmd_iohs[i]) != 0) {
aprint_error_dev(
sc->sc_wdcdev.sc_atac.atac_dev,
"couldn't subregion %s "
"channel cmd regs\n", cp->name);
return;
}
}
if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh,
WDC_NREG + 2, 1, &wdr->ctl_ioh) != 0) {
aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
"couldn't map channel %d ctl regs\n", channel);
return;
}
wdc_init_shadow_regs(wdc_cp);
wdr->data32iot = wdr->cmd_iot;
wdr->data32ioh = wdr->cmd_iohs[wd_data];
wdcattach(wdc_cp);
}
}
