static int ar7240sw_reset(struct ar7240sw *as) { struct mii_bus *mii = as->mii_bus; int ret; int i; /* Set all ports to disabled state. */ for (i = 0; i < AR7240_NUM_PORTS; i++) ar7240sw_disable_port(as, i); /* Wait for transmit queues to drain. */ msleep(2); /* Reset the switch. */ ar7240sw_reg_write(mii, AR7240_REG_MASK_CTRL, AR7240_MASK_CTRL_SOFT_RESET); ret = ar7240sw_reg_wait(mii, AR7240_REG_MASK_CTRL, AR7240_MASK_CTRL_SOFT_RESET, 0, 1000); /* setup PHYs */ for (i = 0; i < AR7240_NUM_PHYS; i++) { ar7240sw_phy_write(mii, i, MII_ADVERTISE, ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM); ar7240sw_phy_write(mii, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE); } msleep(1000); ar7240sw_setup(as); return ret; }
static int ag71xx_mdio_write(struct mii_bus *bus, int addr, int reg, u16 val) { struct ag71xx_mdio *am = bus->priv; if (am->pdata->is_ar7240) ar7240sw_phy_write(bus, addr, reg, val); else ag71xx_mdio_mii_write(am, addr, reg, val); return 0; }