void __init plat_mem_setup(void)
{
unsigned long io_base;
_machine_restart = ar7_machine_restart;
_machine_halt = ar7_machine_halt;
pm_power_off = ar7_machine_power_off;
panic_timeout = 3;
io_base = (unsigned long)ioremap(AR7_REGS_BASE, 0x10000);
if (!io_base) panic("Can't remap IO base!\n");
set_io_port_base(io_base);
prom_meminit();
ar7_init_clocks();
ioport_resource.start = 0;
ioport_resource.end = ~0;
iomem_resource.start = 0;
iomem_resource.end = ~0;
printk(KERN_INFO "%s, ID: 0x%04x, Revision: 0x%02x\n",
get_system_type(),
ar7_chip_id(), ar7_chip_rev());
}
void __init plat_time_init(void)
{
struct clk *cpu_clk;
/* Initialize ar7 clocks so the CPU clock frequency is correct */
ar7_init_clocks();
cpu_clk = clk_get(NULL, "cpu");
if (IS_ERR(cpu_clk)) {
printk(KERN_ERR "unable to get cpu clock\n");
return;
}
mips_hpt_frequency = clk_get_rate(cpu_clk) / 2;
}
