void arm_cpu_device::execute_set_input(int irqline, int state)
{
switch (irqline)
{
case ARM_IRQ_LINE: /* IRQ */
if (state && (R15&0x3)!=eARM_MODE_IRQ) /* Don't allow nested IRQs */
m_pendingIrq=1;
else
m_pendingIrq=0;
break;
case ARM_FIRQ_LINE: /* FIRQ */
if (state && (R15&0x3)!=eARM_MODE_FIQ) /* Don't allow nested FIRQs */
m_pendingFiq=1;
else
m_pendingFiq=0;
break;
}
arm_check_irq_state();
}
void arm_set_irq_line(int irqline, int state)
{
switch (irqline) {
case ARM_IRQ_LINE: /* IRQ */
if (state)
arm.pendingIrq=1;
else
arm.pendingIrq=0;
break;
case ARM_FIRQ_LINE: /* FIRQ */
if (state)
arm.pendingFiq=1;
else
arm.pendingFiq=0;
break;
}
arm_check_irq_state();
}
static void set_irq_line(ARM_REGS* cpustate, int irqline, int state)
{
switch (irqline) {
case ARM_IRQ_LINE: /* IRQ */
if (state && (R15&0x3)!=eARM_MODE_IRQ) /* Don't allow nested IRQs */
cpustate->pendingIrq=1;
else
cpustate->pendingIrq=0;
break;
case ARM_FIRQ_LINE: /* FIRQ */
if (state && (R15&0x3)!=eARM_MODE_FIQ) /* Don't allow nested FIRQs */
cpustate->pendingFiq=1;
else
cpustate->pendingFiq=0;
break;
}
arm_check_irq_state(cpustate);
}
void arm_set_irq_line(int irqline, int state)
{
switch (irqline) {
case ARM_IRQ_LINE: /* IRQ */
if (state && (R15&0x3)!=eARM_MODE_IRQ) /* Don't allow nested IRQs */
arm.pendingIrq=1;
else
arm.pendingIrq=0;
break;
case ARM_FIRQ_LINE: /* FIRQ */
if (state && (R15&0x3)!=eARM_MODE_FIQ) /* Don't allow nested FIRQs */
arm.pendingFiq=1;
else
arm.pendingFiq=0;
break;
}
arm_check_irq_state();
}
void arm_cpu_device::execute_run()
{
UINT32 pc;
UINT32 insn;
do
{
debugger_instruction_hook(this, R15 & ADDRESS_MASK);
/* load instruction */
pc = R15;
insn = m_direct->read_decrypted_dword( pc & ADDRESS_MASK );
switch (insn >> INSN_COND_SHIFT)
{
case COND_EQ:
if (Z_IS_CLEAR(pc)) goto L_Next;
break;
case COND_NE:
if (Z_IS_SET(pc)) goto L_Next;
break;
case COND_CS:
if (C_IS_CLEAR(pc)) goto L_Next;
break;
case COND_CC:
if (C_IS_SET(pc)) goto L_Next;
break;
case COND_MI:
if (N_IS_CLEAR(pc)) goto L_Next;
break;
case COND_PL:
if (N_IS_SET(pc)) goto L_Next;
break;
case COND_VS:
if (V_IS_CLEAR(pc)) goto L_Next;
break;
case COND_VC:
if (V_IS_SET(pc)) goto L_Next;
break;
case COND_HI:
if (C_IS_CLEAR(pc) || Z_IS_SET(pc)) goto L_Next;
break;
case COND_LS:
if (C_IS_SET(pc) && Z_IS_CLEAR(pc)) goto L_Next;
break;
case COND_GE:
if (!(pc & N_MASK) != !(pc & V_MASK)) goto L_Next; /* Use x ^ (x >> ...) method */
break;
case COND_LT:
if (!(pc & N_MASK) == !(pc & V_MASK)) goto L_Next;
break;
case COND_GT:
if (Z_IS_SET(pc) || (!(pc & N_MASK) != !(pc & V_MASK))) goto L_Next;
break;
case COND_LE:
if (Z_IS_CLEAR(pc) && (!(pc & N_MASK) == !(pc & V_MASK))) goto L_Next;
break;
case COND_NV:
goto L_Next;
}
/* Condition satisfied, so decode the instruction */
if ((insn & 0x0fc000f0u) == 0x00000090u) /* Multiplication */
{
HandleMul(insn);
R15 += 4;
}
else if (!(insn & 0x0c000000u)) /* Data processing */
{
HandleALU(insn);
}
else if ((insn & 0x0c000000u) == 0x04000000u) /* Single data access */
{
HandleMemSingle(insn);
R15 += 4;
}
else if ((insn & 0x0e000000u) == 0x08000000u ) /* Block data access */
{
HandleMemBlock(insn);
R15 += 4;
}
else if ((insn & 0x0e000000u) == 0x0a000000u) /* Branch */
{
HandleBranch(insn);
}
else if ((insn & 0x0f000000u) == 0x0e000000u) /* Coprocessor */
{
if (m_copro_type == ARM_COPRO_TYPE_VL86C020)
HandleCoProVL86C020(insn);
else
HandleCoPro(insn);
R15 += 4;
}
else if ((insn & 0x0f000000u) == 0x0f000000u) /* Software interrupt */
{
pc=R15+4;
R15 = eARM_MODE_SVC; /* Set SVC mode so PC is saved to correct R14 bank */
SetRegister( 14, pc ); /* save PC */
R15 = (pc&PSR_MASK)|(pc&IRQ_MASK)|0x8|eARM_MODE_SVC|I_MASK|(pc&MODE_MASK);
m_icount -= 2 * S_CYCLE + N_CYCLE;
}
else /* Undefined */
{
logerror("%08x: Undefined instruction\n",R15);
L_Next:
m_icount -= S_CYCLE;
R15 += 4;
}
arm_check_irq_state();
} while( m_icount > 0 );
} /* arm_execute */
static CPU_EXECUTE( arm )
{
UINT32 pc;
UINT32 insn;
ARM_REGS *cpustate = get_safe_token(device);
cpustate->icount = cycles;
do
{
debugger_instruction_hook(device, R15 & ADDRESS_MASK);
/* load instruction */
pc = R15;
insn = memory_decrypted_read_dword( cpustate->program, pc & ADDRESS_MASK );
switch (insn >> INSN_COND_SHIFT)
{
case COND_EQ:
if (Z_IS_CLEAR(pc)) goto L_Next;
break;
case COND_NE:
if (Z_IS_SET(pc)) goto L_Next;
break;
case COND_CS:
if (C_IS_CLEAR(pc)) goto L_Next;
break;
case COND_CC:
if (C_IS_SET(pc)) goto L_Next;
break;
case COND_MI:
if (N_IS_CLEAR(pc)) goto L_Next;
break;
case COND_PL:
if (N_IS_SET(pc)) goto L_Next;
break;
case COND_VS:
if (V_IS_CLEAR(pc)) goto L_Next;
break;
case COND_VC:
if (V_IS_SET(pc)) goto L_Next;
break;
case COND_HI:
if (C_IS_CLEAR(pc) || Z_IS_SET(pc)) goto L_Next;
break;
case COND_LS:
if (C_IS_SET(pc) && Z_IS_CLEAR(pc)) goto L_Next;
break;
case COND_GE:
if (!(pc & N_MASK) != !(pc & V_MASK)) goto L_Next; /* Use x ^ (x >> ...) method */
break;
case COND_LT:
if (!(pc & N_MASK) == !(pc & V_MASK)) goto L_Next;
break;
case COND_GT:
if (Z_IS_SET(pc) || (!(pc & N_MASK) != !(pc & V_MASK))) goto L_Next;
break;
case COND_LE:
if (Z_IS_CLEAR(pc) && (!(pc & N_MASK) == !(pc & V_MASK))) goto L_Next;
break;
case COND_NV:
goto L_Next;
}
/* Condition satisfied, so decode the instruction */
if ((insn & 0x0fc000f0u) == 0x00000090u) /* Multiplication */
{
HandleMul(cpustate, insn);
R15 += 4;
}
else if (!(insn & 0x0c000000u)) /* Data processing */
{
HandleALU(cpustate, insn);
}
else if ((insn & 0x0c000000u) == 0x04000000u) /* Single data access */
{
HandleMemSingle(cpustate, insn);
R15 += 4;
}
else if ((insn & 0x0e000000u) == 0x08000000u ) /* Block data access */
{
HandleMemBlock(cpustate, insn);
R15 += 4;
}
else if ((insn & 0x0e000000u) == 0x0a000000u) /* Branch */
{
HandleBranch(cpustate, insn);
}
else if ((insn & 0x0f000000u) == 0x0e000000u) /* Coprocessor */
{
HandleCoPro(cpustate, insn);
R15 += 4;
}
else if ((insn & 0x0f000000u) == 0x0f000000u) /* Software interrupt */
{
pc=R15+4;
R15 = eARM_MODE_SVC; /* Set SVC mode so PC is saved to correct R14 bank */
SetRegister( cpustate, 14, pc ); /* save PC */
R15 = (pc&PSR_MASK)|(pc&IRQ_MASK)|0x8|eARM_MODE_SVC|I_MASK|(pc&MODE_MASK);
cpustate->icount -= 2 * S_CYCLE + N_CYCLE;
}
else /* Undefined */
{
logerror("%08x: Undefined instruction\n",R15);
L_Next:
cpustate->icount -= S_CYCLE;
R15 += 4;
}
arm_check_irq_state(cpustate);
} while( cpustate->icount > 0 );
return cycles - cpustate->icount;
} /* arm_execute */
int ArmRun( int cycles )
{
UINT32 pc;
UINT32 insn;
arm_icount = cycles;
arm.ArmLeftCycles = cycles;
do
{
/* load instruction */
pc = R15;
insn = Arm_program_opcode_dword_32le( pc & ADDRESS_MASK );
switch (insn >> INSN_COND_SHIFT)
{
case COND_EQ:
if (Z_IS_CLEAR(pc)) goto L_Next;
break;
case COND_NE:
if (Z_IS_SET(pc)) goto L_Next;
break;
case COND_CS:
if (C_IS_CLEAR(pc)) goto L_Next;
break;
case COND_CC:
if (C_IS_SET(pc)) goto L_Next;
break;
case COND_MI:
if (N_IS_CLEAR(pc)) goto L_Next;
break;
case COND_PL:
if (N_IS_SET(pc)) goto L_Next;
break;
case COND_VS:
if (V_IS_CLEAR(pc)) goto L_Next;
break;
case COND_VC:
if (V_IS_SET(pc)) goto L_Next;
break;
case COND_HI:
if (C_IS_CLEAR(pc) || Z_IS_SET(pc)) goto L_Next;
break;
case COND_LS:
if (C_IS_SET(pc) && Z_IS_CLEAR(pc)) goto L_Next;
break;
case COND_GE:
if (!(pc & N_MASK) != !(pc & V_MASK)) goto L_Next; /* Use x ^ (x >> ...) method */
break;
case COND_LT:
if (!(pc & N_MASK) == !(pc & V_MASK)) goto L_Next;
break;
case COND_GT:
if (Z_IS_SET(pc) || (!(pc & N_MASK) != !(pc & V_MASK))) goto L_Next;
break;
case COND_LE:
if (Z_IS_CLEAR(pc) && (!(pc & N_MASK) == !(pc & V_MASK))) goto L_Next;
break;
case COND_NV:
goto L_Next;
}
/* Condition satisfied, so decode the instruction */
if ((insn & 0x0fc000f0u) == 0x00000090u) /* Multiplication */
{
HandleMul(insn);
R15 += 4;
}
else if (!(insn & 0x0c000000u)) /* Data processing */
{
HandleALU(insn);
}
else if ((insn & 0x0c000000u) == 0x04000000u) /* Single data access */
{
HandleMemSingle(insn);
R15 += 4;
}
else if ((insn & 0x0e000000u) == 0x08000000u ) /* Block data access */
{
HandleMemBlock(insn);
R15 += 4;
}
else if ((insn & 0x0e000000u) == 0x0a000000u) /* Branch */
{
HandleBranch(insn);
}
else if ((insn & 0x0f000000u) == 0x0e000000u) /* Coprocessor */
{
HandleCoPro(insn);
R15 += 4;
}
else if ((insn & 0x0f000000u) == 0x0f000000u) /* Software interrupt */
{
pc=R15+4;
R15 = eARM_MODE_SVC; /* Set SVC mode so PC is saved to correct R14 bank */
SetRegister( 14, pc ); /* save PC */
R15 = (pc&PSR_MASK)|(pc&IRQ_MASK)|0x8|eARM_MODE_SVC|I_MASK|(pc&MODE_MASK);
change_pc(pc&ADDRESS_MASK);
arm_icount -= 2 * S_CYCLE + N_CYCLE;
}
else /* Undefined */
{
L_Next:
arm_icount -= S_CYCLE;
R15 += 4;
}
arm_check_irq_state();
} while( arm_icount > 0 );
arm.ArmTotalCycles += (cycles - arm_icount);
return cycles - arm_icount;
} /* arm_execute */
