void arch_early_init(void) { arch_disable_ints(); #if (__CORTEX_M >= 0x03) || (CORTEX_SC >= 300) uint i; /* set the vector table base */ SCB->VTOR = (uint32_t)&vectab; #if ARM_CM_DYNAMIC_PRIORITY_SIZE /* number of priorities */ for (i=0; i < 7; i++) { __set_BASEPRI(1 << i); if (__get_BASEPRI() != 0) break; } arm_cm_num_irq_pri_bits = 8 - i; arm_cm_irq_pri_mask = ~((1 << i) - 1) & 0xff; #endif /* clear any pending interrupts and set all the vectors to medium priority */ uint groups = (SCnSCB->ICTR & 0xf) + 1; for (i = 0; i < groups; i++) { NVIC->ICER[i] = 0xffffffff; NVIC->ICPR[i] = 0xffffffff; for (uint j = 0; j < 32; j++) { NVIC_SetPriority(i*32 + j, arm_cm_medium_priority()); } } /* leave BASEPRI at 0 */ __set_BASEPRI(0); /* set priority grouping to 0 */ NVIC_SetPriorityGrouping(0); /* enable certain faults */ SCB->SHCSR |= (SCB_SHCSR_USGFAULTENA_Msk | SCB_SHCSR_BUSFAULTENA_Msk | SCB_SHCSR_MEMFAULTENA_Msk); /* set the svc and pendsv priority level to pretty low */ #endif NVIC_SetPriority(SVCall_IRQn, arm_cm_lowest_priority()); NVIC_SetPriority(PendSV_IRQn, arm_cm_lowest_priority()); /* set systick and debugmonitor to medium priority */ NVIC_SetPriority(SysTick_IRQn, arm_cm_medium_priority()); #if (__CORTEX_M >= 0x03) NVIC_SetPriority(DebugMonitor_IRQn, arm_cm_medium_priority()); #endif #if ARM_WITH_CACHE arch_enable_cache(UCACHE); #endif }
void arm_cm_systick_init(void) { NVIC_SetPriority(SysTick_IRQn, arm_cm_medium_priority()); }