static void sp804_write(void *opaque, target_phys_addr_t offset, uint32_t value) { sp804_state *s = (sp804_state *)opaque; if (offset < 0x20) { arm_timer_write(s->timer[0], offset, value); } else { arm_timer_write(s->timer[1], offset - 0x20, value); } }
static void sp804_write(void *opaque, target_phys_addr_t offset, uint64_t value, unsigned size) { sp804_state *s = (sp804_state *)opaque; if (offset < 0x20) { arm_timer_write(s->timer[0], offset, value); return; } if (offset < 0x40) { arm_timer_write(s->timer[1], offset - 0x20, value); return; } /* Technically we could be writing to the Test Registers, but not likely */ hw_error("%s: Bad offset %x\n", __func__, (int)offset); }
static void sp804_write(void *opaque, hwaddr offset, uint64_t value, unsigned size) { SP804State *s = (SP804State *)opaque; if (offset < 0x20) { arm_timer_write(s->timer[0], offset, value); return; } if (offset < 0x40) { arm_timer_write(s->timer[1], offset - 0x20, value); return; } /* Technically we could be writing to the Test Registers, but not likely */ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %x\n", __func__, (int)offset); }
static void icp_pit_write(void *opaque, target_phys_addr_t offset, uint32_t value) { icp_pit_state *s = (icp_pit_state *)opaque; int n; n = offset >> 8; if (n > 3) cpu_abort(cpu_single_env, "sp804_write: Bad timer %d\n", n); arm_timer_write(s->timer[n], offset & 0xff, value); }
static void icp_pit_write(void *opaque, target_phys_addr_t offset, uint64_t value, unsigned size) { icp_pit_state *s = (icp_pit_state *)opaque; int n; n = offset >> 8; if (n > 2) { hw_error("%s: Bad timer %d\n", __func__, n); } arm_timer_write(s->timer[n], offset & 0xff, value); }
static void icp_pit_write(void *opaque, target_phys_addr_t offset, uint32_t value) { icp_pit_state *s = (icp_pit_state *)opaque; int n; n = offset >> 8; if (n > 3) { hw_error("sp804_write: Bad timer %d\n", n); } arm_timer_write(s->timer[n], offset & 0xff, value); }
static void icp_pit_write(void *opaque, hwaddr offset, uint64_t value, unsigned size) { icp_pit_state *s = (icp_pit_state *)opaque; int n; n = offset >> 8; if (n > 2) { qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad timer %d\n", __func__, n); } arm_timer_write(s->timer[n], offset & 0xff, value); }