static void cpu_pci_domain_set_resources(device_t dev)
{
u32 pci_tolm = find_pci_tolm(dev->link_list);
unsigned long tomk = 0, tolmk;
int idx;
tomk = get_memory_size();
printk(BIOS_DEBUG, "Detected %lu Kbytes (%lu MiB) RAM.\n",
tomk, tomk / 1024);
/* Compute the top of Low memory */
tolmk = pci_tolm >> 10;
if (tolmk >= tomk) {
/* The PCI hole does not overlap the memory. */
tolmk = tomk;
}
/* Report the memory regions. */
idx = 10;
ram_resource(dev, idx++, 0, 640);
ram_resource(dev, idx++, 768, tolmk - 768);
set_top_of_ram(tomk * 1024);
assign_resources(dev->link_list);
}
static void pci_domain_set_resources(device_t dev)
{
device_t mc_dev;
uint32_t pci_tolm;
printk(BIOS_DEBUG, "Entered with dev vid = %x\n", dev->vendor);
printk(BIOS_DEBUG, "Entered with dev did = %x\n", dev->device);
pci_tolm = find_pci_tolm(dev->link_list);
mc_dev = dev->link_list->children->sibling;
printk(BIOS_DEBUG, "MC dev vendor = %x\n", mc_dev->vendor);
printk(BIOS_DEBUG, "MC dev device = %x\n", mc_dev->device);
if (mc_dev) {
/* Figure out which areas are/should be occupied by RAM.
* This is all computed in kilobytes and converted to/from
* the memory controller right at the edges.
* Having different variables in different units is
* too confusing to get right. Kilobytes are good up to
* 4 Terabytes of RAM...
*/
unsigned long tomk, tolmk;
int idx;
/* Get the value of the highest DRB. This tells the end of
* the physical memory. The units are ticks of 32MB
* i.e. 1 means 32MB.
*/
tomk = (unsigned long)pci_read_config8(mc_dev, 0x43);
tomk = tomk * 32 * 1024;
/* add vga_mem detection */
tomk = tomk - 16 * 1024;
/* Compute the top of Low memory */
tolmk = pci_tolm >> 10;
if (tolmk >= tomk) {
/* The PCI hole does not overlap memory
*/
tolmk = tomk;
}
/* Write the ram configuration registers,
* preserving the reserved bits.
*/
/* Report the memory regions */
printk(BIOS_DEBUG, "tomk = %ld\n", tomk);
printk(BIOS_DEBUG, "tolmk = %ld\n", tolmk);
idx = 10;
/* avoid pam region */
ram_resource(dev, idx++, 0, 640);
/* ram_resource(dev, idx++, 1024, tolmk - 1024); */
ram_resource(dev, idx++, 768, tolmk - 768);
/* Leave some space for ACPI, PIRQ and MP tables */
high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE;
high_tables_size = HIGH_MEMORY_SIZE;
}
assign_resources(dev->link_list);
}
static void pci_domain_set_resources(device_t dev)
{
device_t mc_dev;
int igd_memory = 0;
mc_dev = dev->link_list->children;
if (!mc_dev)
return;
unsigned long tomk, tomk_stolen;
int idx, drp_value;
u8 reg8;
reg8 = pci_read_config8(mc_dev, SMRAM);
reg8 &= 0xc0;
switch (reg8) {
case 0xc0:
igd_memory = 1024;
printk(BIOS_DEBUG, "%dKB IGD UMA\n", igd_memory);
break;
case 0x80:
igd_memory = 512;
printk(BIOS_DEBUG, "%dKB IGD UMA\n", igd_memory);
break;
default:
igd_memory = 0;
printk(BIOS_DEBUG, "No IGD UMA Memory\n");
break;
}
/* Get the value for DIMM 0 and translate it to MB. */
drp_value = pci_read_config8(mc_dev, DRP);
tomk = (unsigned long)(translate_i82810_to_mb[drp_value & 0x0f]);
/* Get the value for DIMM 1 and translate it to MB. */
drp_value = drp_value >> 4;
tomk += (unsigned long)(translate_i82810_to_mb[drp_value]);
/* Convert tomk from MB to KB. */
tomk = tomk << 10;
tomk_stolen = tomk - igd_memory;
/* For reserving UMA memory in the memory map */
uma_memory_base = tomk_stolen * 1024ULL;
uma_memory_size = igd_memory * 1024ULL;
printk(BIOS_DEBUG, "Available memory: %ldKB\n", tomk_stolen);
/* Report the memory regions. */
idx = 10;
ram_resource(dev, idx++, 0, 640);
ram_resource(dev, idx++, 768, tomk - 768);
uma_resource(dev, idx++, uma_memory_base >> 10, uma_memory_size >> 10);
set_top_of_ram(tomk_stolen * 1024);
assign_resources(dev->link_list);
}
static void pci_domain_set_resources(device_t dev)
{
static const uint8_t ramregs[] = {
0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f, 0x56, 0x57
};
device_t mc_dev;
uint32_t pci_tolm;
pci_tolm = find_pci_tolm(dev->link_list);
mc_dev = dev->link_list->children;
if (mc_dev) {
unsigned long tomk, tolmk;
unsigned char rambits;
int i, idx;
for(rambits = 0, i = 0; i < ARRAY_SIZE(ramregs); i++) {
unsigned char reg;
reg = pci_read_config8(mc_dev, ramregs[i]);
/* these are ENDING addresses, not sizes.
* if there is memory in this slot, then reg will be > rambits.
* So we just take the max, that gives us total.
* We take the highest one to cover for once and future coreboot
* bugs. We warn about bugs.
*/
if (reg > rambits)
rambits = reg;
if (reg < rambits)
printk(BIOS_ERR, "ERROR! register 0x%x is not set!\n",
ramregs[i]);
}
printk(BIOS_DEBUG, "I would set ram size to 0x%x Kbytes\n", (rambits)*8*1024);
tomk = rambits*8*1024;
/* Compute the top of Low memory */
tolmk = pci_tolm >> 10;
if (tolmk >= tomk) {
/* The PCI hole does does not overlap the memory.
*/
tolmk = tomk;
}
#if CONFIG_WRITE_HIGH_TABLES == 1
high_tables_base = (tolmk * 1024) - HIGH_MEMORY_SIZE;
high_tables_size = HIGH_MEMORY_SIZE;
printk(BIOS_DEBUG, "tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n",
tomk*1024, high_tables_base, high_tables_size);
#endif
/* Report the memory regions */
idx = 10;
ram_resource(dev, idx++, 0, tolmk);
}
assign_resources(dev->link_list);
}
static void pci_domain_set_resources(device_t dev)
{
device_t mc_dev;
u32 pci_tolm;
unsigned char reg;
unsigned long tomk, tolmk;
unsigned char rambits;
int idx;
pci_tolm = find_pci_tolm(dev->link_list);
mc_dev = dev_find_device(PCI_VENDOR_ID_VIA, 0x3324, 0);
rambits = pci_read_config8(mc_dev, 0x88);
rambits >>= 2;
/* Get memory size and frame buffer from northbridge's registers.
*
* If register contains an invalid value we set frame buffer size to a
* default of 32M, but that probably won't happen.
*/
reg = pci_read_config8(mc_dev, 0xa1);
reg &= 0x70;
reg = reg >> 4;
/* TOP 1M SMM Memory */
if (reg == 0x0 || reg == 0x6 || reg == 0x7)
tomk = (((rambits << 6) - 32 - 1) * 1024); // Set frame buffer 32M for default
else
tomk = (((rambits << 6) - (4 << reg) - 1) * 1024);
/* Compute the top of Low memory */
tolmk = pci_tolm >> 10;
if (tolmk >= tomk) {
/* The PCI hole does does not overlap the memory. */
tolmk = tomk;
tolmk -= 1024; // TOP 1M SM Memory
}
#if CONFIG_WRITE_HIGH_TABLES == 1
high_tables_base = (tolmk * 1024) - HIGH_MEMORY_SIZE;
high_tables_size = HIGH_MEMORY_SIZE;
printk(BIOS_DEBUG, "tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n",
tomk*1024, high_tables_base, high_tables_size);
#endif
/* Report the memory regions */
idx = 10;
/* TODO: Hole needed? Should this go elsewhere? */
ram_resource(dev, idx++, 0, 640); /* first 640k */
ram_resource(dev, idx++, 768, (tolmk - 768)); /* leave a hole for vga */
assign_resources(dev->link_list);
}
static void pci_domain_set_resources(device_t dev)
{
static const uint8_t ramregs[] = {0x5a, 0x5b, 0x5c, 0x5d };
device_t mc_dev;
uint32_t pci_tolm;
printk(BIOS_SPEW, "Entering vt8623 pci_domain_set_resources.\n");
pci_tolm = find_pci_tolm(dev->link_list);
mc_dev = dev->link_list->children;
if (mc_dev) {
unsigned long tomk, tolmk;
unsigned char rambits;
int i, idx;
for(rambits = 0, i = 0; i < ARRAY_SIZE(ramregs); i++) {
unsigned char reg;
reg = pci_read_config8(mc_dev, ramregs[i]);
/* these are ENDING addresses, not sizes.
* if there is memory in this slot, then reg will be > rambits.
* So we just take the max, that gives us total.
* We take the highest one to cover for once and future coreboot
* bugs. We warn about bugs.
*/
if (reg > rambits)
rambits = reg;
if (reg < rambits)
printk(BIOS_ERR, "ERROR! register 0x%x is not set!\n",
ramregs[i]);
}
printk(BIOS_DEBUG, "I would set ram size to 0x%x Kbytes\n", (rambits)*16*1024);
tomk = rambits*16*1024 - 32768;
/* Compute the top of Low memory */
tolmk = pci_tolm >> 10;
if (tolmk >= tomk) {
/* The PCI hole does does not overlap the memory.
*/
tolmk = tomk;
}
set_top_of_ram(tolmk * 1024);
/* Report the memory regions */
idx = 10;
ram_resource(dev, idx++, 0, 640); /* first 640k */
ram_resource(dev, idx++, 768, tolmk - 768); /* leave a hole for vga */
}
assign_resources(dev->link_list);
}
static void pci_domain_set_resources(device_t dev)
{
device_t mc_dev;
uint32_t pci_tolm;
printk(BIOS_SPEW, "%s\n", __func__);
pci_tolm = find_pci_tolm(dev->link_list);
mc_dev = dev->link_list->children;
if (mc_dev) {
unsigned long tomk, tolmk;
// unsigned char rambits;
// int i;
int idx;
#if 0
for(rambits = 0, i = 0; i < ARRAY_SIZE(ramregs); i++) {
unsigned char reg;
reg = pci_read_config8(mc_dev, ramregs[i]);
/* these are ENDING addresses, not sizes.
* if there is memory in this slot, then reg will be > rambits.
* So we just take the max, that gives us total.
* We take the highest one to cover for once and future coreboot
* bugs. We warn about bugs.
*/
if (reg > rambits)
rambits = reg;
if (reg < rambits)
printk(BIOS_ERR, "ERROR! register 0x%x is not set!\n",
ramregs[i]);
}
printk(BIOS_DEBUG, "I would set ram size to 0x%x Kbytes\n", (rambits)*8*1024);
tomk = rambits*8*1024;
#endif
tomk = 32 * 1024;
/* Compute the top of Low memory */
tolmk = pci_tolm >> 10;
if (tolmk >= tomk) {
/* The PCI hole does does not overlap the memory.
*/
tolmk = tomk;
}
/* Report the memory regions */
idx = 10;
ram_resource(dev, idx++, 0, tolmk);
}
assign_resources(dev->link_list);
}
int gameClient::build_board()
{
int resource = 0;
int dice = 0;
srand(time(0));
//must create tile, put it into pieces array, and update tile number in other array
for (int x = 0; x < active_num_tiles; x++)
{
resource = assign_resources();
if (resource == DESERT)
dice = 1;
else
dice = rolldice();
board[x].set_resource_type(resource);
board[x].set_dice_roll(dice);
}
return(1);
}
static void i440lx_domain_set_resources(device_t dev)
{
device_t mc_dev;
uint32_t pci_tolm;
pci_tolm = find_pci_tolm(dev->link_list);
mc_dev = dev->link_list->children;
if (mc_dev) {
unsigned long tomk, tolmk;
int idx;
/* Figure out which areas are/should be occupied by RAM. The
* value of the highest DRB denotes the end of the physical
* memory (in units of 8MB).
*/
tomk = ((unsigned long)pci_read_config8(mc_dev, DRB7));
/* Convert to KB. */
tomk *= (8 * 1024);
printk(BIOS_DEBUG, "Setting RAM size to %lu MB\n", tomk / 1024);
/* Compute the top of low memory. */
tolmk = pci_tolm / 1024;
if (tolmk >= tomk) {
/* The PCI hole does not overlap the memory. */
tolmk = tomk;
}
/* Report the memory regions. */
idx = 10;
ram_resource(dev, idx++, 0, 640);
ram_resource(dev, idx++, 768, tolmk - 768);
#if CONFIG_WRITE_HIGH_TABLES==1
/* Leave some space for ACPI, PIRQ and MP tables */
high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE;
high_tables_size = HIGH_MEMORY_SIZE;
#endif
}
assign_resources(dev->link_list);
}
static void i440bx_domain_set_resources(device_t dev)
{
device_t mc_dev;
uint32_t pci_tolm;
pci_tolm = find_pci_tolm(dev->link_list);
mc_dev = dev->link_list->children;
if (mc_dev) {
unsigned long tomk, tolmk;
int idx;
/* Figure out which areas are/should be occupied by RAM. The
* value of the highest DRB denotes the end of the physical
* memory (in units of 8MB).
*/
tomk = ((unsigned long)pci_read_config8(mc_dev, DRB7));
/* Convert to KB. */
tomk *= (8 * 1024);
printk(BIOS_DEBUG, "Setting RAM size to %ld MB\n", tomk / 1024);
/* Compute the top of low memory. */
tolmk = pci_tolm / 1024;
if (tolmk >= tomk) {
/* The PCI hole does not overlap the memory. */
tolmk = tomk;
}
/* Report the memory regions. */
idx = 10;
ram_resource(dev, idx++, 0, 640);
ram_resource(dev, idx++, 768, tolmk - 768);
set_top_of_ram(tomk * 1024);
}
assign_resources(dev->link_list);
}
static void pci_domain_set_resources(device_t dev)
{
assign_resources(dev->link_list);
}
/* Starts the auction main loop */
void start_auction_system(){
int tao_processes_msqid = msgget(IPC_PRIVATE, 0600 | IPC_CREAT);
tao* current_tao;
int taos_total_count = avail_resources->resources_count;
int created_taos = 0;
int terminated_taos = 0;
// int i = 1;
while(terminated_taos < taos_total_count){
if (created_taos < 3) {
/* Creates the firs three TAOs without waiting for any tao process message */
current_tao = get_tao(created_taos);
init_tao(current_tao);
notify_tao_creation(current_tao);
create_tao_process(current_tao->id, current_tao->lifetime, tao_processes_msqid);
created_taos++;
printf("[\x1b[34mAuction\x1b[0m] %-16s || Starting three seconds timer (tao id: %d)\n", current_tao->name, current_tao->id);
} else {
simple_message* msg = (simple_message*) malloc(sizeof(simple_message));
/* Waits for a message from the tao process */
if ( msgrcv(tao_processes_msqid, msg, sizeof(simple_message) - sizeof(long), SIMPLE_MESSAGE_MTYPE, 0) != -1 ) {
if ( strcmp(msg->msg, TAO_PROCESS_END_MSG) == 0 ){
/* The TAO must be ended */
int p_status;
/* Avoids zombie creation */
waitpid(msg->pid, &p_status, WUNTRACED);
current_tao = get_tao_by_id(msg->content.i);
notify_tao_end(current_tao);
assign_resources(current_tao);
terminated_taos++;
printf("[\x1b[34mAuction\x1b[0m] %-16s || Ended auction (tao id: %d)\n", current_tao->name, current_tao->id);
/* Deallocates shared memory and semaphore */
semctl(current_tao->sem_id, 0, IPC_RMID, 0);
shmctl(current_tao->shm_id, IPC_RMID, 0);
/* Creates a new TAO, if there is any left */
if (created_taos < taos_total_count){
current_tao = get_tao(created_taos);
init_tao(current_tao);
notify_tao_creation(current_tao);
create_tao_process(current_tao->id, current_tao->lifetime, tao_processes_msqid);
created_taos++;
printf("[\x1b[34mAuction\x1b[0m] %-16s || Starting three seconds timer (tao id: %d)\n", current_tao->name, current_tao->id);
}
} else if ( strcmp(msg->msg, TAO_PROCESS_END_THREESEC) == 0 ){
/* The three seconds timer has ticked, so the TAO must start */
current_tao = get_tao(msg->content.i);
start_tao(current_tao);
notify_tao_start(current_tao);
printf("[\x1b[34mAuction\x1b[0m] %-16s || Started auction (tao id: %d)\n", current_tao->name, current_tao->id);
}
}
free(msg);
}
}
/* Removes the TAOS creation semaphore */
semctl(semid, 0, IPC_RMID, 0);
/* Close message queue */
msgctl(tao_processes_msqid, IPC_RMID,0);
free(avail_resources);
canexit == 1;
}
/**
* Configure devices on the devices tree.
*
* Starting at the root of the device tree, travel it recursively in two
* passes. In the first pass, we compute and allocate resources (ranges)
* requried by each device. In the second pass, the resources ranges are
* relocated to their final position and stored to the hardware.
*
* I/O resources grow upward. MEM resources grow downward.
*
* Since the assignment is hierarchical we set the values into the dev_root
* struct.
*/
void dev_configure(void)
{
struct resource *res;
struct device *root;
struct device *child;
set_vga_bridge_bits();
printk(BIOS_INFO, "Allocating resources...\n");
root = &dev_root;
/*
* Each domain should create resources which contain the entire address
* space for IO, MEM, and PREFMEM resources in the domain. The
* allocation of device resources will be done from this address space.
*/
/* Read the resources for the entire tree. */
printk(BIOS_INFO, "Reading resources...\n");
read_resources(root->link_list);
printk(BIOS_INFO, "Done reading resources.\n");
print_resource_tree(root, BIOS_SPEW, "After reading.");
/* Compute resources for all domains. */
for (child = root->link_list->children; child; child = child->sibling) {
if (!(child->path.type == DEVICE_PATH_DOMAIN))
continue;
for (res = child->resource_list; res; res = res->next) {
if (res->flags & IORESOURCE_FIXED)
continue;
if (res->flags & IORESOURCE_PREFETCH) {
compute_resources(child->link_list,
res, MEM_MASK, PREF_TYPE);
continue;
}
if (res->flags & IORESOURCE_MEM) {
compute_resources(child->link_list,
res, MEM_MASK, MEM_TYPE);
continue;
}
if (res->flags & IORESOURCE_IO) {
compute_resources(child->link_list,
res, IO_MASK, IO_TYPE);
continue;
}
}
}
/* For all domains. */
for (child = root->link_list->children; child; child=child->sibling)
if (child->path.type == DEVICE_PATH_DOMAIN)
avoid_fixed_resources(child);
/*
* Now we need to adjust the resources. MEM resources need to start at
* the highest address managable.
*/
for (child = root->link_list->children; child; child = child->sibling) {
if (child->path.type != DEVICE_PATH_DOMAIN)
continue;
for (res = child->resource_list; res; res = res->next) {
if (!(res->flags & IORESOURCE_MEM) ||
res->flags & IORESOURCE_FIXED)
continue;
res->base = resource_max(res);
}
}
/* Store the computed resource allocations into device registers ... */
printk(BIOS_INFO, "Setting resources...\n");
for (child = root->link_list->children; child; child = child->sibling) {
if (!(child->path.type == DEVICE_PATH_DOMAIN))
continue;
for (res = child->resource_list; res; res = res->next) {
if (res->flags & IORESOURCE_FIXED)
continue;
if (res->flags & IORESOURCE_PREFETCH) {
allocate_resources(child->link_list,
res, MEM_MASK, PREF_TYPE);
continue;
}
if (res->flags & IORESOURCE_MEM) {
allocate_resources(child->link_list,
res, MEM_MASK, MEM_TYPE);
continue;
}
if (res->flags & IORESOURCE_IO) {
allocate_resources(child->link_list,
res, IO_MASK, IO_TYPE);
continue;
}
}
}
assign_resources(root->link_list);
printk(BIOS_INFO, "Done setting resources.\n");
print_resource_tree(root, BIOS_SPEW, "After assigning values.");
printk(BIOS_INFO, "Done allocating resources.\n");
}
static void pci_domain_set_resources(device_t dev)
{
printk(BIOS_SPEW, "%s/%s ( %s )\n",
__FILE__, __func__, dev_name(dev));
assign_resources(dev->link_list);
}
static void cpu_pci_domain_set_resources(struct device *dev)
{
assign_resources(dev->link_list);
}
static void pci_domain_set_resources(device_t dev)
{
/*
* the order is important to find the correct RAM size.
*/
u8 ramregs[] = { 0x43, 0x42, 0x41, 0x40 };
device_t mc_dev;
u32 pci_tolm;
u8 reg;
printk(BIOS_SPEW, "Entering vx800 pci_domain_set_resources.\n");
pci_tolm = find_pci_tolm(dev->link_list);
mc_dev = dev_find_device(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_VX855_MEMCTRL, 0);
if (mc_dev) {
unsigned long tomk, tolmk;
unsigned char rambits;
u8 i, idx;
/*
* once the register value is not zero, the ramsize is
* this register's value multiply 64 * 1024 * 1024
*/
for (rambits = 0, i = 0; i < ARRAY_SIZE(ramregs); i++) {
rambits = pci_read_config8(mc_dev, ramregs[i]);
if (rambits != 0)
break;
}
/*
Get memory size and frame buffer from northbridge's registers.
if register with invalid value we set frame buffer size to 32M for default, but it won't happen.
*/
reg = pci_read_config8(mc_dev, 0xa1);
reg &= 0x70;
reg = reg >> 4;
/* TOP 1M SM Memory */
if (reg == 0x0)
tomk = (((rambits << 6) - 32 - VIACONFIG_TOP_SM_SIZE_MB) * 1024); // Set frame buffer 32M for default
else
tomk =
(((rambits << 6) - (4 << reg) -
VIACONFIG_TOP_SM_SIZE_MB) * 1024);
printk(BIOS_SPEW, "tomk is 0x%lx\n", tomk);
/* Compute the Top Of Low Memory, in Kb */
tolmk = pci_tolm >> 10;
if (tolmk >= tomk) {
/* The PCI hole does does not overlap the memory. */
tolmk = tomk;
}
/* Report the memory regions */
idx = 10;
/* TODO: Hole needed? */
ram_resource(dev, idx++, 0, 640); /* first 640k */
/* Leave a hole for vga, 0xa0000 - 0xc0000 */
ram_resource(dev, idx++, 768, (tolmk - 768));
}
assign_resources(dev->link_list);
}
