long board_init(void) { /* * Since the USART supports RS-485 multidrop mode, it allows the * TX pins to float. However, for RS-232 operations, we don't want * these pins to float. Instead, they should be pulled up to avoid * mismatches. Linux does something similar when it configures the * TX lines. This implies that we also allow the RX lines to float * rather than be in the state they are left in by the boot loader. * Since they are input pins, I think that this is the right thing * to do. */ /* PIOA's A periph: Turn USART 0 and 2's TX/RX pins */ at91_pio_use_periph_a(AT91RM92_PIOA_BASE, AT91C_PA18_RXD0 | AT91C_PA22_RXD2, 0); at91_pio_use_periph_a(AT91RM92_PIOA_BASE, AT91C_PA17_TXD0 | AT91C_PA23_TXD2, 1); /* PIOA's B periph: Turn USART 3's TX/RX pins */ at91_pio_use_periph_b(AT91RM92_PIOA_BASE, AT91C_PA6_RXD3, 0); at91_pio_use_periph_b(AT91RM92_PIOA_BASE, AT91C_PA5_TXD3, 1); /* PIOB's A periph: Turn USART 1's TX/RX pins */ at91_pio_use_periph_a(AT91RM92_PIOB_BASE, AT91C_PB21_RXD1, 0); at91_pio_use_periph_a(AT91RM92_PIOB_BASE, AT91C_PB20_TXD1, 1); return (at91_ramsize()); }
BOARD_INIT long board_init(void) { /* PIOB's A periph: Turn the debug USART's TX/RX pins */ at91_pio_use_periph_a(AT91SAM9G45_PIOB_BASE, AT91C_PB12_DRXD, 0); at91_pio_use_periph_a(AT91SAM9G45_PIOB_BASE, AT91C_PB13_DTXD, 1); return (at91_ramsize()); }
static void bi_dbgu(void) { /* * DBGU */ /* DRXD */ at91_pio_use_periph_a(AT91SAM9260_PIOB_BASE, AT91C_PIO_PB14, 0); /* DTXD */ at91_pio_use_periph_a(AT91SAM9260_PIOB_BASE, AT91C_PIO_PB15, 1); }
void at91rm9200_config_mci(int has_4wire) { /* XXX TODO chip changed GPIO, other slots, etc */ at91_pio_use_periph_a(AT91RM92_PIOA_BASE, AT91C_PIO_PA27, 0); /* MCCK */ at91_pio_use_periph_a(AT91RM92_PIOA_BASE, AT91C_PIO_PA28, 1); /* MCCDA */ at91_pio_use_periph_a(AT91RM92_PIOA_BASE, AT91C_PIO_PA29, 1); /* MCDA0 */ if (has_4wire) { at91_pio_use_periph_b(AT91RM92_PIOB_BASE, AT91C_PIO_PB3, 1); /* MCDA1 */ at91_pio_use_periph_b(AT91RM92_PIOB_BASE, AT91C_PIO_PB4, 1); /* MCDA2 */ at91_pio_use_periph_b(AT91RM92_PIOB_BASE, AT91C_PIO_PB5, 1); /* MCDA3 */ } }
static void bi_iic(void) { /* * TWI. Only one child on the iic bus, which we take care of * via hints. */ /* TWD */ at91_pio_use_periph_a(AT91SAM9260_PIOA_BASE, AT91C_PIO_PA23, 1); /* TWCK */ at91_pio_use_periph_a(AT91SAM9260_PIOA_BASE, AT91C_PIO_PA24, 1); }
static void bi_usart1(void) { /* * USART1 */ /* RTS1 */ at91_pio_use_periph_a(AT91SAM9260_PIOB_BASE, AT91C_PIO_PB28, 1); /* CTS1 */ at91_pio_use_periph_a(AT91SAM9260_PIOB_BASE, AT91C_PIO_PB29, 0); /* TXD1 */ at91_pio_use_periph_a(AT91SAM9260_PIOB_BASE, AT91C_PIO_PB6, 1); /* RXD1 */ at91_pio_use_periph_a(AT91SAM9260_PIOB_BASE, AT91C_PIO_PB7, 0); }
static int at91_usart_requires_rts0_workaround(struct uart_softc *sc) { int value; int unit; unit = device_get_unit(sc->sc_dev); /* * On the rm9200 chips, the PA21/RTS0 pin is not correctly wired to the * usart device interally (so-called 'erratum 39', but it's 41.14 in rev * I of the manual). This prevents use of the hardware flow control * feature in the usart itself. It also means that if we are to * implement RTS/CTS flow via the tty layer logic, we must use pin PA21 * as a gpio and manually manipulate it in at91_usart_bus_setsig(). We * can only safely do so if we've been given permission via a hint, * otherwise we might manipulate a pin that's attached to who-knows-what * and Bad Things could happen. */ if (at91_is_rm92() && unit == 1) { value = 0; resource_int_value(device_get_name(sc->sc_dev), unit, "use_rts0_workaround", &value); if (value != 0) { at91_pio_use_gpio(AT91RM92_PIOA_BASE, AT91C_PIO_PA21); at91_pio_gpio_output(AT91RM92_PIOA_BASE, AT91C_PIO_PA21, 1); at91_pio_use_periph_a(AT91RM92_PIOA_BASE, AT91C_PIO_PA20, 0); return (1); } } return (0); }
static void bi_mmc(void) { /* * MMC, wired to socket B. */ /* MCDB0 */ at91_pio_use_periph_b(AT91SAM9260_PIOA_BASE, AT91C_PIO_PA0, 1); /* MCCDB */ at91_pio_use_periph_b(AT91SAM9260_PIOA_BASE, AT91C_PIO_PA1, 1); /* MCDB3 */ at91_pio_use_periph_b(AT91SAM9260_PIOA_BASE, AT91C_PIO_PA3, 1); /* MCDB2 */ at91_pio_use_periph_b(AT91SAM9260_PIOA_BASE, AT91C_PIO_PA4, 1); /* MCDB1 */ at91_pio_use_periph_b(AT91SAM9260_PIOA_BASE, AT91C_PIO_PA5, 1); /* MCCK */ at91_pio_use_periph_a(AT91SAM9260_PIOA_BASE, AT91C_PIO_PA8, 1); /* * SPI0 and MMC are wired together, since we don't support sharing * don't support the dataflash. But if you did, you'd have to * use CS0 and CS1. */ }
/* * TSC-specific code to read the ID eeprom on the mainboard and extract the * unit's EUI-64 which gets translated into a MAC-48 for ethernet. */ static void eeprom_init(void) { const uint32_t twiHz = 400000; const uint32_t twiCkDiv = 1 << 16; const uint32_t twiChDiv = ((at91_master_clock / twiHz) - 2) << 8; const uint32_t twiClDiv = ((at91_master_clock / twiHz) - 2); /* * Set the TWCK and TWD lines for Periph A, no pullup, open-drain. */ at91_pio_use_periph_a(AT91RM92_PIOA_BASE, AT91C_PIO_PA25 | AT91C_PIO_PA26, 0); at91_pio_gpio_high_z(AT91RM92_PIOA_BASE, AT91C_PIO_PA25, 1); /* * Enable TWI power (irq numbers are also device IDs for power) */ WR4HW(AT91RM92_PMC_BASE, PMC_PCER, 1u << AT91RM92_IRQ_TWI); /* * Disable TWI interrupts, reset device, enable Master mode, * disable Slave mode, set the clock. */ WR4HW(AT91RM92_TWI_BASE, TWI_IDR, 0xffffffff); WR4HW(AT91RM92_TWI_BASE, TWI_CR, TWI_CR_SWRST); WR4HW(AT91RM92_TWI_BASE, TWI_CR, TWI_CR_MSEN | TWI_CR_SVDIS); WR4HW(AT91RM92_TWI_BASE, TWI_CWGR, twiCkDiv | twiChDiv | twiClDiv); }
static void bi_emac(void) { /* * EMAC */ /* ETX0 */ at91_pio_use_periph_a(AT91SAM9260_PIOA_BASE, AT91C_PIO_PA12, 0); /* ETX1 */ at91_pio_use_periph_a(AT91SAM9260_PIOA_BASE, AT91C_PIO_PA13, 0); /* ERX0 */ at91_pio_use_periph_a(AT91SAM9260_PIOA_BASE, AT91C_PIO_PA14, 0); /* ERX1 */ at91_pio_use_periph_a(AT91SAM9260_PIOA_BASE, AT91C_PIO_PA15, 0); /* ETXEN */ at91_pio_use_periph_a(AT91SAM9260_PIOA_BASE, AT91C_PIO_PA16, 0); /* ERXDV */ at91_pio_use_periph_a(AT91SAM9260_PIOA_BASE, AT91C_PIO_PA17, 0); /* ERXER */ at91_pio_use_periph_a(AT91SAM9260_PIOA_BASE, AT91C_PIO_PA18, 0); /* ETXCK */ at91_pio_use_periph_a(AT91SAM9260_PIOA_BASE, AT91C_PIO_PA19, 0); /* EMDC */ at91_pio_use_periph_a(AT91SAM9260_PIOA_BASE, AT91C_PIO_PA20, 0); /* EMDIO */ at91_pio_use_periph_a(AT91SAM9260_PIOA_BASE, AT91C_PIO_PA21, 0); /* Not RMII */ /* ETX2 */ at91_pio_use_periph_b(AT91SAM9260_PIOA_BASE, AT91C_PIO_PA10, 0); /* ETX3 */ at91_pio_use_periph_b(AT91SAM9260_PIOA_BASE, AT91C_PIO_PA11, 0); /* ETXER */ at91_pio_use_periph_b(AT91SAM9260_PIOA_BASE, AT91C_PIO_PA22, 0); /* ERX2 */ at91_pio_use_periph_b(AT91SAM9260_PIOA_BASE, AT91C_PIO_PA25, 0); /* ERX3 */ at91_pio_use_periph_b(AT91SAM9260_PIOA_BASE, AT91C_PIO_PA26, 0); /* ERXCK */ at91_pio_use_periph_b(AT91SAM9260_PIOA_BASE, AT91C_PIO_PA27, 0); /* ECRS */ at91_pio_use_periph_b(AT91SAM9260_PIOA_BASE, AT91C_PIO_PA28, 0); /* ECOL */ at91_pio_use_periph_b(AT91SAM9260_PIOA_BASE, AT91C_PIO_PA29, 0); }
static int pinctrl_configure_pins(device_t bus, phandle_t cfgxref) { struct pinctrl_softc *sc; struct pincfg *cfg, *cfgdata; char name[32]; phandle_t node; ssize_t npins; int i; sc = device_get_softc(bus); node = OF_node_from_xref(cfgxref); memset(name, 0, sizeof(name)); OF_getprop(node, "name", name, sizeof(name)); npins = OF_getencprop_alloc(node, "atmel,pins", sizeof(*cfgdata), (void **)&cfgdata); if (npins < 0) { printf("We're doing it wrong %s\n", name); return (ENXIO); } if (npins == 0) return (0); for (i = 0, cfg = cfgdata; i < npins; i++, cfg++) { uint32_t pio; pio = (0xfffffff & sc->ranges[0].bus) + 0x200 * cfg->unit; printf("P%c%d %s %#x\n", cfg->unit + 'A', cfg->pin, periphs[cfg->periph], cfg->flags); switch (cfg->periph) { case 0: at91_pio_use_gpio(pio, 1u << cfg->pin); at91_pio_gpio_pullup(pio, 1u << cfg->pin, !!(cfg->flags & 1)); at91_pio_gpio_high_z(pio, 1u << cfg->pin, !!(cfg->flags & 2)); at91_pio_gpio_set_deglitch(pio, 1u << cfg->pin, !!(cfg->flags & 4)); // at91_pio_gpio_pulldown(pio, 1u << cfg->pin, // !!(cfg->flags & 8)); // at91_pio_gpio_dis_schmidt(pio, // 1u << cfg->pin, !!(cfg->flags & 16)); break; case 1: at91_pio_use_periph_a(pio, 1u << cfg->pin, cfg->flags); break; case 2: at91_pio_use_periph_b(pio, 1u << cfg->pin, cfg->flags); break; } } OF_prop_free(cfgdata); return (0); }
static void bi_usart0(void) { /* * USART0 */ /* TXD0 */ at91_pio_use_periph_a(AT91SAM9260_PIOB_BASE, AT91C_PIO_PB4, 1); /* RXD0 */ at91_pio_use_periph_a(AT91SAM9260_PIOB_BASE, AT91C_PIO_PB5, 0); /* DSR0 */ at91_pio_use_periph_a(AT91SAM9260_PIOB_BASE, AT91C_PIO_PB22, 0); /* DCD0 */ at91_pio_use_periph_a(AT91SAM9260_PIOB_BASE, AT91C_PIO_PB23, 0); /* DTR0 */ at91_pio_use_periph_a(AT91SAM9260_PIOB_BASE, AT91C_PIO_PB24, 1); /* RI0 */ at91_pio_use_periph_a(AT91SAM9260_PIOB_BASE, AT91C_PIO_PB25, 0); /* RTS0 */ at91_pio_use_periph_a(AT91SAM9260_PIOB_BASE, AT91C_PIO_PB26, 1); /* CTS0 */ at91_pio_use_periph_a(AT91SAM9260_PIOB_BASE, AT91C_PIO_PB27, 0); }
BOARD_INIT long board_init(void) { #if 0 /* PIOB's A periph: Turn USART 0's TX/RX pins */ at91_pio_use_periph_a(AT91SAM9G20_PIOB_BASE, AT91C_PB14_DRXD, 0); at91_pio_use_periph_a(AT91SAM9G20_PIOB_BASE, AT91C_PB15_DTXD, 1); /* PIOB's A periph: Turn USART 0's TX/RX pins */ at91_pio_use_periph_a(AT91SAM9G20_PIOB_BASE, AT91C_PB4_TXD0, 1); at91_pio_use_periph_a(AT91SAM9G20_PIOB_BASE, AT91C_PB5_RXD0, 0); at91_pio_use_periph_a(AT91SAM9G20_PIOB_BASE, AT91C_PB22_DSR0, 0); at91_pio_use_periph_a(AT91SAM9G20_PIOB_BASE, AT91C_PB23_DCD0, 0); at91_pio_use_periph_a(AT91SAM9G20_PIOB_BASE, AT91C_PB24_DTR0, 1); at91_pio_use_periph_a(AT91SAM9G20_PIOB_BASE, AT91C_PB25_RI0, 0); at91_pio_use_periph_a(AT91SAM9G20_PIOB_BASE, AT91C_PB26_RTS0, 1); at91_pio_use_periph_a(AT91SAM9G20_PIOB_BASE, AT91C_PB27_CTS0, 0); /* PIOB's A periph: Turn USART 1's TX/RX pins */ at91_pio_use_periph_a(AT91SAM9G20_PIOB_BASE, AT91C_PB6_TXD1, 1); at91_pio_use_periph_a(AT91SAM9G20_PIOB_BASE, AT91C_PB7_RXD1, 0); at91_pio_use_periph_a(AT91SAM9G20_PIOB_BASE, AT91C_PB28_RTS1, 1); at91_pio_use_periph_a(AT91SAM9G20_PIOB_BASE, AT91C_PB29_CTS1, 0); /* TWI Two-wire Serial Data */ at91_pio_use_periph_a(AT91SAM9G20_PIOA_BASE,AT91C_PA23_TWD, 1); at91_pio_use_periph_a(AT91SAM9G20_PIOA_BASE,AT91C_PA24_TWCK, 1); #if 1 /* * Turn off Clock to DataFlash, conflicts with MCI clock. */ at91_pio_use_gpio(AT91SAM9G20_PIOA_BASE,AT91C_PIO_PA2); at91_pio_gpio_input(AT91SAM9G20_PIOA_BASE,AT91C_PIO_PA2); /* Turn off chip select to DataFlash */ at91_pio_gpio_output(AT91SAM9G20_PIOC_BASE,AT91C_PIO_PC11, 0); at91_pio_gpio_set(AT91SAM9G20_PIOC_BASE,AT91C_PIO_PC11); at91_pio_use_gpio(AT91SAM9G20_PIOC_BASE,AT91C_PIO_PC11); /* Multimedia Card */ at91_pio_use_periph_b(AT91SAM9G20_PIOA_BASE,AT91C_PA0_MCDB0, 1); at91_pio_use_periph_b(AT91SAM9G20_PIOA_BASE,AT91C_PA1_MCCDB, 1); at91_pio_use_periph_b(AT91SAM9G20_PIOA_BASE,AT91C_PA3_MCDB3, 1); at91_pio_use_periph_b(AT91SAM9G20_PIOA_BASE,AT91C_PA4_MCDB2, 1); at91_pio_use_periph_b(AT91SAM9G20_PIOA_BASE,AT91C_PA5_MCDB1, 1); at91_pio_use_periph_a(AT91SAM9G20_PIOA_BASE,AT91C_PA8_MCCK, 1); at91_pio_use_gpio(AT91SAM9G20_PIOC_BASE, AT91C_PIO_PC9); #else /* SPI0 to DataFlash */ at91_pio_use_periph_a(AT91SAM9G20_PIOA_BASE, AT91C_PIO_PA0, 0); at91_pio_use_periph_a(AT91SAM9G20_PIOA_BASE, AT91C_PIO_PA1, 0); at91_pio_use_periph_a(AT91SAM9G20_PIOA_BASE, AT91C_PIO_PA2, 0); at91_pio_use_periph_b(AT91SAM9G20_PIOC_BASE, AT91C_PIO_PC11,0); at91_pio_gpio_input(AT91SAM9G20_PIOA_BASE,AT91C_PIO_PA8); at91_pio_use_gpio(AT91SAM9G20_PIOA_BASE,AT91C_PIO_PA8); #endif /* EMAC */ at91_pio_use_periph_a(AT91SAM9G20_PIOA_BASE,AT91C_PA12_ETX0 , 0); at91_pio_use_periph_a(AT91SAM9G20_PIOA_BASE,AT91C_PA13_ETX1, 0); at91_pio_use_periph_a(AT91SAM9G20_PIOA_BASE,AT91C_PA14_ERX0, 0); at91_pio_use_periph_a(AT91SAM9G20_PIOA_BASE,AT91C_PA15_ERX1, 0); at91_pio_use_periph_a(AT91SAM9G20_PIOA_BASE,AT91C_PA16_ETXEN, 0); at91_pio_use_periph_a(AT91SAM9G20_PIOA_BASE,AT91C_PA17_ERXDV, 0); at91_pio_use_periph_a(AT91SAM9G20_PIOA_BASE,AT91C_PA18_ERXER, 0); at91_pio_use_periph_a(AT91SAM9G20_PIOA_BASE,AT91C_PA19_ETXCK, 0); at91_pio_use_periph_a(AT91SAM9G20_PIOA_BASE,AT91C_PA20_EMDC, 0); at91_pio_use_periph_a(AT91SAM9G20_PIOA_BASE,AT91C_PA21_EMDIO, 0); at91_pio_use_periph_b(AT91SAM9G20_PIOA_BASE,AT91C_PA10_ETX2_0, 0); at91_pio_use_periph_b(AT91SAM9G20_PIOA_BASE,AT91C_PA11_ETX3_0, 0); at91_pio_use_periph_b(AT91SAM9G20_PIOA_BASE,AT91C_PA22_ETXER, 0); at91_pio_use_periph_b(AT91SAM9G20_PIOA_BASE,AT91C_PA25_ERX2, 0); at91_pio_use_periph_b(AT91SAM9G20_PIOA_BASE,AT91C_PA26_ERX3, 0); at91_pio_use_periph_b(AT91SAM9G20_PIOA_BASE,AT91C_PA27_ERXCK, 0); at91_pio_use_periph_b(AT91SAM9G20_PIOA_BASE,AT91C_PA28_ECRS, 0); at91_pio_use_periph_b(AT91SAM9G20_PIOA_BASE,AT91C_PA29_ECOL, 0); #endif return (at91_ramsize()); }
long board_init(void) { /* Setup Ethernet Pins */ at91_pio_use_periph_a(AT91SAM9G20_PIOA_BASE, 1<<7, 0); at91_pio_gpio_input(AT91SAM9G20_PIOA_BASE, 1<<7); at91_pio_gpio_set_deglitch(AT91SAM9G20_PIOA_BASE, 1<<7, 1); at91_pio_use_periph_a(AT91SAM9G20_PIOA_BASE, AT91C_PIO_PA19, 0); /* ETXCK_EREFCK */ at91_pio_use_periph_a(AT91SAM9G20_PIOA_BASE, AT91C_PIO_PA17, 0); /* ERXDV */ at91_pio_use_periph_a(AT91SAM9G20_PIOA_BASE, AT91C_PIO_PA14, 0); /* ERX0 */ at91_pio_use_periph_a(AT91SAM9G20_PIOA_BASE, AT91C_PIO_PA15, 0); /* ERX1 */ at91_pio_use_periph_a(AT91SAM9G20_PIOA_BASE, AT91C_PIO_PA18, 0); /* ERXER */ at91_pio_use_periph_a(AT91SAM9G20_PIOA_BASE, AT91C_PIO_PA16, 0); /* ETXEN */ at91_pio_use_periph_a(AT91SAM9G20_PIOA_BASE, AT91C_PIO_PA12, 0); /* ETX0 */ at91_pio_use_periph_a(AT91SAM9G20_PIOA_BASE, AT91C_PIO_PA13, 0); /* ETX1 */ at91_pio_use_periph_a(AT91SAM9G20_PIOA_BASE, AT91C_PIO_PA21, 0); /* EMDIO */ at91_pio_use_periph_a(AT91SAM9G20_PIOA_BASE, AT91C_PIO_PA20, 0); /* EMDC */ at91_pio_use_periph_b(AT91SAM9G20_PIOA_BASE, AT91C_PIO_PA28, 0); /* ECRS */ at91_pio_use_periph_b(AT91SAM9G20_PIOA_BASE, AT91C_PIO_PA29, 0); /* ECOL */ at91_pio_use_periph_b(AT91SAM9G20_PIOA_BASE, AT91C_PIO_PA25, 0); /* ERX2 */ at91_pio_use_periph_b(AT91SAM9G20_PIOA_BASE, AT91C_PIO_PA26, 0); /* ERX3 */ at91_pio_use_periph_b(AT91SAM9G20_PIOA_BASE, AT91C_PIO_PA27, 0); /* ERXCK */ at91_pio_use_periph_b(AT91SAM9G20_PIOA_BASE, AT91C_PIO_PA23, 0); /* ETX2 */ at91_pio_use_periph_b(AT91SAM9G20_PIOA_BASE, AT91C_PIO_PA24, 0); /* ETX3 */ at91_pio_use_periph_b(AT91SAM9G20_PIOA_BASE, AT91C_PIO_PA22, 0); /* ETXER */ return (at91_ramsize()); }
BOARD_INIT long board_init(void) { int is_bga, rev_mii; /* * Deal with bootinfo (if any) passed in from the boot2 bootloader and * copied to the static inkernel_bootinfo earlier in the init. Do this * early so that bootverbose is set from this point on. */ if (inkernel_bootinfo.bi_size > 0 && (inkernel_bootinfo.bi_flags & RB_BOOTINFO)) { struct tsc_bootinfo *bip = &inkernel_bootinfo; printf("TSC_BOOTINFO: size %u howtoflags=0x%08x rootdev='%s'\n", bip->bi_size, bip->bi_flags, bip->bi_rootdevname); boothowto = bip->bi_flags; bootverbose = (boothowto & RB_VERBOSE); if (bip->bi_rootdevname[0] != 0) rootdevnames[0] = bip->bi_rootdevname; } /* * The only way to know if we're in a BGA package (and thus have PIOD) * is to be told via a hint; there's nothing detectable in the silicon. * This is esentially an rm92-specific extension to getting the chip ID * (which was done by at91_machdep just before calling this routine). * If it is the BGA package, enable the clock for PIOD. */ is_bga = 0; resource_int_value("at91", 0, "is_bga_package", &is_bga); if (is_bga) WR4HW(AT91RM92_PMC_BASE, PMC_PCER, 1u << AT91RM92_IRQ_PIOD); #if __FreeBSD_version >= 1000000 at91rm9200_set_subtype(is_bga ? AT91_ST_RM9200_BGA : AT91_ST_RM9200_PQFP); #endif /* * Go reprogram the MCK frequency based on hints. */ master_clock_init(); /* * Configure UARTs. */ at91rm9200_config_uart(AT91_ID_DBGU, 0, 0); /* DBGU just Tx and Rx */ at91rm9200_config_uart(AT91RM9200_ID_USART0, 1, 0); /* Tx and Rx */ at91rm9200_config_uart(AT91RM9200_ID_USART1, 2, 0); /* Tx and Rx */ at91rm9200_config_uart(AT91RM9200_ID_USART2, 3, 0); /* Tx and Rx */ at91rm9200_config_uart(AT91RM9200_ID_USART3, 4, 0); /* Tx and Rx */ /* * Configure MCI (sdcard) */ at91rm9200_config_mci(0); /* * Assign the pins needed by the emac device, and power it up. Also, * configure it for RMII operation unless the 'revmii_mode' hint is set, * in which case configure the full set of MII pins. The revmii_mode * hint is for so-called reverse-MII, used for connections to a Broadcom * 5325E switch on some boards. Note that order is important here: * configure pins, then power on the device, then access the device's * config registers. */ rev_mii = 0; resource_int_value("ate", 0, "phy_revmii_mode", &rev_mii); at91_pio_use_periph_a(AT91RM92_PIOA_BASE, AT91C_PIO_PA7 | AT91C_PIO_PA8 | AT91C_PIO_PA9 | AT91C_PIO_PA10 | AT91C_PIO_PA11 | AT91C_PIO_PA12 | AT91C_PIO_PA13 | AT91C_PIO_PA14 | AT91C_PIO_PA15 | AT91C_PIO_PA16, 0); if (rev_mii) { at91_pio_use_periph_b(AT91RM92_PIOB_BASE, AT91C_PIO_PB12 | AT91C_PIO_PB13 | AT91C_PIO_PB14 | AT91C_PIO_PB15 | AT91C_PIO_PB16 | AT91C_PIO_PB17 | AT91C_PIO_PB18 | AT91C_PIO_PB19, 0); } WR4HW(AT91RM92_PMC_BASE, PMC_PCER, 1u << AT91RM92_IRQ_EMAC); if (!rev_mii) { WR4HW(AT91RM92_EMAC_BASE, ETH_CFG, RD4HW(AT91RM92_EMAC_BASE, ETH_CFG) | ETH_CFG_RMII); } /* * Get our ethernet MAC address from the ID eeprom. * Configures TWI as a side effect. */ set_mac_from_idprom(); /* * Configure SPI */ assign_spi_pins(); /* * Configure SSC */ at91_pio_use_periph_a( AT91RM92_PIOB_BASE, AT91C_PIO_PB6 | AT91C_PIO_PB7 | AT91C_PIO_PB8 | /* transmit */ AT91C_PIO_PB9 | AT91C_PIO_PB10 | AT91C_PIO_PB11, /* receive */ 0); /* no pullup */ /* * We're using TC1's A1 input for PPS measurements that drive the * kernel PLL and our NTP refclock. On some old boards we route a 5mhz * signal to TC1's A2 input (pin PA21), but we have never used that * clock (it rolls over too fast for hz=100), and now newer boards are * using pin PA21 as a CTS0 for USART1, so we no longer assign it to * the timer block like we used to here. */ at91_pio_use_periph_b(AT91RM92_PIOA_BASE, AT91C_PIO_PA19, 0); /* * Configure pins used to bitbang-upload the firmware to the main FPGA. */ at91_pio_use_gpio(AT91RM92_PIOB_BASE, AT91C_PIO_PB16 | AT91C_PIO_PB17 | AT91C_PIO_PB18 | AT91C_PIO_PB19); return (at91_ramsize()); }
/* * Assign SPI chip select pins based on which chip selects are found in hints. */ static void assign_spi_pins(void) { struct { uint32_t num; const char * name; } chipsel_pins[] = { { AT91C_PIO_PA3, "PA3", }, { AT91C_PIO_PA4, "PA4", }, { AT91C_PIO_PA5, "PA5", }, { AT91C_PIO_PA6, "PA6", }, }; int anchor = 0; uint32_t chipsel_inuse = 0; /* * Search through all device hints looking for any that have * ".at=spibus0". For each one found, ensure that there is also a * chip select hint ".cs=<num>" and that <num> is 0-3, and assign the * corresponding pin to the SPI peripheral. Whine if we find a SPI * device with a missing or invalid chipsel hint. */ for (;;) { const char * rName = ""; int unit = 0; int cs = 0; int ret; ret = resource_find_match(&anchor, &rName, &unit, "at", "spibus0"); if (ret != 0) break; ret = resource_int_value(rName, unit, "cs", &cs); if (ret != 0) { printf( "Error: hint for SPI device %s%d " "without a chip select hint; " "device will not function.\n", rName, unit); continue; } if (cs < 0 || cs > 3) { printf( "Error: hint for SPI device %s%d " "contains an invalid chip select " "value: %d\n", rName, unit, cs); continue; } if (chipsel_inuse & (1 << cs)) { printf( "Error: hint for SPI device %s%d " "specifies chip select %d, which " "is already used by another device\n", rName, unit, cs); continue; } chipsel_inuse |= 1 << cs; at91_pio_use_periph_a(AT91RM92_PIOA_BASE, chipsel_pins[cs].num, 1); printf( "Configured pin %s as SPI chip " "select %d for %s%d\n", chipsel_pins[cs].name, cs, rName, unit); } /* * If there were hints for any SPI devices, assign the basic SPI IO pins * and enable SPI power (irq numbers are also device IDs for power). */ if (chipsel_inuse != 0) { at91_pio_use_periph_a(AT91RM92_PIOA_BASE, AT91C_PIO_PA1 | AT91C_PIO_PA0 | AT91C_PIO_PA2, 0); WR4HW(AT91RM92_PMC_BASE, PMC_PCER, 1u << AT91RM92_IRQ_SPI); } }
void at91rm9200_config_uart(unsigned devid, unsigned unit, unsigned pinmask) { /* * Since the USART supports RS-485 multidrop mode, it allows the * TX pins to float. However, for RS-232 operations, we don't want * these pins to float. Instead, they should be pulled up to avoid * mismatches. Linux does something similar when it configures the * TX lines. This implies that we also allow the RX lines to float * rather than be in the state they are left in by the boot loader. * Since they are input pins, I think that this is the right thing * to do. */ /* * Current boards supported don't need the extras, but they should be * implemented. But that should wait until the new pin api goes in. */ switch (devid) { case AT91_ID_DBGU: at91_pio_use_periph_a(AT91RM92_PIOA_BASE, AT91C_PIO_PA30, 0); /* DRXD */ at91_pio_use_periph_a(AT91RM92_PIOA_BASE, AT91C_PIO_PA31, 1); /* DTXD */ break; case AT91RM9200_ID_USART0: at91_pio_use_periph_a(AT91RM92_PIOA_BASE, AT91C_PIO_PA17, 1); /* TXD0 */ at91_pio_use_periph_a(AT91RM92_PIOA_BASE, AT91C_PIO_PA18, 0); /* RXD0 */ /* CTS PA20 */ /* RTS -- errata #39 PA21 */ break; case AT91RM9200_ID_USART1: at91_pio_use_periph_a(AT91RM92_PIOB_BASE, AT91C_PIO_PB20, 1); /* TXD1 */ at91_pio_use_periph_a(AT91RM92_PIOB_BASE, AT91C_PIO_PB21, 0); /* RXD1 */ /* RI - PB18 */ /* DTR - PB19 */ /* DCD - PB23 */ /* CTS - PB24 */ /* DSR - PB25 */ /* RTS - PB26 */ break; case AT91RM9200_ID_USART2: at91_pio_use_periph_a(AT91RM92_PIOA_BASE, AT91C_PIO_PA22, 0); /* RXD2 */ at91_pio_use_periph_a(AT91RM92_PIOA_BASE, AT91C_PIO_PA23, 1); /* TXD2 */ /* CTS - PA30 B periph */ /* RTS - PA31 B periph */ break; case AT91RM9200_ID_USART3: at91_pio_use_periph_b(AT91RM92_PIOA_BASE, AT91C_PIO_PA5, 1); /* TXD3 */ at91_pio_use_periph_b(AT91RM92_PIOA_BASE, AT91C_PIO_PA6, 0); /* RXD3 */ /* CTS - PB0 B periph */ /* RTS - PB1 B periph */ break; default: break; } }
BOARD_INIT long board_init(void) { /* * DBGU */ /* DRXD */ at91_pio_use_periph_a(AT91SAM9260_PIOB_BASE, AT91C_PIO_PB14, 0); /* DTXD */ at91_pio_use_periph_a(AT91SAM9260_PIOB_BASE, AT91C_PIO_PB15, 1); /* * EMAC */ /* ETX0 */ at91_pio_use_periph_a(AT91SAM9260_PIOA_BASE, AT91C_PIO_PA12, 0); /* ETX1 */ at91_pio_use_periph_a(AT91SAM9260_PIOA_BASE, AT91C_PIO_PA13, 0); /* ERX0 */ at91_pio_use_periph_a(AT91SAM9260_PIOA_BASE, AT91C_PIO_PA14, 0); /* ERX1 */ at91_pio_use_periph_a(AT91SAM9260_PIOA_BASE, AT91C_PIO_PA15, 0); /* ETXEN */ at91_pio_use_periph_a(AT91SAM9260_PIOA_BASE, AT91C_PIO_PA16, 0); /* ERXDV */ at91_pio_use_periph_a(AT91SAM9260_PIOA_BASE, AT91C_PIO_PA17, 0); /* ERXER */ at91_pio_use_periph_a(AT91SAM9260_PIOA_BASE, AT91C_PIO_PA18, 0); /* ETXCK */ at91_pio_use_periph_a(AT91SAM9260_PIOA_BASE, AT91C_PIO_PA19, 0); /* EMDC */ at91_pio_use_periph_a(AT91SAM9260_PIOA_BASE, AT91C_PIO_PA20, 0); /* EMDIO */ at91_pio_use_periph_a(AT91SAM9260_PIOA_BASE, AT91C_PIO_PA21, 0); /* Not RMII */ /* ETX2 */ at91_pio_use_periph_b(AT91SAM9260_PIOA_BASE, AT91C_PIO_PA10, 0); /* ETX3 */ at91_pio_use_periph_b(AT91SAM9260_PIOA_BASE, AT91C_PIO_PA11, 0); /* ETXER */ at91_pio_use_periph_b(AT91SAM9260_PIOA_BASE, AT91C_PIO_PA22, 0); /* ERX2 */ at91_pio_use_periph_b(AT91SAM9260_PIOA_BASE, AT91C_PIO_PA25, 0); /* ERX3 */ at91_pio_use_periph_b(AT91SAM9260_PIOA_BASE, AT91C_PIO_PA26, 0); /* ERXCK */ at91_pio_use_periph_b(AT91SAM9260_PIOA_BASE, AT91C_PIO_PA27, 0); /* ECRS */ at91_pio_use_periph_b(AT91SAM9260_PIOA_BASE, AT91C_PIO_PA28, 0); /* ECOL */ at91_pio_use_periph_b(AT91SAM9260_PIOA_BASE, AT91C_PIO_PA29, 0); /* * MMC, wired to socket B. */ /* MCDB0 */ at91_pio_use_periph_b(AT91SAM9260_PIOA_BASE, AT91C_PIO_PA0, 1); /* MCCDB */ at91_pio_use_periph_b(AT91SAM9260_PIOA_BASE, AT91C_PIO_PA1, 1); /* MCDB3 */ at91_pio_use_periph_b(AT91SAM9260_PIOA_BASE, AT91C_PIO_PA3, 1); /* MCDB2 */ at91_pio_use_periph_b(AT91SAM9260_PIOA_BASE, AT91C_PIO_PA4, 1); /* MCDB1 */ at91_pio_use_periph_b(AT91SAM9260_PIOA_BASE, AT91C_PIO_PA5, 1); /* MCCK */ at91_pio_use_periph_a(AT91SAM9260_PIOA_BASE, AT91C_PIO_PA8, 1); /* * SPI0 and MMC are wired together, since we don't support sharing * don't support the dataflash. But if you did, you'd have to * use CS0 and CS1. */ /* * SPI1 is wired to a audio CODEC that we don't support, so * give it a pass. */ /* * TWI. Only one child on the iic bus, which we take care of * via hints. */ /* TWD */ at91_pio_use_periph_a(AT91SAM9260_PIOA_BASE, AT91C_PIO_PA23, 1); /* TWCK */ at91_pio_use_periph_a(AT91SAM9260_PIOA_BASE, AT91C_PIO_PA24, 1); /* * USART0 */ /* TXD0 */ at91_pio_use_periph_a(AT91SAM9260_PIOB_BASE, AT91C_PIO_PB4, 1); /* RXD0 */ at91_pio_use_periph_a(AT91SAM9260_PIOB_BASE, AT91C_PIO_PB5, 0); /* DSR0 */ at91_pio_use_periph_a(AT91SAM9260_PIOB_BASE, AT91C_PIO_PB22, 0); /* DCD0 */ at91_pio_use_periph_a(AT91SAM9260_PIOB_BASE, AT91C_PIO_PB23, 0); /* DTR0 */ at91_pio_use_periph_a(AT91SAM9260_PIOB_BASE, AT91C_PIO_PB24, 1); /* RI0 */ at91_pio_use_periph_a(AT91SAM9260_PIOB_BASE, AT91C_PIO_PB25, 0); /* RTS0 */ at91_pio_use_periph_a(AT91SAM9260_PIOB_BASE, AT91C_PIO_PB26, 1); /* CTS0 */ at91_pio_use_periph_a(AT91SAM9260_PIOB_BASE, AT91C_PIO_PB27, 0); /* * USART1 */ /* RTS1 */ at91_pio_use_periph_a(AT91SAM9260_PIOB_BASE, AT91C_PIO_PB28, 1); /* CTS1 */ at91_pio_use_periph_a(AT91SAM9260_PIOB_BASE, AT91C_PIO_PB29, 0); /* TXD1 */ at91_pio_use_periph_a(AT91SAM9260_PIOB_BASE, AT91C_PIO_PB6, 1); /* RXD1 */ at91_pio_use_periph_a(AT91SAM9260_PIOB_BASE, AT91C_PIO_PB7, 0); /* USART2 - USART5 aren't wired up, except via PIO pins, ignore them. */ return (at91_ramsize()); }
BOARD_INIT long board_init(void) { /* * DBGU */ /* DRXD */ at91_pio_use_periph_a(AT91SAM9260_PIOB_BASE, AT91C_PIO_PB14, 0); /* DTXD */ at91_pio_use_periph_a(AT91SAM9260_PIOB_BASE, AT91C_PIO_PB15, 1); /* * EMAC */ /* ETX0 */ at91_pio_use_periph_a(AT91SAM9260_PIOA_BASE, AT91C_PIO_PA12, 0); /* ETX1 */ at91_pio_use_periph_a(AT91SAM9260_PIOA_BASE, AT91C_PIO_PA13, 0); /* ERX0 */ at91_pio_use_periph_a(AT91SAM9260_PIOA_BASE, AT91C_PIO_PA14, 0); /* ERX1 */ at91_pio_use_periph_a(AT91SAM9260_PIOA_BASE, AT91C_PIO_PA15, 0); /* ETXEN */ at91_pio_use_periph_a(AT91SAM9260_PIOA_BASE, AT91C_PIO_PA16, 0); /* ERXDV */ at91_pio_use_periph_a(AT91SAM9260_PIOA_BASE, AT91C_PIO_PA17, 0); /* ERXER */ at91_pio_use_periph_a(AT91SAM9260_PIOA_BASE, AT91C_PIO_PA18, 0); /* ETXCK */ at91_pio_use_periph_a(AT91SAM9260_PIOA_BASE, AT91C_PIO_PA19, 0); /* EMDC */ at91_pio_use_periph_a(AT91SAM9260_PIOA_BASE, AT91C_PIO_PA20, 0); /* EMDIO */ at91_pio_use_periph_a(AT91SAM9260_PIOA_BASE, AT91C_PIO_PA21, 0); /* * MMC */ /* MCDA0 */ at91_pio_use_periph_a(AT91SAM9260_PIOA_BASE, AT91C_PIO_PA6, 1); /* MCCDA */ at91_pio_use_periph_a(AT91SAM9260_PIOA_BASE, AT91C_PIO_PA7, 1); /* MCCK */ at91_pio_use_periph_a(AT91SAM9260_PIOA_BASE, AT91C_PIO_PA8, 1); /* MCDA1 */ at91_pio_use_periph_a(AT91SAM9260_PIOA_BASE, AT91C_PIO_PA9, 1); /* MCDA2 */ at91_pio_use_periph_a(AT91SAM9260_PIOA_BASE, AT91C_PIO_PA10, 1); /* MCDA3 */ at91_pio_use_periph_a(AT91SAM9260_PIOA_BASE, AT91C_PIO_PA11, 1); /* * SPI0 */ /* MISO */ at91_pio_use_periph_a(AT91SAM9260_PIOA_BASE, AT91C_PIO_PA0, 0); /* MOSI */ at91_pio_use_periph_a(AT91SAM9260_PIOA_BASE, AT91C_PIO_PA1, 0); /* SPCK */ at91_pio_use_periph_a(AT91SAM9260_PIOA_BASE, AT91C_PIO_PA2, 0); /* NPCS0 */ at91_pio_use_periph_a(AT91SAM9260_PIOA_BASE, AT91C_PIO_PA3, 0); /* * TWI */ /* TWD */ at91_pio_use_periph_a(AT91SAM9260_PIOA_BASE, AT91C_PIO_PA23, 1); /* TWCK */ at91_pio_use_periph_a(AT91SAM9260_PIOA_BASE, AT91C_PIO_PA24, 1); /* * USART0 */ /* TXD0 */ at91_pio_use_periph_a(AT91SAM9260_PIOB_BASE, AT91C_PIO_PB4, 1); /* RXD0 */ at91_pio_use_periph_a(AT91SAM9260_PIOB_BASE, AT91C_PIO_PB5, 0); /* DSR0 */ at91_pio_use_periph_a(AT91SAM9260_PIOB_BASE, AT91C_PIO_PB22, 0); /* DCD0 */ at91_pio_use_periph_a(AT91SAM9260_PIOB_BASE, AT91C_PIO_PB23, 0); /* DTR0 */ at91_pio_use_periph_a(AT91SAM9260_PIOB_BASE, AT91C_PIO_PB24, 1); /* RI0 */ at91_pio_use_periph_a(AT91SAM9260_PIOB_BASE, AT91C_PIO_PB25, 0); /* RTS0 */ at91_pio_use_periph_a(AT91SAM9260_PIOB_BASE, AT91C_PIO_PB26, 1); /* CTS0 */ at91_pio_use_periph_a(AT91SAM9260_PIOB_BASE, AT91C_PIO_PB27, 0); /* * USART2 */ /* RTS2 */ at91_pio_use_periph_a(AT91SAM9260_PIOA_BASE, AT91C_PIO_PA4, 1); /* CTS2 */ at91_pio_use_periph_a(AT91SAM9260_PIOA_BASE, AT91C_PIO_PA5, 0); /* TXD2 */ at91_pio_use_periph_a(AT91SAM9260_PIOB_BASE, AT91C_PIO_PB8, 1); /* RXD2 */ at91_pio_use_periph_a(AT91SAM9260_PIOB_BASE, AT91C_PIO_PB9, 0); return (at91_ramsize()); }
BOARD_INIT long board_init(void) { //at91_led_create("power", 0, 9, 0); /* PIOB's A periph: Turn USART 0's TX/RX pins */ at91_pio_use_periph_a(AT91SAM9G20_PIOB_BASE, AT91C_PB14_DRXD, 0); at91_pio_use_periph_a(AT91SAM9G20_PIOB_BASE, AT91C_PB15_DTXD, 1); /* PIOB's A periph: Turn USART 0's TX/RX pins */ at91_pio_use_periph_a(AT91SAM9G20_PIOB_BASE, AT91C_PB4_TXD0, 1); at91_pio_use_periph_a(AT91SAM9G20_PIOB_BASE, AT91C_PB5_RXD0, 0); at91_pio_use_periph_a(AT91SAM9G20_PIOB_BASE, AT91C_PB22_DSR0, 0); at91_pio_use_periph_a(AT91SAM9G20_PIOB_BASE, AT91C_PB23_DCD0, 0); at91_pio_use_periph_a(AT91SAM9G20_PIOB_BASE, AT91C_PB24_DTR0, 1); at91_pio_use_periph_a(AT91SAM9G20_PIOB_BASE, AT91C_PB25_RI0, 0); at91_pio_use_periph_a(AT91SAM9G20_PIOB_BASE, AT91C_PB26_RTS0, 1); at91_pio_use_periph_a(AT91SAM9G20_PIOB_BASE, AT91C_PB27_CTS0, 0); /* PIOB's A periph: Turn USART 1's TX/RX pins */ at91_pio_use_periph_a(AT91SAM9G20_PIOB_BASE, AT91C_PB6_TXD1, 1); at91_pio_use_periph_a(AT91SAM9G20_PIOB_BASE, AT91C_PB7_RXD1, 0); at91_pio_use_periph_a(AT91SAM9G20_PIOB_BASE, AT91C_PB28_RTS1, 1); at91_pio_use_periph_a(AT91SAM9G20_PIOB_BASE, AT91C_PB29_CTS1, 0); /* TWI Two-wire Serial Data */ at91_pio_use_periph_a(AT91SAM9G20_PIOA_BASE,AT91C_PA23_TWD, 1); at91_pio_use_periph_a(AT91SAM9G20_PIOA_BASE,AT91C_PA24_TWCK, 1); /* Multimedia Card */ at91_pio_use_periph_a(AT91SAM9G20_PIOA_BASE,AT91C_PA6_MCDA0, 1); at91_pio_use_periph_a(AT91SAM9G20_PIOA_BASE,AT91C_PA7_MCCDA, 1); at91_pio_use_periph_a(AT91SAM9G20_PIOA_BASE,AT91C_PA8_MCCK, 1); at91_pio_use_periph_a(AT91SAM9G20_PIOA_BASE,AT91C_PA9_MCDA1, 1); at91_pio_use_periph_a(AT91SAM9G20_PIOA_BASE,AT91C_PA10_MCDA2, 1); at91_pio_use_periph_a(AT91SAM9G20_PIOA_BASE,AT91C_PA11_MCDA3, 1); /* SPI0 to DataFlash */ at91_pio_use_periph_a(AT91SAM9G20_PIOA_BASE, AT91C_PA0_SPI0_MISO, 0); at91_pio_use_periph_a(AT91SAM9G20_PIOA_BASE, AT91C_PA1_SPI0_MOSI, 0); at91_pio_use_periph_a(AT91SAM9G20_PIOA_BASE, AT91C_PA2_SPI0_SPCK, 0); at91_pio_use_periph_a(AT91SAM9G20_PIOA_BASE, AT91C_PA3_SPI0_NPCS0, 0); /* EMAC */ at91_pio_use_periph_a(AT91SAM9G20_PIOA_BASE,AT91C_PA19_ETXCK, 0); at91_pio_use_periph_a(AT91SAM9G20_PIOA_BASE,AT91C_PA21_EMDIO, 0); at91_pio_use_periph_a(AT91SAM9G20_PIOA_BASE,AT91C_PA20_EMDC, 0); at91_pio_use_periph_a(AT91SAM9G20_PIOA_BASE,AT91C_PA17_ERXDV, 0); at91_pio_use_periph_a(AT91SAM9G20_PIOA_BASE,AT91C_PA16_ETXEN, 0); at91_pio_use_periph_a(AT91SAM9G20_PIOA_BASE,AT91C_PA12_ETX0 , 0); at91_pio_use_periph_a(AT91SAM9G20_PIOA_BASE,AT91C_PA13_ETX1, 0); at91_pio_use_periph_a(AT91SAM9G20_PIOA_BASE,AT91C_PA14_ERX0, 0); at91_pio_use_periph_a(AT91SAM9G20_PIOA_BASE,AT91C_PA15_ERX1, 0); at91_pio_use_periph_a(AT91SAM9G20_PIOA_BASE,AT91C_PA18_ERXER, 0); return (at91_ramsize()); }