void __init plat_time_init(void) { unsigned long cpu_clk_rate; unsigned long ahb_clk_rate; unsigned long ddr_clk_rate; unsigned long ref_clk_rate; if (IS_ENABLED(CONFIG_OF) && mips_machtype == ATH79_MACH_GENERIC_OF) { ath79_of_plat_time_init(); return; } ath79_clocks_init(); cpu_clk_rate = ath79_get_sys_clk_rate("cpu"); ahb_clk_rate = ath79_get_sys_clk_rate("ahb"); ddr_clk_rate = ath79_get_sys_clk_rate("ddr"); ref_clk_rate = ath79_get_sys_clk_rate("ref"); pr_info("Clocks: CPU:%lu.%03luMHz, DDR:%lu.%03luMHz, AHB:%lu.%03luMHz, Ref:%lu.%03luMHz\n", cpu_clk_rate / 1000000, (cpu_clk_rate / 1000) % 1000, ddr_clk_rate / 1000000, (ddr_clk_rate / 1000) % 1000, ahb_clk_rate / 1000000, (ahb_clk_rate / 1000) % 1000, ref_clk_rate / 1000000, (ref_clk_rate / 1000) % 1000); mips_hpt_frequency = cpu_clk_rate / 2; }
void __init ath79_register_uart(void) { unsigned long uart_clk_rate; uart_clk_rate = ath79_get_sys_clk_rate("uart"); if (soc_is_ar71xx()) ath79_gpio_function_enable(AR71XX_GPIO_FUNC_UART_EN); else if (soc_is_ar724x()) ath79_gpio_function_enable(AR724X_GPIO_FUNC_UART_EN); else if (soc_is_ar913x()) ath79_gpio_function_enable(AR913X_GPIO_FUNC_UART_EN); else if (soc_is_ar933x()) ath79_gpio_function_enable(AR933X_GPIO_FUNC_UART_EN); if (soc_is_ar71xx() || soc_is_ar724x() || soc_is_ar913x() || soc_is_ar934x() || soc_is_qca955x()) { ath79_uart_data[0].uartclk = uart_clk_rate; platform_device_register(&ath79_uart_device); } else if (soc_is_ar933x()) { platform_device_register(&ar933x_uart_device); } else { BUG(); } }
void __init plat_time_init(void) { unsigned long cpu_clk_rate; unsigned long ahb_clk_rate; unsigned long ddr_clk_rate; unsigned long ref_clk_rate; ath79_clocks_init(); cpu_clk_rate = ath79_get_sys_clk_rate("cpu"); ahb_clk_rate = ath79_get_sys_clk_rate("ahb"); ddr_clk_rate = ath79_get_sys_clk_rate("ddr"); ref_clk_rate = ath79_get_sys_clk_rate("ref"); pr_info("Clocks: CPU:%lu.%03luMHz, DDR:%lu.%03luMHz, AHB:%lu.%03luMHz, Ref:%lu.%03luMHz\n", cpu_clk_rate / 1000000, (cpu_clk_rate / 1000) % 1000, ddr_clk_rate / 1000000, (ddr_clk_rate / 1000) % 1000, ahb_clk_rate / 1000000, (ahb_clk_rate / 1000) % 1000, ref_clk_rate / 1000000, (ref_clk_rate / 1000) % 1000); mips_hpt_frequency = cpu_clk_rate / 2; }