void __init ath79_register_uart(void)
{
unsigned long uart_clk_rate;
uart_clk_rate = ath79_get_sys_clk_rate("uart");
if (soc_is_ar71xx())
ath79_gpio_function_enable(AR71XX_GPIO_FUNC_UART_EN);
else if (soc_is_ar724x())
ath79_gpio_function_enable(AR724X_GPIO_FUNC_UART_EN);
else if (soc_is_ar913x())
ath79_gpio_function_enable(AR913X_GPIO_FUNC_UART_EN);
else if (soc_is_ar933x())
ath79_gpio_function_enable(AR933X_GPIO_FUNC_UART_EN);
if (soc_is_ar71xx() ||
soc_is_ar724x() ||
soc_is_ar913x() ||
soc_is_ar934x() ||
soc_is_qca955x()) {
ath79_uart_data[0].uartclk = uart_clk_rate;
platform_device_register(&ath79_uart_device);
} else if (soc_is_ar933x()) {
platform_device_register(&ar933x_uart_device);
} else {
BUG();
}
}
void __init ath79_register_uart(void)
{
struct clk *clk;
clk = clk_get(NULL, "uart");
if (IS_ERR(clk))
panic("unable to get UART clock, err=%ld", PTR_ERR(clk));
if (soc_is_ar71xx())
ath79_gpio_function_enable(AR71XX_GPIO_FUNC_UART_EN);
else if (soc_is_ar724x())
ath79_gpio_function_enable(AR724X_GPIO_FUNC_UART_EN);
else if (soc_is_ar913x())
ath79_gpio_function_enable(AR913X_GPIO_FUNC_UART_EN);
else if (soc_is_ar933x())
ath79_gpio_function_enable(AR933X_GPIO_FUNC_UART_EN);
if (soc_is_ar71xx() ||
soc_is_ar724x() ||
soc_is_ar913x() ||
soc_is_ar934x() ||
soc_is_qca953x() ||
soc_is_qca955x()) {
ath79_uart_data[0].uartclk = clk_get_rate(clk);
platform_device_register(&ath79_uart_device);
} else if (soc_is_ar933x()) {
ar933x_uart_data.uartclk = clk_get_rate(clk);
platform_device_register(&ar933x_uart_device);
} else {
BUG();
}
}
static void __init cf_e320n_v2_setup(void)
{
cf_exxxn_common_setup(0x10000, CF_E320N_V2_GPIO_EXT_WDT);
cf_exxxn_qca953x_eth_setup();
/* Disable JTAG (enables GPIO0-3) */
ath79_gpio_function_enable(AR934X_GPIO_FUNC_JTAG_DISABLE);
ath79_gpio_direction_select(CF_E320N_V2_GPIO_LED_LAN, true);
ath79_gpio_direction_select(CF_E320N_V2_GPIO_LED_WAN, true);
ath79_gpio_direction_select(CF_E320N_V2_GPIO_LED_WLAN, true);
ath79_gpio_output_select(CF_E320N_V2_GPIO_LED_LAN, 0);
ath79_gpio_output_select(CF_E320N_V2_GPIO_LED_WAN, 0);
ath79_gpio_output_select(CF_E320N_V2_GPIO_LED_WLAN, 0);
/* Enable GPIO function for GPIOs in J9 header */
ath79_gpio_output_select(CF_E320N_V2_GPIO_HEADER_J9_1, 0);
ath79_gpio_output_select(CF_E320N_V2_GPIO_HEADER_J9_2, 0);
ath79_gpio_output_select(CF_E320N_V2_GPIO_HEADER_J9_3, 0);
ath79_gpio_output_select(CF_E320N_V2_GPIO_HEADER_J9_4, 0);
ath79_register_leds_gpio(-1, ARRAY_SIZE(cf_e320n_v2_leds_gpio),
cf_e320n_v2_leds_gpio);
ath79_register_gpio_keys_polled(-1, CF_EXXXN_KEYS_POLL_INTERVAL,
ARRAY_SIZE(cf_e320n_v2_gpio_keys),
cf_e320n_v2_gpio_keys);
}
/*
* Init the wAPGSC (RB wAPG-5HacT2HnD // wAP AC) hardware.
* The wAPGSC has one Ethernet port via AR8033 with PoE input, dual radio (SoC
* 2.4 GHz and external QCA9880) and a ZT2046Q temperature and voltage sensor
* (currently not supported).
*/
static void __init rbwapgsc_setup(void)
{
u32 flags = RBSPI_HAS_PCI;
if (!rbspi_platform_setup())
return;
rbspi_peripherals_setup(flags);
platform_device_register(&rbwapgsc_phy_device);
ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 0);
ath79_eth1_data.mii_bus_dev = &rbwapgsc_phy_device.dev;
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII;
ath79_eth1_data.phy_mask = BIT(RBWAPGSC_MDIO_PHYADDR);
ath79_eth1_pll_data.pll_1000 = 0x03000101;
ath79_eth1_pll_data.pll_100 = 0x80000101;
ath79_eth1_pll_data.pll_10 = 0x80001313;
ath79_eth1_data.speed = SPEED_1000;
ath79_eth1_data.duplex = DUPLEX_FULL;
ath79_register_eth(1);
rbspi_wlan_init(1, 2);
rbspi_register_reset_button(RBWAPGSC_GPIO_BTN_RESET);
ath79_gpio_function_enable(QCA955X_GPIO_FUNC_JTAG_DISABLE|
QCA955X_GPIO_REG_OUT_FUNC4|
QCA955X_GPIO_REG_OUT_FUNC3);
ath79_register_leds_gpio(-1, ARRAY_SIZE(rbwapgsc_leds),
rbwapgsc_leds);
}
static void __init carambola2_common_setup(void)
{
u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
/* Disable UART, enabling GPIO 9 and GPIO 10 */
ath79_gpio_function_disable(AR933X_GPIO_FUNC_UART_EN);
/* Enabling internal CS1, disable GPIO 9 */
ath79_gpio_function_enable(AR933X_GPIO_FUNC_SPI_CS_EN1);
ath79_register_m25p80i_multi(NULL);
ath79_register_wmac(art + CARAMBOLA2_CALDATA_OFFSET,
art + CARAMBOLA2_WMAC_MAC_OFFSET);
ath79_setup_ar933x_phy4_switch(true, true);
ath79_init_mac(ath79_eth0_data.mac_addr, art + CARAMBOLA2_MAC0_OFFSET, 0);
ath79_init_mac(ath79_eth1_data.mac_addr, art + CARAMBOLA2_MAC1_OFFSET, 0);
ath79_register_mdio(0, 0x0);
/* LAN ports */
ath79_register_eth(1);
/* WAN port */
ath79_register_eth(0);
// spi_register_board_info(ath79_spi_info, ARRAY_SIZE(ath79_spi_info));
}
static void __init om5p_acv2_setup(void)
{
u8 *art = (u8 *)KSEG1ADDR(0x1fff0000);
u8 mac[6];
/* power amplifier high power, 4.2V at RFFM4203/4503 instead of 3.3 */
ath79_gpio_function_enable(QCA955X_GPIO_FUNC_JTAG_DISABLE);
ath79_gpio_output_select(OM5PACV2_GPIO_PA_DCDC, QCA955X_GPIO_OUT_GPIO);
ath79_gpio_output_select(OM5PACV2_GPIO_PA_HIGH, QCA955X_GPIO_OUT_GPIO);
gpio_request_one(OM5PACV2_GPIO_PA_DCDC, GPIOF_OUT_INIT_HIGH,
"PA DC/DC");
gpio_request_one(OM5PACV2_GPIO_PA_HIGH, GPIOF_OUT_INIT_HIGH, "PA HIGH");
/* temperature sensor */
platform_device_register(&om5pacv2_i2c_device);
i2c_register_board_info(0, om5pacv2_i2c_devs,
ARRAY_SIZE(om5pacv2_i2c_devs));
ath79_register_m25p80(&om5pacv2_flash_data);
ath79_register_leds_gpio(-1, ARRAY_SIZE(om5pacv2_leds_gpio),
om5pacv2_leds_gpio);
ath79_register_gpio_keys_polled(-1, OM5PACV2_KEYS_POLL_INTERVAL,
ARRAY_SIZE(om5pacv2_gpio_keys),
om5pacv2_gpio_keys);
ath79_init_mac(mac, art, 0x02);
ath79_register_wmac(art + OM5PACV2_WMAC_CALDATA_OFFSET, mac);
om5p_acv2_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN, 2, 2, 0, 0);
ath79_register_mdio(0, 0x0);
ath79_register_mdio(1, 0x0);
mdiobus_register_board_info(om5pacv2_an_mdio0_info,
ARRAY_SIZE(om5pacv2_an_mdio0_info));
ath79_init_mac(ath79_eth0_data.mac_addr, art, 0x00);
ath79_init_mac(ath79_eth1_data.mac_addr, art, 0x01);
/* GMAC0 is connected to the PHY4 */
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
ath79_eth0_data.phy_mask = BIT(4);
ath79_eth0_pll_data.pll_1000 = 0x82000101;
ath79_eth0_pll_data.pll_100 = 0x80000101;
ath79_eth0_pll_data.pll_10 = 0x80001313;
ath79_register_eth(0);
/* GMAC1 is connected to MDIO1 in SGMII mode */
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII;
ath79_eth1_data.mii_bus_dev = &ath79_mdio1_device.dev;
ath79_eth1_data.phy_mask = BIT(1);
ath79_eth1_pll_data.pll_1000 = 0x03000101;
ath79_eth1_pll_data.pll_100 = 0x80000101;
ath79_eth1_pll_data.pll_10 = 0x80001313;
ath79_eth1_data.speed = SPEED_1000;
ath79_eth1_data.duplex = DUPLEX_FULL;
ath79_register_eth(1);
ath79_register_pci();
}
static void __init alfa_ap96_gpio_setup(void)
{
ath79_gpio_function_enable(AR71XX_GPIO_FUNC_SPI_CS1_EN |
AR71XX_GPIO_FUNC_SPI_CS2_EN);
gpio_request(ALFA_AP96_GPIO_MICROSD_CD, "microSD CD");
gpio_direction_input(ALFA_AP96_GPIO_MICROSD_CD);
gpio_request(ALFA_AP96_GPIO_PCIE_RESET, "PCIe reset");
gpio_direction_output(ALFA_AP96_GPIO_PCIE_RESET, 1);
gpio_request(ALFA_AP96_GPIO_PCIE_W_DISABLE, "PCIe write disable");
gpio_direction_output(ALFA_AP96_GPIO_PCIE_W_DISABLE, 1);
}
static void __init om2p_hs_setup(void)
{
u8 *mac1 = (u8 *)KSEG1ADDR(0x1ffc0000);
u8 *mac2 = (u8 *)KSEG1ADDR(0x1ffc0000 + ETH_ALEN);
u8 *art = (u8 *)KSEG1ADDR(0x1ffc1000);
/* make lan / wan leds software controllable */
ath79_gpio_output_select(OM2P_GPIO_LED_LAN, AR934X_GPIO_OUT_GPIO);
ath79_gpio_output_select(OM2P_GPIO_LED_WAN, AR934X_GPIO_OUT_GPIO);
/* enable reset button */
ath79_gpio_output_select(OM2P_GPIO_BTN_RESET, AR934X_GPIO_OUT_GPIO);
ath79_gpio_function_enable(AR934X_GPIO_FUNC_JTAG_DISABLE);
om2p_leds_gpio[4].gpio = OM2P_GPIO_LED_WAN;
om2p_leds_gpio[5].gpio = OM2P_GPIO_LED_LAN;
ath79_register_m25p80(&om2p_lc_flash_data);
ath79_register_leds_gpio(-1, ARRAY_SIZE(om2p_leds_gpio),
om2p_leds_gpio);
ath79_register_gpio_keys_polled(-1, OM2P_KEYS_POLL_INTERVAL,
ARRAY_SIZE(om2p_gpio_keys),
om2p_gpio_keys);
ath79_register_wmac(art, NULL);
ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_PHY_SWAP);
ath79_register_mdio(1, 0x0);
ath79_init_mac(ath79_eth0_data.mac_addr, mac1, 0);
ath79_init_mac(ath79_eth1_data.mac_addr, mac2, 0);
/* GMAC0 is connected to the PHY0 of the internal switch */
ath79_switch_data.phy4_mii_en = 1;
ath79_switch_data.phy_poll_mask = BIT(0);
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
ath79_eth0_data.phy_mask = BIT(0);
ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev;
ath79_register_eth(0);
/* GMAC1 is connected to the internal switch */
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
ath79_register_eth(1);
}
static void __init cf_e380ac_v1v2_common_setup(unsigned long art_ofs)
{
u8 *mac = (u8 *) KSEG1ADDR(0x1f000000 + art_ofs);
cf_exxxn_common_setup(art_ofs, CF_E380AC_V1V2_GPIO_EXT_WDT);
ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
ath79_register_mdio(0, 0x0);
mdiobus_register_board_info(cf_e380ac_v1v2_mdio0_info,
ARRAY_SIZE(cf_e380ac_v1v2_mdio0_info));
/* LAN */
ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ath79_eth0_data.phy_mask = BIT(0);
ath79_eth0_pll_data.pll_1000 = 0xbe000000;
ath79_eth0_pll_data.pll_100 = 0xb0000101;
ath79_eth0_pll_data.pll_10 = 0xb0001313;
ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0);
ath79_register_eth(0);
ap91_pci_init(mac + 0x5000, NULL);
/* Disable JTAG (enables GPIO0-3) */
ath79_gpio_function_enable(AR934X_GPIO_FUNC_JTAG_DISABLE);
ath79_gpio_direction_select(CF_E380AC_V1V2_GPIO_LED_LAN, true);
ath79_gpio_direction_select(CF_E380AC_V1V2_GPIO_LED_WLAN2G, true);
ath79_gpio_direction_select(CF_E380AC_V1V2_GPIO_LED_WLAN5G, true);
ath79_gpio_output_select(CF_E380AC_V1V2_GPIO_LED_LAN, 0);
ath79_gpio_output_select(CF_E380AC_V1V2_GPIO_LED_WLAN2G, 0);
ath79_gpio_output_select(CF_E380AC_V1V2_GPIO_LED_WLAN5G, 0);
/* For J7-4 */
ath79_gpio_function_disable(AR934X_GPIO_FUNC_CLK_OBS4_EN);
ath79_register_gpio_keys_polled(-1, CF_EXXXN_KEYS_POLL_INTERVAL,
ARRAY_SIZE(cf_e380ac_v1v2_gpio_keys),
cf_e380ac_v1v2_gpio_keys);
}
static void __init gl_ar300m_setup(void)
{
u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
u8 tmpmac[ETH_ALEN];
ath79_gpio_function_enable(AR934X_GPIO_FUNC_JTAG_DISABLE);
ath79_register_spi(&gl_ar300m_spi_data, gl_ar300m_spi_info, 2);
/* register gpio LEDs and keys */
ath79_register_leds_gpio(-1, ARRAY_SIZE(gl_ar300m_leds_gpio),
gl_ar300m_leds_gpio);
ath79_register_gpio_keys_polled(-1, GL_AR300M_KEYS_POLL_INTERVAL,
ARRAY_SIZE(gl_ar300m_gpio_keys),
gl_ar300m_gpio_keys);
ath79_register_mdio(0, 0x0);
/* WAN */
ath79_init_mac(ath79_eth0_data.mac_addr, art + GL_AR300M_MAC0_OFFSET, 0);
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
ath79_eth0_data.speed = SPEED_100;
ath79_eth0_data.duplex = DUPLEX_FULL;
ath79_eth0_data.phy_mask = BIT(4);
ath79_register_eth(0);
/* LAN */
ath79_init_mac(ath79_eth1_data.mac_addr, art + GL_AR300M_MAC1_OFFSET, 0);
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
ath79_eth1_data.speed = SPEED_1000;
ath79_eth1_data.duplex = DUPLEX_FULL;
ath79_switch_data.phy_poll_mask |= BIT(4);
ath79_switch_data.phy4_mii_en = 1;
ath79_register_eth(1);
ath79_init_mac(tmpmac, art + GL_AR300M_WMAC_CALDATA_OFFSET + 2, 0);
ath79_register_wmac(art + GL_AR300M_WMAC_CALDATA_OFFSET, tmpmac);
/* enable usb */
ath79_register_usb();
/* enable pci */
ath79_register_pci();
}
static void __init cr5000_setup(void)
{
u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
ath79_gpio_function_enable(AR934X_GPIO_FUNC_JTAG_DISABLE);
gpio_request_one(CR5000_GPIO_LED_POWER_ENABLE,
GPIOF_OUT_INIT_LOW, "Power LED enable");
ath79_gpio_output_select(CR5000_GPIO_LED_POWER_AMBER, AR934X_GPIO_OUT_GPIO);
ath79_gpio_output_select(CR5000_GPIO_LED_WLAN_2G, AR934X_GPIO_OUT_GPIO);
ath79_gpio_output_select(CR5000_GPIO_LED_WPS, AR934X_GPIO_OUT_GPIO);
ath79_register_m25p80(NULL);
ath79_register_leds_gpio(-1, ARRAY_SIZE(cr5000_leds_gpio),
cr5000_leds_gpio);
ath79_register_gpio_keys_polled(-1, CR5000_KEYS_POLL_INTERVAL,
ARRAY_SIZE(cr5000_gpio_keys),
cr5000_gpio_keys);
ath79_register_usb();
ath79_register_wmac(art + CR5000_WMAC_CALDATA_OFFSET, art + CR5000_WMAC_MAC_OFFSET);
ap94_pci_init(NULL, NULL, NULL, art + CR5000_PCIE_MAC_OFFSET);
ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0);
ath79_register_mdio(0, 0x0);
ath79_init_mac(ath79_eth0_data.mac_addr, art + CR5000_MAC0_OFFSET, 0);
mdiobus_register_board_info(cr5000_mdio0_info,
ARRAY_SIZE(cr5000_mdio0_info));
/* GMAC0 is connected to an AR8327 switch */
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ath79_eth0_data.phy_mask = BIT(0);
ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
ath79_eth0_pll_data.pll_1000 = 0x06000000;
ath79_register_eth(0);
}
static void __init cf_e38xac_common_setup(unsigned long art_ofs)
{
cf_exxxn_common_setup(art_ofs, CF_E38XAC_GPIO_EXT_WDT);
ath79_register_pci();
/* Disable JTAG (enables GPIO0-3) */
ath79_gpio_function_enable(AR934X_GPIO_FUNC_JTAG_DISABLE);
ath79_gpio_direction_select(CF_E38XAC_GPIO_LED_LAN, true);
ath79_gpio_direction_select(CF_E38XAC_GPIO_LED_WLAN2G, true);
ath79_gpio_direction_select(CF_E38XAC_GPIO_LED_WLAN5G, true);
ath79_gpio_output_select(CF_E38XAC_GPIO_LED_LAN, 0);
ath79_gpio_output_select(CF_E38XAC_GPIO_LED_WLAN2G, 0);
ath79_gpio_output_select(CF_E38XAC_GPIO_LED_WLAN5G, 0);
/* For J7-4 */
ath79_gpio_function_disable(AR934X_GPIO_FUNC_CLK_OBS4_EN);
ath79_register_gpio_keys_polled(-1, CF_EXXXN_KEYS_POLL_INTERVAL,
ARRAY_SIZE(cf_e38xac_gpio_keys),
cf_e38xac_gpio_keys);
}
static void __init qihoo_c301_setup(void)
{
ath79_register_m25p80_multi(&flash);
ath79_gpio_function_enable(AR934X_GPIO_FUNC_JTAG_DISABLE);
ath79_gpio_output_select(QIHOO_C301_GPIO_LED_WAN,
AR934X_GPIO_OUT_LED_LINK4);
ath79_gpio_output_select(QIHOO_C301_GPIO_LED_LAN1,
AR934X_GPIO_OUT_LED_LINK1);
ath79_gpio_output_select(QIHOO_C301_GPIO_LED_LAN2,
AR934X_GPIO_OUT_LED_LINK2);
ath79_gpio_output_select(QIHOO_C301_GPIO_SPI_CS1,
AR934X_GPIO_OUT_SPI_CS1);
gpio_request_one(QIHOO_C301_GPIO_ETH_LEN_EN,
GPIOF_OUT_INIT_LOW | GPIOF_EXPORT_DIR_FIXED,
"Ethernet LED enable");
ath79_register_leds_gpio(-1, ARRAY_SIZE(qihoo_c301_leds_gpio),
qihoo_c301_leds_gpio);
ath79_register_gpio_keys_polled(-1, QIHOO_C301_KEYS_POLL_INTERVAL,
ARRAY_SIZE(qihoo_c301_gpio_keys),
qihoo_c301_gpio_keys);
ath79_wmac_set_ext_lna_gpio(0, QIHOO_C301_GPIO_EXTERNAL_LNA0);
ath79_wmac_set_ext_lna_gpio(1, QIHOO_C301_GPIO_EXTERNAL_LNA1);
qihoo_c301_get_mac("wlan24mac=", wlan24mac);
ath79_register_pci();
ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_ONLY_MODE |
AR934X_ETH_CFG_SW_PHY_SWAP);
ath79_register_mdio(1, 0x0);
/* LAN */
qihoo_c301_get_mac("lanmac=", ath79_eth1_data.mac_addr);
/* GMAC1 is connected to the internal switch */
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
ath79_register_eth(1);
/* WAN */
qihoo_c301_get_mac("wanmac=", ath79_eth0_data.mac_addr);
/* GMAC0 is connected to the PHY4 of the internal switch */
ath79_switch_data.phy4_mii_en = 1;
ath79_switch_data.phy_poll_mask = BIT(0);
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
ath79_eth0_data.phy_mask = BIT(0);
ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev;
ath79_register_eth(0);
gpio_request_one(QIHOO_C301_GPIO_USB_POWER,
GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
"USB power");
ath79_register_usb();
qihoo_c301_board = 1;
}
static void __init wr2041n_setup(void)
{
u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
u8 tmpmac[ETH_ALEN];
ath79_register_m25p80(&wr2041n_flash_data);
/* Disable JTAG to enable GPIO 0-4 */
ath79_gpio_function_enable(AR934X_GPIO_FUNC_JTAG_DISABLE);
ath79_register_leds_gpio(-1, ARRAY_SIZE(wr2041n_leds_gpio),
wr2041n_leds_gpio);
ath79_register_gpio_keys_polled(-1, WR2041N_KEYS_POLL_INTERVAL,
ARRAY_SIZE(wr2041n_gpio_keys),
wr2041n_gpio_keys);
ath79_init_mac(tmpmac, mac, 0);
ath79_register_wmac(art + WR2041N_WMAC_CALDATA_OFFSET, tmpmac);
ath79_init_mac(tmpmac, mac, 1);
// try to setup wlan led pin
ath79_wmac_set_led_pin(WR2041N_GPIO_WMAC_LED_WLAN);
ap91_pci_init(art + WR2041N_PCIE_CALDATA_OFFSET, tmpmac);
ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_ONLY_MODE);
ath79_register_mdio(1, 0x0);
/* LAN */
ath79_init_mac(ath79_eth1_data.mac_addr, mac, -1);
/* GMAC1 is connected to the internal switch */
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
ath79_register_eth(1);
/* WAN */
ath79_init_mac(ath79_eth0_data.mac_addr, mac, 2);
/* GMAC0 is connected to the PHY4 of the internal switch */
ath79_switch_data.phy4_mii_en = 1;
ath79_switch_data.phy_poll_mask = BIT(4);
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
ath79_eth0_data.phy_mask = BIT(4);
ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev;
ath79_register_eth(0);
ath79_gpio_output_select(WR2041N_GPIO_LED_WAN,
AR934X_GPIO_OUT_LED_LINK4);
ath79_gpio_output_select(WR2041N_GPIO_LED_LAN1,
AR934X_GPIO_OUT_LED_LINK3);
ath79_gpio_output_select(WR2041N_GPIO_LED_LAN2,
AR934X_GPIO_OUT_LED_LINK2);
ath79_gpio_output_select(WR2041N_GPIO_LED_LAN3,
AR934X_GPIO_OUT_LED_LINK1);
ath79_gpio_output_select(WR2041N_GPIO_LED_LAN4,
AR934X_GPIO_OUT_LED_LINK0);
}