static void __init zcn_1523h_generic_setup(void)
{
u8 *mac = (u8 *) KSEG1ADDR(0x1f7e0004);
u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000);
ath79_gpio_function_disable(AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN |
AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN |
AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN |
AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN |
AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN);
ath79_register_m25p80(NULL);
ath79_register_leds_gpio(0, ARRAY_SIZE(zcn_1523h_leds_gpio),
zcn_1523h_leds_gpio);
ath79_register_gpio_keys_polled(-1, ZCN_1523H_KEYS_POLL_INTERVAL,
ARRAY_SIZE(zcn_1523h_gpio_keys),
zcn_1523h_gpio_keys);
ap91_pci_init(ee, mac);
ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0);
ath79_init_mac(ath79_eth1_data.mac_addr, mac, 1);
ath79_register_mdio(0, 0x0);
/* LAN1 port */
ath79_register_eth(0);
}
static void __init tl_wa901nd_v2_setup(void)
{
u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000);
ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0);
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
ath79_eth0_data.phy_mask = 0x00001000;
ath79_register_mdio(0, 0x0);
ath79_eth0_data.reset_bit = AR71XX_RESET_GE0_MAC |
AR71XX_RESET_GE0_PHY;
ath79_register_eth(0);
ath79_register_m25p80(&tl_wa901nd_v2_flash_data);
ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wa901nd_v2_leds_gpio),
tl_wa901nd_v2_leds_gpio);
ath79_register_gpio_keys_polled(-1, TL_WA901ND_V2_KEYS_POLL_INTERVAL,
ARRAY_SIZE(tl_wa901nd_v2_gpio_keys),
tl_wa901nd_v2_gpio_keys);
ath79_register_wmac(eeprom, mac);
}
static void __init mr600_base_setup(unsigned num_leds, struct gpio_led *leds)
{
u8 *art = (u8 *)KSEG1ADDR(0x1fff0000);
u8 mac[6];
ath79_register_m25p80(NULL);
ath79_register_leds_gpio(-1, num_leds, leds);
ath79_register_gpio_keys_polled(-1, MR600_KEYS_POLL_INTERVAL,
ARRAY_SIZE(mr600_gpio_keys),
mr600_gpio_keys);
ath79_init_mac(mac, art + MR600_MAC_OFFSET, 1);
ath79_register_wmac(art + MR600_WMAC_CALDATA_OFFSET, mac);
ath79_init_mac(mac, art + MR600_MAC_OFFSET, 8);
ap91_pci_init(art + MR600_PCIE_CALDATA_OFFSET, mac);
ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0 |
AR934X_ETH_CFG_SW_ONLY_MODE);
ath79_register_mdio(0, 0x0);
ath79_init_mac(ath79_eth0_data.mac_addr, art + MR600_MAC_OFFSET, 0);
/* GMAC0 is connected to an external PHY */
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ath79_eth0_data.phy_mask = BIT(0);
ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
ath79_eth0_pll_data.pll_1000 = 0x06000000;
ath79_register_eth(0);
}
static void __init cpe510_setup(void)
{
u8 *mac = (u8 *) KSEG1ADDR(0x1f830008);
u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000);
/* Disable JTAG, enabling GPIOs 0-3 */
/* Configure OBS4 line, for GPIO 4*/
ath79_gpio_function_setup(AR934X_GPIO_FUNC_JTAG_DISABLE,
AR934X_GPIO_FUNC_CLK_OBS4_EN);
ath79_register_leds_gpio(-1, ARRAY_SIZE(cpe510_leds_gpio),
cpe510_leds_gpio);
ath79_register_gpio_keys_polled(1, CPE510_KEYS_POLL_INTERVAL,
ARRAY_SIZE(cpe510_gpio_keys),
cpe510_gpio_keys);
ath79_wmac_set_ext_lna_gpio(0, CPE510_GPIO_EXTERNAL_LNA0);
ath79_wmac_set_ext_lna_gpio(1, CPE510_GPIO_EXTERNAL_LNA1);
ath79_register_m25p80(NULL);
ath79_register_mdio(1, 0);
ath79_init_mac(ath79_eth1_data.mac_addr, mac, 0);
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
ath79_register_eth(1);
ath79_register_wmac(ee, mac);
}
static void __init ubnt_uap_pro_setup(void)
{
u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff0000);
ath79_register_m25p80(NULL);
ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_uap_pro_gpio_leds),
ubnt_uap_pro_gpio_leds);
ath79_register_gpio_keys_polled(-1, UBNT_XM_KEYS_POLL_INTERVAL,
ARRAY_SIZE(uap_pro_gpio_keys),
uap_pro_gpio_keys);
ath79_register_wmac(eeprom + UAP_PRO_WMAC_CALDATA_OFFSET, NULL);
ap91_pci_init(eeprom + UAP_PRO_PCI_CALDATA_OFFSET, NULL);
ath79_register_mdio(0, 0x0);
mdiobus_register_board_info(uap_pro_mdio0_info,
ARRAY_SIZE(uap_pro_mdio0_info));
ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0);
ath79_init_mac(ath79_eth0_data.mac_addr,
eeprom + UAP_PRO_MAC0_OFFSET, 0);
/* GMAC0 is connected to an AR8327 switch */
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ath79_eth0_data.phy_mask = BIT(0);
ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
ath79_eth0_pll_data.pll_1000 = 0x06000000;
ath79_register_eth(0);
}
static void __init tl_mr3020_setup(void)
{
u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000);
ath79_setup_ar933x_phy4_switch(false, true);
ath79_register_m25p80(&tl_mr3020_flash_data);
ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_mr3020_leds_gpio),
tl_mr3020_leds_gpio);
ath79_register_gpio_keys_polled(-1, TL_MR3020_KEYS_POLL_INTERVAL,
ARRAY_SIZE(tl_mr3020_gpio_keys),
tl_mr3020_gpio_keys);
ath79_set_usb_power_gpio(TL_MR3020_GPIO_USB_POWER, GPIOF_OUT_INIT_HIGH,
"USB power");
ath79_register_usb();
ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0);
ath79_register_mdio(0, 0x0);
ath79_register_eth(0);
ath79_eth0_data.phy_mask = BIT(0);
ath79_register_wmac(ee, mac);
}
static void __init rw2458n_setup(void)
{
u8 *mac1 = (u8 *) KSEG1ADDR(0x1fff0000);
u8 *mac2 = (u8 *) KSEG1ADDR(0x1fff0000 + ETH_ALEN);
u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000);
ath79_register_m25p80(&rw2458n_flash_data);
ath79_register_mdio(0, ~RW2458N_WAN_PHYMASK);
ath79_init_mac(ath79_eth0_data.mac_addr, mac1, 0);
ath79_init_mac(ath79_eth1_data.mac_addr, mac2, 0);
ath79_register_eth(0);
ath79_register_eth(1);
ap91_pci_init(ee, NULL);
ath79_register_leds_gpio(-1, ARRAY_SIZE(rw2458n_leds_gpio),
rw2458n_leds_gpio);
ath79_register_gpio_keys_polled(-1, RW2458N_KEYS_POLL_INTERVAL,
ARRAY_SIZE(rw2458n_gpio_keys),
rw2458n_gpio_keys);
ath79_register_usb();
}
static void __init MK5_setup(void)
{
u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000);
/* Disable hardware control LAN1 and LAN2 LEDs, enabling GPIO14 and GPIO15 */
ath79_gpio_function_disable(AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN |
AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN |
AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN |
AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN);
ath79_register_leds_gpio(-1, ARRAY_SIZE(MK5_leds_gpio),
MK5_leds_gpio);
ath79_register_gpio_keys_polled(-1, MK5_KEYS_POLL_INTERVAL,
ARRAY_SIZE(MK5_gpio_keys),
MK5_gpio_keys);
ath79_register_usb();
ath79_register_m25p80(&MK5_flash_data);
ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0);
ath79_register_mdio(0, 0x0);
ath79_register_eth(0);
ath79_register_wmac(ee, mac);
}
/*
* The hAP, hEX lite and hEX PoE lite share the same platform
*/
static void __init rbspi_952_750r2_setup(u32 flags)
{
if (flags & RBSPI_HAS_SSR)
rbspi_spi_cs_gpios[1] = RB952_GPIO_SSR_CS;
rbspi_peripherals_setup(flags);
/* GMAC1 is HW MAC + 1, WLAN MAC IS HW MAC + 5 */
rbspi_network_setup(flags, 1, 5);
if (flags & RBSPI_HAS_USB)
gpio_request_one(RB952_GPIO_USB_POWER,
GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
"USB power");
if (flags & RBSPI_HAS_POE)
gpio_request_one(RB952_GPIO_POE_POWER,
GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
"POE power");
ath79_register_leds_gpio(-1, ARRAY_SIZE(rb952_leds), rb952_leds);
/* These devices have a single reset button as gpio 16 */
ath79_register_gpio_keys_polled(-1, RBSPI_KEYS_POLL_INTERVAL,
ARRAY_SIZE(rbspi_gpio_keys_reset16),
rbspi_gpio_keys_reset16);
}
static void __init om5p_acv2_setup(void)
{
u8 *art = (u8 *)KSEG1ADDR(0x1fff0000);
u8 mac[6];
/* power amplifier high power, 4.2V at RFFM4203/4503 instead of 3.3 */
ath79_gpio_function_enable(QCA955X_GPIO_FUNC_JTAG_DISABLE);
ath79_gpio_output_select(OM5PACV2_GPIO_PA_DCDC, QCA955X_GPIO_OUT_GPIO);
ath79_gpio_output_select(OM5PACV2_GPIO_PA_HIGH, QCA955X_GPIO_OUT_GPIO);
gpio_request_one(OM5PACV2_GPIO_PA_DCDC, GPIOF_OUT_INIT_HIGH,
"PA DC/DC");
gpio_request_one(OM5PACV2_GPIO_PA_HIGH, GPIOF_OUT_INIT_HIGH, "PA HIGH");
/* temperature sensor */
platform_device_register(&om5pacv2_i2c_device);
i2c_register_board_info(0, om5pacv2_i2c_devs,
ARRAY_SIZE(om5pacv2_i2c_devs));
ath79_register_m25p80(&om5pacv2_flash_data);
ath79_register_leds_gpio(-1, ARRAY_SIZE(om5pacv2_leds_gpio),
om5pacv2_leds_gpio);
ath79_register_gpio_keys_polled(-1, OM5PACV2_KEYS_POLL_INTERVAL,
ARRAY_SIZE(om5pacv2_gpio_keys),
om5pacv2_gpio_keys);
ath79_init_mac(mac, art, 0x02);
ath79_register_wmac(art + OM5PACV2_WMAC_CALDATA_OFFSET, mac);
om5p_acv2_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN, 2, 2, 0, 0);
ath79_register_mdio(0, 0x0);
ath79_register_mdio(1, 0x0);
mdiobus_register_board_info(om5pacv2_an_mdio0_info,
ARRAY_SIZE(om5pacv2_an_mdio0_info));
ath79_init_mac(ath79_eth0_data.mac_addr, art, 0x00);
ath79_init_mac(ath79_eth1_data.mac_addr, art, 0x01);
/* GMAC0 is connected to the PHY4 */
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
ath79_eth0_data.phy_mask = BIT(4);
ath79_eth0_pll_data.pll_1000 = 0x82000101;
ath79_eth0_pll_data.pll_100 = 0x80000101;
ath79_eth0_pll_data.pll_10 = 0x80001313;
ath79_register_eth(0);
/* GMAC1 is connected to MDIO1 in SGMII mode */
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII;
ath79_eth1_data.mii_bus_dev = &ath79_mdio1_device.dev;
ath79_eth1_data.phy_mask = BIT(1);
ath79_eth1_pll_data.pll_1000 = 0x03000101;
ath79_eth1_pll_data.pll_100 = 0x80000101;
ath79_eth1_pll_data.pll_10 = 0x80001313;
ath79_eth1_data.speed = SPEED_1000;
ath79_eth1_data.duplex = DUPLEX_FULL;
ath79_register_eth(1);
ath79_register_pci();
}
static void __init tl_mr13u_setup(void)
{
u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000);
/* disable PHY_SWAP and PHY_ADDR_SWAP bits */
ath79_setup_ar933x_phy4_switch(false, false);
ath79_register_m25p80(&tl_mr13u_flash_data);
ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_mr13u_leds_gpio),
tl_mr13u_leds_gpio);
ath79_register_gpio_keys_polled(-1, TL_MR13U_KEYS_POLL_INTERVAL,
ARRAY_SIZE(tl_mr13u_gpio_keys),
tl_mr13u_gpio_keys);
gpio_request_one(TL_MR13U_GPIO_USB_POWER,
GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
"USB power");
ath79_register_usb();
ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0);
ath79_register_mdio(0, 0x0);
ath79_register_eth(0);
ath79_register_wmac(ee, mac);
}
static void __init domino_setup(void)
{
/* ART base address */
u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
/* disable PHY_SWAP and PHY_ADDR_SWAP bits */
ath79_setup_ar933x_phy4_switch(false, false);
/* register flash. */
ath79_register_m25p80(NULL);
/* register gpio LEDs and keys */
ath79_register_leds_gpio(-1, ARRAY_SIZE(domino_leds_gpio),
domino_leds_gpio);
ath79_register_gpio_keys_polled(-1, DOMINO_KEYS_POLL_INTERVAL,
ARRAY_SIZE(domino_gpio_keys),
domino_gpio_keys);
gpio_request_one(DOMINO_GPIO_USB_POWER,
GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
"USB power");
/* enable usb */
ath79_register_usb();
/* register eth0 as WAN, eth1 as LAN */
ath79_init_mac(ath79_eth0_data.mac_addr, art+DOMINO_MAC0_OFFSET, 0);
ath79_init_mac(ath79_eth1_data.mac_addr, art+DOMINO_MAC1_OFFSET, 0);
ath79_register_mdio(0, 0x0);
ath79_register_eth(0);
ath79_register_eth(1);
/* register wireless mac with cal data */
ath79_register_wmac(art + DOMINO_CALDATA_OFFSET, art + DOMINO_WMAC_MAC_OFFSET);
}
static void __init ubnt_unifi_outdoor_plus_setup(void)
{
u8 *mac1 = (u8 *) KSEG1ADDR(0x1fff0000);
u8 *mac2 = (u8 *) KSEG1ADDR(0x1fff0000 + ETH_ALEN);
u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000);
ath79_register_m25p80(NULL);
ath79_register_mdio(0, ~(UBNT_UNIFIOD_PRI_PHYMASK |
UBNT_UNIFIOD_2ND_PHYMASK));
ath79_init_mac(ath79_eth0_data.mac_addr, mac1, 0);
ath79_init_mac(ath79_eth1_data.mac_addr, mac2, 0);
ath79_register_eth(0);
ath79_register_eth(1);
ap91_pci_init(ee, NULL);
ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_unifi_outdoor_plus_leds_gpio),
ubnt_unifi_outdoor_plus_leds_gpio);
ath79_register_gpio_keys_polled(-1, UBNT_XM_KEYS_POLL_INTERVAL,
ARRAY_SIZE(ubnt_xm_gpio_keys),
ubnt_xm_gpio_keys);
}
static void __init wndr4300_setup(void)
{
ath79_register_leds_gpio(-1, ARRAY_SIZE(wndr4300_leds_gpio),
wndr4300_leds_gpio);
ath79_register_gpio_keys_polled(-1, WNDR4300_KEYS_POLL_INTERVAL,
ARRAY_SIZE(wndr4300_gpio_keys),
wndr4300_gpio_keys);
ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0);
mdiobus_register_board_info(wndr4300_mdio0_info,
ARRAY_SIZE(wndr4300_mdio0_info));
ath79_register_mdio(0, 0x0);
/* GMAC0 is connected to an AR8327N switch */
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ath79_eth0_data.phy_mask = BIT(0);
ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
ath79_eth0_pll_data.pll_1000 = 0x06000000;
ath79_register_eth(0);
ath79_nfc_set_ecc_mode(AR934X_NFC_ECC_HW);
ath79_register_nfc();
ath79_register_usb();
ath79_register_wmac_simple();
ap91_pci_init_simple();
}
static void __init tl_wr1041nv2_setup(void)
{
u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000);
ath79_register_m25p80(&tl_wr1041nv2_flash_data);
ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wr1041nv2_leds_gpio),
tl_wr1041nv2_leds_gpio);
ath79_register_gpio_keys_polled(-1, TL_WR1041NV2_KEYS_POLL_INTERVAL,
ARRAY_SIZE(tl_wr1041nv2_gpio_keys),
tl_wr1041nv2_gpio_keys);
ath79_register_wmac(ee, mac);
ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0 |
AR934X_ETH_CFG_SW_ONLY_MODE);
ath79_register_mdio(1, 0x0);
ath79_register_mdio(0, 0x0);
ath79_init_mac(ath79_eth0_data.mac_addr, mac, 1);
mdiobus_register_board_info(db120_mdio0_info,
ARRAY_SIZE(db120_mdio0_info));
/* GMAC0 is connected to an AR8327 switch */
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ath79_eth0_data.phy_mask = BIT(0);
ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
ath79_eth0_pll_data.pll_1000 = 0x06000000;
ath79_register_eth(0);
ath79_register_usb();
}
static void __init gl_ar150_setup(void)
{
/* ART base address */
u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
/* disable PHY_SWAP and PHY_ADDR_SWAP bits */
ath79_setup_ar933x_phy4_switch(false, false);
/* register flash. */
ath79_register_m25p80(NULL);
/* register gpio LEDs and keys */
ath79_register_leds_gpio(-1, ARRAY_SIZE(gl_ar150_leds_gpio),
gl_ar150_leds_gpio);
ath79_register_gpio_keys_polled(-1, GL_AR150_KEYS_POLL_INTERVAL,
ARRAY_SIZE(gl_ar150_gpio_keys),
gl_ar150_gpio_keys);
/* enable usb */
ath79_register_usb();
/* register eth0 as WAN, eth1 as LAN */
ath79_init_mac(ath79_eth0_data.mac_addr, art+GL_AR150_MAC0_OFFSET, 0);
ath79_init_mac(ath79_eth1_data.mac_addr, art+GL_AR150_MAC1_OFFSET, 0);
ath79_register_mdio(0, 0x0);
ath79_register_eth(0);
ath79_register_eth(1);
/* register wireless mac with cal data */
ath79_register_wmac(art + GL_AR150_CALDATA_OFFSET, art + GL_AR150_WMAC_MAC_OFFSET);
}
static void __init ja76pf_init(void)
{
ath79_register_m25p80(&ja76pf_flash_data);
ath79_register_mdio(0, ~JA76PF_MDIO_PHYMASK);
ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0);
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ath79_eth0_data.phy_mask = JA76PF_LAN_PHYMASK;
ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 1);
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ath79_eth1_data.phy_mask = JA76PF_WAN_PHYMASK;
ath79_eth1_data.speed = SPEED_1000;
ath79_eth1_data.duplex = DUPLEX_FULL;
ath79_register_eth(0);
ath79_register_eth(1);
platform_device_register(&ja76pf_i2c_gpio_device);
ath79_register_leds_gpio(-1, ARRAY_SIZE(ja76pf_leds_gpio),
ja76pf_leds_gpio);
ath79_register_gpio_keys_polled(-1, JA76PF_KEYS_POLL_INTERVAL,
ARRAY_SIZE(ja76pf_gpio_keys),
ja76pf_gpio_keys);
ath79_register_usb();
ath79_register_pci();
}
static void __init ja76pf2_init(void)
{
ath79_register_m25p80(&ja76pf_flash_data);
ath79_register_mdio(0, ~JA76PF2_MDIO_PHYMASK);
/* MAC0 is connected to the CPU port of the AR8316 switch */
ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0);
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ath79_eth0_data.phy_mask = BIT(0);
/* MAC1 is connected to the PHY4 of the AR8316 switch */
ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 1);
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ath79_eth1_data.phy_mask = BIT(4);
ath79_register_eth(0);
ath79_register_eth(1);
ath79_register_leds_gpio(-1, ARRAY_SIZE(ja76pf2_leds_gpio),
ja76pf2_leds_gpio);
ath79_register_gpio_keys_polled(-1, JA76PF_KEYS_POLL_INTERVAL,
ARRAY_SIZE(ja76pf2_gpio_keys),
ja76pf2_gpio_keys);
ath79_register_pci();
}
static void __init tl_wr1043nd_setup(void)
{
u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
tl_wr1043nd_rtl8366rb_hw_reset(true);
ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0);
ath79_eth0_data.mii_bus_dev = &tl_wr1043nd_rtl8366rb_device.dev;
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ath79_eth0_data.speed = SPEED_1000;
ath79_eth0_data.duplex = DUPLEX_FULL;
ath79_eth0_pll_data.pll_1000 = 0x1a000000;
ath79_register_eth(0);
ath79_register_usb();
ath79_register_m25p80(&tl_wr1043nd_flash_data);
ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wr1043nd_leds_gpio),
tl_wr1043nd_leds_gpio);
platform_device_register(&tl_wr1043nd_rtl8366rb_device);
ath79_register_gpio_keys_polled(-1, TL_WR1043ND_KEYS_POLL_INTERVAL,
ARRAY_SIZE(tl_wr1043nd_gpio_keys),
tl_wr1043nd_gpio_keys);
tplink_register_builtin_wmac1(0x1000, mac, -1);
}
static void __init om2p_setup(void)
{
u8 *mac1 = (u8 *)KSEG1ADDR(0x1ffc0000);
u8 *mac2 = (u8 *)KSEG1ADDR(0x1ffc0000 + ETH_ALEN);
u8 *ee = (u8 *)KSEG1ADDR(0x1ffc1000);
ath79_gpio_function_disable(AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN |
AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN |
AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN |
AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN |
AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN);
ath79_register_m25p80(&om2p_flash_data);
ath79_register_mdio(0, ~OM2P_WAN_PHYMASK);
ath79_init_mac(ath79_eth0_data.mac_addr, mac1, 0);
ath79_init_mac(ath79_eth1_data.mac_addr, mac2, 0);
ath79_register_eth(0);
ath79_register_eth(1);
ap91_pci_init(ee, NULL);
ath79_register_leds_gpio(-1, ARRAY_SIZE(om2p_leds_gpio),
om2p_leds_gpio);
ath79_register_gpio_keys_polled(-1, OM2P_KEYS_POLL_INTERVAL,
ARRAY_SIZE(om2p_gpio_keys),
om2p_gpio_keys);
}
static void __init hornet_ub_setup(void)
{
u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
hornet_ub_gpio_setup();
ath79_register_m25p80(NULL);
ath79_register_leds_gpio(-1, ARRAY_SIZE(hornet_ub_leds_gpio),
hornet_ub_leds_gpio);
ath79_register_gpio_keys_polled(-1, HORNET_UB_KEYS_POLL_INTERVAL,
ARRAY_SIZE(hornet_ub_gpio_keys),
hornet_ub_gpio_keys);
ath79_init_mac(ath79_eth1_data.mac_addr,
art + HORNET_UB_MAC0_OFFSET, 0);
ath79_init_mac(ath79_eth0_data.mac_addr,
art + HORNET_UB_MAC1_OFFSET, 0);
ath79_register_mdio(0, 0x0);
ath79_register_eth(1);
ath79_register_eth(0);
ath79_register_wmac(art + HORNET_UB_CALDATA_OFFSET, NULL);
ath79_register_usb();
}
static void __init dr344_setup(void)
{
u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
u8 *mac = (u8 *) KSEG1ADDR(0x1f03f810);
ath79_register_m25p80(NULL);
ath79_gpio_direction_select(DR344_GPIO_LED_STATUS, true);
gpio_set_value(DR344_GPIO_LED_STATUS, 1);
ath79_gpio_output_select(DR344_GPIO_LED_STATUS, 0);
ath79_gpio_direction_select(DR344_GPIO_LED_LAN, true);
gpio_set_value(DR344_GPIO_LED_LAN, 1);
ath79_gpio_output_select(DR344_GPIO_LED_LAN, 0);
ath79_register_leds_gpio(-1, ARRAY_SIZE(dr344_leds_gpio),
dr344_leds_gpio);
ath79_register_gpio_keys_polled(-1, DR344_KEYS_POLL_INTERVAL,
ARRAY_SIZE(dr344_gpio_keys),
dr344_gpio_keys);
ath79_register_usb();
ath79_wmac_set_ext_lna_gpio(0, DR344_GPIO_EXTERNAL_LNA0);
ath79_wmac_set_ext_lna_gpio(1, DR344_GPIO_EXTERNAL_LNA1);
ath79_register_wmac(art + DR344_WMAC_CALDATA_OFFSET, NULL);
ath79_register_pci();
mdiobus_register_board_info(dr344_mdio0_info,
ARRAY_SIZE(dr344_mdio0_info));
ath79_register_mdio(1, 0x0);
ath79_register_mdio(0, 0x0);
ath79_init_mac(ath79_eth0_data.mac_addr, mac + DR344_MAC0_OFFSET, 0);
ath79_init_mac(ath79_eth1_data.mac_addr, mac + DR344_MAC1_OFFSET, 0);
ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0 |
AR934X_ETH_CFG_SW_ONLY_MODE);
/* GMAC0 is connected to an AR8035 Gbps PHY */
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ath79_eth0_data.phy_mask = BIT(0);
ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
ath79_eth0_pll_data.pll_1000 = 0x02000000;
ath79_eth0_pll_data.pll_100 = 0x0101;
ath79_eth0_pll_data.pll_10 = 0x1313;
/* GMAC1 is connected to the internal switch */
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
ath79_eth1_data.speed = SPEED_1000;
ath79_eth1_data.duplex = DUPLEX_FULL;
ath79_register_eth(0);
ath79_register_eth(1);
}
static void __init ds_setup(void)
{
#ifdef DS2_PREV_RESET_PIN
u32 t;
#endif
ds_common_setup();
ath79_register_leds_gpio(-1, ARRAY_SIZE(ds_leds_gpio),
ds_leds_gpio);
ath79_register_gpio_keys_polled(-1, DS_KEYS_POLL_INTERVAL,
ARRAY_SIZE(ds_gpio_keys),
ds_gpio_keys);
ath79_register_usb();
//Disable the Function for some pins to have GPIO functionality active
// GPIO6-7-8 and GPIO11
ath79_gpio_function_setup(AR933X_GPIO_FUNC_JTAG_DISABLE | AR933X_GPIO_FUNC_I2S_MCK_EN, 0);
ath79_gpio_function2_setup(AR933X_GPIO_FUNC2_JUMPSTART_DISABLE, 0);
printk("Setting DogStick2 GPIO\n");
#ifdef DS2_PREV_RESET_PIN
t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
t |= AR933X_BOOTSTRAP_MDIO_GPIO_EN;
ath79_reset_wr(AR933X_RESET_REG_BOOTSTRAP, t);
// Put the avr reset to high
if (gpio_request_one(DS_GPIO_AVR_RESET_DS2,
GPIOF_OUT_INIT_LOW | GPIOF_EXPORT_DIR_FIXED,
"OE-1") != 0)
printk("Error setting GPIO OE\n");
gpio_unexport(DS_GPIO_AVR_RESET_DS2);
gpio_free(DS_GPIO_AVR_RESET_DS2);
#endif
// enable OE of level shifter
if (gpio_request_one(DS_GPIO_OE,
GPIOF_OUT_INIT_LOW | GPIOF_EXPORT_DIR_FIXED,
"OE-1") != 0)
printk("Error setting GPIO OE\n");
#ifdef DS1
if (gpio_request_one(DS_GPIO_OE2,
GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
"OE-2") != 0)
printk("Error setting GPIO OE2\n");
#else
if (gpio_request_one(DS_GPIO_UART_ENA,
GPIOF_OUT_INIT_LOW | GPIOF_EXPORT_DIR_FIXED,
"UART-ENA") != 0)
printk("Error setting GPIO Uart Enable\n");
// enable OE of level shifter
if (gpio_request_one(DS_GPIO_OE2,
GPIOF_OUT_INIT_LOW | GPIOF_EXPORT_DIR_FIXED,
"OE-2") != 0)
printk("Error setting GPIO OE2\n");
#endif
}
static void __init anonabox_pro_gpio_led_setup(void)
{
ath79_register_leds_gpio(-1, ARRAY_SIZE(anonabox_pro_leds_gpio),
anonabox_pro_leds_gpio);
ath79_register_gpio_keys_polled(-1, ANONABOX_PRO_KEYS_POLL_INTERVAL,
ARRAY_SIZE(anonabox_pro_gpio_keys),
anonabox_pro_gpio_keys);
}
static void __init wrtnode2q_gpio_led_setup(void)
{
ath79_register_leds_gpio(-1, ARRAY_SIZE(wrtnode2q_leds_gpio),
wrtnode2q_leds_gpio);
ath79_register_gpio_keys_polled(-1, WRTNODE2Q_KEYS_POLL_INTERVAL,
ARRAY_SIZE(wrtnode2q_gpio_keys),
wrtnode2q_gpio_keys);
}
static void __init cf_e5x0n_gpio_setup(void)
{
ath79_gpio_direction_select(CF_E5X0N_GPIO_LED_WAN, true);
ath79_gpio_output_select(CF_E5X0N_GPIO_LED_WAN, 0);
ath79_register_gpio_keys_polled(-1, CF_EXXXN_KEYS_POLL_INTERVAL,
ARRAY_SIZE(cf_e320n_v2_gpio_keys),
cf_e320n_v2_gpio_keys);
}
static void __init tl_mr3040_setup(void)
{
common_setup();
ath79_register_gpio_keys_polled(-1, TL_MR11U_KEYS_POLL_INTERVAL,
1, tl_mr11u_gpio_keys);
gpio_request_one(TL_MR3040_GPIO_USB_POWER,
GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
"USB power");
}
static void __init tl_wa901nd_v3_setup(void)
{
tl_ap123_setup();
ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wa801nd_v2_leds_gpio),
tl_wa801nd_v2_leds_gpio);
ath79_register_gpio_keys_polled(-1, TL_WAX50RE_KEYS_POLL_INTERVAL,
ARRAY_SIZE(tl_wax50re_gpio_keys) - 1,
tl_wax50re_gpio_keys);
}
static void __init tl_wr941nd_v5_setup(void)
{
tl_ap123_setup();
ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wr941nd_v5_leds_gpio),
tl_wr941nd_v5_leds_gpio);
ath79_register_gpio_keys_polled(1, TL_WR841NV8_KEYS_POLL_INTERVAL,
ARRAY_SIZE(tl_wr841n_v8_gpio_keys),
tl_wr841n_v8_gpio_keys);
}
static void __init wnr2000v4_setup(void)
{
wnr_common_setup();
ath79_register_leds_gpio(-1, ARRAY_SIZE(wnr2000v4_leds_gpio),
wnr2000v4_leds_gpio);
ath79_register_gpio_keys_polled(-1, WNR2000V4_KEYS_POLL_INTERVAL,
ARRAY_SIZE(wnr2000v4_gpio_keys),
wnr2000v4_gpio_keys);
}
