static void __init tl_wr841n_v8_setup(void)
{
u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000);
ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wr841n_v8_leds_gpio),
tl_wr841n_v8_leds_gpio);
ath79_register_gpio_keys_polled(1, TL_WR841NV8_KEYS_POLL_INTERVAL,
ARRAY_SIZE(tl_wr841n_v8_gpio_keys),
tl_wr841n_v8_gpio_keys);
/* enable power for the USB port */
gpio_request(TL_WR841NV8_GPIO_USB_POWER, "USB power");
gpio_direction_input(TL_WR841NV8_GPIO_USB_POWER);
ath79_register_usb();
/* END for the USB port */
ath79_register_m25p80(&tl_wr841n_v8_flash_data);
ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_PHY_SWAP);
ath79_register_mdio(1, 0x0);
ath79_init_mac(ath79_eth0_data.mac_addr, mac, -1);
ath79_init_mac(ath79_eth1_data.mac_addr, mac, 0);
/* GMAC0 is connected to the PHY0 of the internal switch */
ath79_switch_data.phy4_mii_en = 1;
ath79_switch_data.phy_poll_mask = BIT(0);
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
ath79_eth0_data.phy_mask = BIT(0);
ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev;
ath79_register_eth(0);
/* GMAC1 is connected to the internal switch */
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
ath79_register_eth(1);
ath79_register_wmac(ee, mac);
}
static void __init tl_ap123_setup(void)
{
u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000);
ath79_register_m25p80(&tl_wax50re_flash_data);
ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_PHY_SWAP);
ath79_register_mdio(1, 0x0);
ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0);
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
ath79_eth0_data.phy_mask = BIT(0);
ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev;
ath79_register_eth(0);
ath79_register_wmac(ee, mac);
}
static void __init wa161dd_setup(void)
{
u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
ath79_register_m25p80(&huawei_wa161dd_flash_data);
ath79_register_leds_gpio(-1, ARRAY_SIZE(huawei_wa161dd_leds_gpio),
huawei_wa161dd_leds_gpio);
ath79_register_gpio_keys_polled(-1, HUAWEI_WA161DD_KEYS_POLL_INTERVAL,
ARRAY_SIZE(huawei_wa161dd_gpio_keys),
huawei_wa161dd_gpio_keys);
tplink_register_builtin_wmac1(HUAWEI_WA161DD_WMAC_CALDATA_OFFSET, mac, -1);
tplink_register_ap91_wmac2(HUAWEI_WA161DD_PCIE_CALDATA_OFFSET, mac, 2);
ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0 |
AR934X_ETH_CFG_SW_ONLY_MODE);
ath79_register_mdio(1, 0x0);
ath79_register_mdio(0, 0x0);
ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0);
mdiobus_register_board_info(mi124_mdio0_info,
ARRAY_SIZE(mi124_mdio0_info));
/* GMAC0 is connected to an AR8035 Gigabit PHY */
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ath79_eth0_data.phy_mask = BIT(0);
ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
ath79_eth0_pll_data.pll_1000 = 0x0e000000;
ath79_eth0_pll_data.pll_100 = 0x0101;
ath79_eth0_pll_data.pll_10 = 0x1313;
ath79_register_eth(0);
ath79_register_usb();
gpio_request_one(HUAWEI_WA161DD_GPIO_LED_GREEN_LAN_POLARITY,
GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
"LAN LED Polarity");
}
static void __init smart_300_setup(void)
{
u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000);
ath79_register_leds_gpio(-1, ARRAY_SIZE(smart_300_leds_gpio),
smart_300_leds_gpio);
ath79_register_gpio_keys_polled(1, SMART_300_KEYS_POLL_INTERVAL,
ARRAY_SIZE(smart_300_gpio_keys),
smart_300_gpio_keys);
ath79_register_m25p80(&smart_300_flash_data);
ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_ONLY_MODE);
ath79_register_mdio(1, 0x0);
ath79_init_mac(ath79_eth0_data.mac_addr, mac, -1);
ath79_init_mac(ath79_eth1_data.mac_addr, mac, 1);
/* GMAC0 is connected to the PHY0 of the internal switch */
ath79_switch_data.phy4_mii_en = 1;
ath79_switch_data.phy_poll_mask = BIT(4);
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
ath79_eth0_data.phy_mask = BIT(4);
ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev;
ath79_register_eth(0);
/* GMAC1 is connected to the internal switch */
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
ath79_register_eth(1);
ath79_register_wmac(ee, mac);
gpio_request(SMART_300_GPIO_LED_POWER, "power");
gpio_direction_output(SMART_300_GPIO_LED_POWER, GPIOF_OUT_INIT_LOW);
ath79_register_usb();
}
static void __init dr34x_setup(void)
{
u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
u8 *mac = (u8 *) KSEG1ADDR(0x1f03f810);
ath79_register_m25p80(NULL);
ath79_gpio_direction_select(DR34X_GPIO_LED_STATUS, true);
gpio_set_value(DR34X_GPIO_LED_STATUS, 1);
ath79_gpio_output_select(DR34X_GPIO_LED_STATUS, 0);
ath79_register_gpio_keys_polled(-1, DR344_KEYS_POLL_INTERVAL,
ARRAY_SIZE(dr34x_gpio_keys),
dr34x_gpio_keys);
ath79_register_usb();
ath79_register_wmac(art + DR34X_WMAC_CALDATA_OFFSET, NULL);
ath79_register_pci();
mdiobus_register_board_info(dr34x_mdio0_info,
ARRAY_SIZE(dr34x_mdio0_info));
ath79_register_mdio(0, 0x0);
ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0 |
AR934X_ETH_CFG_SW_ONLY_MODE);
/* GMAC0 is connected to an AR8035 Gbps PHY */
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ath79_eth0_data.phy_mask = BIT(0);
ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
ath79_eth0_pll_data.pll_1000 = 0x02000000;
ath79_eth0_pll_data.pll_100 = 0x0101;
ath79_eth0_pll_data.pll_10 = 0x1313;
ath79_init_mac(ath79_eth0_data.mac_addr, mac + DR34X_MAC0_OFFSET, 0);
ath79_register_eth(0);
}
static void __init dir825c1_generic_setup(void)
{
u8 *mac = (u8 *) KSEG1ADDR(0x1ffe0000);
u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
u8 mac0[ETH_ALEN], mac1[ETH_ALEN];
u8 wmac0[ETH_ALEN], wmac1[ETH_ALEN];
ath79_parse_ascii_mac(mac + DIR825C1_MAC0_OFFSET, mac0);
ath79_parse_ascii_mac(mac + DIR825C1_MAC1_OFFSET, mac1);
ath79_register_m25p80(NULL);
ath79_register_gpio_keys_polled(-1, DIR825C1_KEYS_POLL_INTERVAL,
ARRAY_SIZE(dir825c1_gpio_keys),
dir825c1_gpio_keys);
ath79_init_mac(wmac0, mac0, 0);
ath79_register_wmac(art + DIR825C1_WMAC_CALDATA_OFFSET, wmac0);
ath79_init_mac(wmac1, mac1, 1);
ap91_pci_init(art + DIR825C1_PCIE_CALDATA_OFFSET, wmac1);
ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0);
mdiobus_register_board_info(dir825c1_mdio0_info,
ARRAY_SIZE(dir825c1_mdio0_info));
ath79_register_mdio(0, 0x0);
ath79_init_mac(ath79_eth0_data.mac_addr, mac0, 0);
/* GMAC0 is connected to an AR8327N switch */
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ath79_eth0_data.phy_mask = BIT(0);
ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
ath79_eth0_pll_data.pll_1000 = 0x06000000;
ath79_register_eth(0);
ath79_register_usb();
}
static void __init wndr4300_setup(void)
{
int i;
for (i = 0; i < ARRAY_SIZE(wndr4300_leds_gpio); i++)
ath79_gpio_output_select(wndr4300_leds_gpio[i].gpio,
AR934X_GPIO_OUT_GPIO);
ath79_register_leds_gpio(-1, ARRAY_SIZE(wndr4300_leds_gpio),
wndr4300_leds_gpio);
ath79_register_gpio_keys_polled(-1, WNDR4300_KEYS_POLL_INTERVAL,
ARRAY_SIZE(wndr4300_gpio_keys),
wndr4300_gpio_keys);
ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0);
mdiobus_register_board_info(wndr4300_mdio0_info,
ARRAY_SIZE(wndr4300_mdio0_info));
ath79_register_mdio(0, 0x0);
/* GMAC0 is connected to an AR8327N switch */
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ath79_eth0_data.phy_mask = BIT(0);
ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
ath79_eth0_pll_data.pll_1000 = 0x06000000;
ath79_register_eth(0);
ath79_nfc_set_ecc_mode(AR934X_NFC_ECC_HW);
ath79_register_nfc();
ath79_register_usb();
ath79_register_wmac_simple();
/* enable power for the USB port */
ap9x_pci_setup_wmac_gpio(0, BIT(WNDR4300_GPIO_USB_5V),
BIT(WNDR4300_GPIO_USB_5V));
ap91_pci_init_simple();
}
static void __init wnr_common_setup(void)
{
u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000);
ath79_register_m25p80(NULL);
ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_ONLY_MODE |
AR934X_ETH_CFG_SW_PHY_SWAP);
ath79_register_mdio(1, 0x0);
/* LAN */
ath79_init_mac(ath79_eth1_data.mac_addr, art+WNR2000V4_MAC0_OFFSET, 0);
/* GMAC1 is connected to the internal switch */
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
ath79_register_eth(1);
/* WAN */
ath79_init_mac(ath79_eth0_data.mac_addr, art+WNR2000V4_MAC1_OFFSET, 0);
/* GMAC0 is connected to the PHY0 of the internal switch */
ath79_switch_data.phy4_mii_en = 1;
ath79_switch_data.phy_poll_mask = BIT(4);
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
ath79_eth0_data.phy_mask = BIT(4);
ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev;
ath79_eth0_data.speed = SPEED_100;
ath79_eth0_data.duplex = DUPLEX_FULL;
ath79_register_eth(0);
/* WLAN */
ath79_register_wmac(ee, art+WNR2000V4_MAC0_OFFSET);
/* USB */
ath79_register_usb();
}
static void __init cap4200ag_setup(void)
{
u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
u8 mac[6];
ath79_gpio_output_select(CAP4200AG_GPIO_LED_LAN_GREEN,
AR934X_GPIO_OUT_GPIO);
ath79_gpio_output_select(CAP4200AG_GPIO_LED_LAN_AMBER,
AR934X_GPIO_OUT_GPIO);
ath79_register_m25p80(NULL);
ath79_register_leds_gpio(-1, ARRAY_SIZE(cap4200ag_leds_gpio),
cap4200ag_leds_gpio);
ath79_register_gpio_keys_polled(-1, CAP4200AG_KEYS_POLL_INTERVAL,
ARRAY_SIZE(cap4200ag_gpio_keys),
cap4200ag_gpio_keys);
ath79_init_mac(mac, art + CAP4200AG_MAC_OFFSET, -1);
ath79_wmac_disable_2ghz();
ath79_register_wmac(art + CAP4200AG_WMAC_CALDATA_OFFSET, mac);
ath79_init_mac(mac, art + CAP4200AG_MAC_OFFSET, -2);
ap91_pci_init(art + CAP4200AG_PCIE_CALDATA_OFFSET, mac);
ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0 |
AR934X_ETH_CFG_SW_ONLY_MODE);
ath79_register_mdio(0, 0x0);
ath79_init_mac(ath79_eth0_data.mac_addr,
art + CAP4200AG_MAC_OFFSET, -2);
/* GMAC0 is connected to an external PHY */
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ath79_eth0_data.phy_mask = BIT(0);
ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
ath79_eth0_pll_data.pll_1000 = 0x06000000;
ath79_register_eth(0);
}
static void __init wpj342_setup(void)
{
u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
u8 *mac = (u8 *) KSEG1ADDR(0x1f02e000);
ath79_register_m25p80(NULL);
ath79_register_leds_gpio(-1, ARRAY_SIZE(wpj342_leds_gpio),
wpj342_leds_gpio);
ath79_register_gpio_keys_polled(-1, WPJ342_KEYS_POLL_INTERVAL,
ARRAY_SIZE(wpj342_gpio_keys),
wpj342_gpio_keys);
ath79_register_usb();
ath79_register_wmac(art + WPJ342_WMAC_CALDATA_OFFSET, NULL);
ath79_register_pci();
mdiobus_register_board_info(wpj342_mdio0_info,
ARRAY_SIZE(wpj342_mdio0_info));
ath79_register_mdio(1, 0x0);
ath79_register_mdio(0, 0x0);
ath79_init_mac(ath79_eth0_data.mac_addr, mac + WPJ342_MAC0_OFFSET, 0);
ath79_init_mac(ath79_eth1_data.mac_addr, mac + WPJ342_MAC1_OFFSET, 0);
ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_MII_GMAC0);
/* GMAC0 is connected to an AR8236 switch */
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
ath79_eth0_data.phy_mask = BIT(0);
ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
ath79_eth0_pll_data.pll_1000 = 0x06000000;
ath79_register_eth(0);
}
static void __init cr5000_setup(void)
{
u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
ath79_gpio_function_enable(AR934X_GPIO_FUNC_JTAG_DISABLE);
gpio_request_one(CR5000_GPIO_LED_POWER_ENABLE,
GPIOF_OUT_INIT_LOW, "Power LED enable");
ath79_gpio_output_select(CR5000_GPIO_LED_POWER_AMBER, AR934X_GPIO_OUT_GPIO);
ath79_gpio_output_select(CR5000_GPIO_LED_WLAN_2G, AR934X_GPIO_OUT_GPIO);
ath79_gpio_output_select(CR5000_GPIO_LED_WPS, AR934X_GPIO_OUT_GPIO);
ath79_register_m25p80(NULL);
ath79_register_leds_gpio(-1, ARRAY_SIZE(cr5000_leds_gpio),
cr5000_leds_gpio);
ath79_register_gpio_keys_polled(-1, CR5000_KEYS_POLL_INTERVAL,
ARRAY_SIZE(cr5000_gpio_keys),
cr5000_gpio_keys);
ath79_register_usb();
ath79_register_wmac(art + CR5000_WMAC_CALDATA_OFFSET, art + CR5000_WMAC_MAC_OFFSET);
ap94_pci_init(NULL, NULL, NULL, art + CR5000_PCIE_MAC_OFFSET);
ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0);
ath79_register_mdio(0, 0x0);
ath79_init_mac(ath79_eth0_data.mac_addr, art + CR5000_MAC0_OFFSET, 0);
mdiobus_register_board_info(cr5000_mdio0_info,
ARRAY_SIZE(cr5000_mdio0_info));
/* GMAC0 is connected to an AR8327 switch */
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ath79_eth0_data.phy_mask = BIT(0);
ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
ath79_eth0_pll_data.pll_1000 = 0x06000000;
ath79_register_eth(0);
}
static void __init ubnt_xw_init(void)
{
u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff0000);
ath79_register_m25p80(NULL);
ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_xw_leds_gpio),
ubnt_xw_leds_gpio);
ath79_register_gpio_keys_polled(-1, UBNT_XM_KEYS_POLL_INTERVAL,
ARRAY_SIZE(ubnt_xm_gpio_keys),
ubnt_xm_gpio_keys);
ath79_register_wmac(eeprom + UAP_PRO_WMAC_CALDATA_OFFSET, NULL);
ap91_pci_init(eeprom + UAP_PRO_PCI_CALDATA_OFFSET, NULL);
ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_MII_GMAC0 | AR934X_ETH_CFG_MII_GMAC0_SLAVE);
ath79_init_mac(ath79_eth0_data.mac_addr,
eeprom + UAP_PRO_MAC0_OFFSET, 0);
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
}
static void __init tl_ap123_setup(void)
{
u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000);
/* Disable JTAG, enabling GPIOs 0-3 */
/* Configure OBS4 line, for GPIO 4*/
ath79_gpio_function_setup(AR934X_GPIO_FUNC_JTAG_DISABLE,
AR934X_GPIO_FUNC_CLK_OBS4_EN);
/* config gpio4 as normal gpio function */
ath79_gpio_output_select(TL_MR3420V2_GPIO_USB_POWER,
AR934X_GPIO_OUT_GPIO);
ath79_register_m25p80(&tl_wr841n_v8_flash_data);
ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_PHY_SWAP);
ath79_register_mdio(1, 0x0);
ath79_init_mac(ath79_eth0_data.mac_addr, mac, -1);
ath79_init_mac(ath79_eth1_data.mac_addr, mac, 0);
/* GMAC0 is connected to the PHY0 of the internal switch */
ath79_switch_data.phy4_mii_en = 1;
ath79_switch_data.phy_poll_mask = BIT(0);
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
ath79_eth0_data.phy_mask = BIT(0);
ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev;
ath79_register_eth(0);
/* GMAC1 is connected to the internal switch */
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
ath79_register_eth(1);
ath79_register_wmac(ee, mac);
}
static void __init cf_e316n_v2_setup(void)
{
u8 *mac = (u8 *) KSEG1ADDR(0x1f010000);
cf_exxxn_common_setup(0x10000, CF_E316N_V2_GPIO_EXT_WDT);
ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_PHY_SWAP);
ath79_register_mdio(1, 0x0);
/* GMAC0 is connected to the PHY0 of the internal switch */
ath79_switch_data.phy4_mii_en = 1;
ath79_switch_data.phy_poll_mask = BIT(0);
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
ath79_eth0_data.phy_mask = BIT(0);
ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev;
ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0);
ath79_register_eth(0);
/* GMAC1 is connected to the internal switch */
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
ath79_init_mac(ath79_eth1_data.mac_addr, mac, 2);
ath79_register_eth(1);
/* Enable 2x Skyworks SE2576L WLAN power amplifiers */
gpio_request_one(CF_E316N_V2_GPIO_EXTERNAL_PA0, GPIOF_OUT_INIT_HIGH,
"WLAN PA0");
gpio_request_one(CF_E316N_V2_GPIO_EXTERNAL_PA1, GPIOF_OUT_INIT_HIGH,
"WLAN PA1");
ath79_register_leds_gpio(-1, ARRAY_SIZE(cf_e316n_v2_leds_gpio),
cf_e316n_v2_leds_gpio);
ath79_register_gpio_keys_polled(1, CF_EXXXN_KEYS_POLL_INTERVAL,
ARRAY_SIZE(cf_e316n_v2_gpio_keys),
cf_e316n_v2_gpio_keys);
}
static void __init omy_x1_setup(void)
{
u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000);
ath79_gpio_function_setup(AR934X_GPIO_FUNC_JTAG_DISABLE,
AR934X_GPIO_FUNC_CLK_OBS4_EN);
ath79_register_m25p80(&omy_x1_flash_data);
ath79_register_leds_gpio(-1, ARRAY_SIZE(omy_x1_leds_gpio),
omy_x1_leds_gpio);
ath79_register_gpio_keys_polled(1, OMY_X1_KEYS_POLL_INTERVAL,
ARRAY_SIZE(omy_x1_gpio_keys),
omy_x1_gpio_keys);
ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_PHY_SWAP);
ath79_register_mdio(1, 0x0);
ath79_init_mac(ath79_eth0_data.mac_addr, mac, -1);
ath79_init_mac(ath79_eth1_data.mac_addr, mac, 0);
ath79_switch_data.phy4_mii_en = 1;
ath79_switch_data.phy_poll_mask = BIT(0);
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
ath79_eth0_data.phy_mask = BIT(0);
ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev;
ath79_register_eth(0);
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
ath79_register_eth(1);
ath79_register_wmac(ee, mac);
}
static void __init r6100_setup(void)
{
ath79_register_leds_gpio(-1, ARRAY_SIZE(r6100_leds_gpio),
r6100_leds_gpio);
ath79_register_gpio_keys_polled(-1, R6100_KEYS_POLL_INTERVAL,
ARRAY_SIZE(r6100_gpio_keys),
r6100_gpio_keys);
ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_PHY_SWAP);
ath79_register_mdio(1, 0x0);
/* GMAC0 is connected to the PHY0 of the internal switch */
ath79_switch_data.phy4_mii_en = 1;
ath79_switch_data.phy_poll_mask = BIT(0);
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
ath79_eth0_data.phy_mask = BIT(0);
ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev;
ath79_register_eth(0);
/* GMAC1 is connected to the internal switch */
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
ath79_register_eth(1);
gpio_request_one(R6100_GPIO_USB_POWER,
GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
"USB power");
ath79_nfc_set_ecc_mode(AR934X_NFC_ECC_HW);
ath79_register_nfc();
ath79_register_usb();
ath79_register_wmac_simple();
ap91_pci_init_simple();
}
static void __init om5p_setup(void)
{
u8 *art = (u8 *)KSEG1ADDR(0x1fff0000);
u8 mac[6];
/* make lan / wan leds software controllable */
ath79_gpio_output_select(OM5P_GPIO_LED_LAN, AR934X_GPIO_OUT_GPIO);
ath79_gpio_output_select(OM5P_GPIO_LED_WAN, AR934X_GPIO_OUT_GPIO);
ath79_register_m25p80(&om5p_flash_data);
ath79_register_leds_gpio(-1, ARRAY_SIZE(om5p_leds_gpio),
om5p_leds_gpio);
ath79_register_gpio_keys_polled(-1, OM5P_KEYS_POLL_INTERVAL,
ARRAY_SIZE(om5p_gpio_keys),
om5p_gpio_keys);
ath79_init_mac(mac, art, 2);
ath79_register_wmac(art + OM5P_WMAC_CALDATA_OFFSET, mac);
ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_PHY_SWAP);
ath79_register_mdio(1, 0x0);
ath79_init_mac(ath79_eth0_data.mac_addr, art, 0);
ath79_init_mac(ath79_eth1_data.mac_addr, art, 1);
/* GMAC0 is connected to the PHY0 of the internal switch */
ath79_switch_data.phy4_mii_en = 1;
ath79_switch_data.phy_poll_mask = BIT(0);
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
ath79_eth0_data.phy_mask = BIT(0);
ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev;
ath79_register_eth(0);
/* GMAC1 is connected to the internal switch */
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
ath79_register_eth(1);
}
static void __init rb951g_setup(void)
{
if (rb95x_setup())
return;
ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0 |
AR934X_ETH_CFG_RXD_DELAY |
AR934X_ETH_CFG_SW_ONLY_MODE);
ath79_register_mdio(0, 0x0);
mdiobus_register_board_info(rb95x_mdio0_info,
ARRAY_SIZE(rb95x_mdio0_info));
ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0);
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ath79_eth0_data.phy_mask = BIT(0);
ath79_eth0_pll_data.pll_1000 = 0x3e000000;
ath79_register_eth(0);
rb95x_wlan_init();
ath79_register_usb();
}
static void __init mynet_n600_setup(void)
{
u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
u8 tmpmac[ETH_ALEN];
ath79_register_m25p80(NULL);
ath79_gpio_output_select(MYNET_N600_GPIO_LED_LAN1,
AR934X_GPIO_OUT_GPIO);
ath79_gpio_output_select(MYNET_N600_GPIO_LED_LAN2,
AR934X_GPIO_OUT_GPIO);
ath79_gpio_output_select(MYNET_N600_GPIO_LED_LAN3,
AR934X_GPIO_OUT_GPIO);
ath79_gpio_output_select(MYNET_N600_GPIO_LED_LAN4,
AR934X_GPIO_OUT_GPIO);
ath79_gpio_output_select(MYNET_N600_GPIO_LED_INTERNET,
AR934X_GPIO_OUT_GPIO);
ath79_register_leds_gpio(-1, ARRAY_SIZE(mynet_n600_leds_gpio),
mynet_n600_leds_gpio);
ath79_register_gpio_keys_polled(-1, MYNET_N600_KEYS_POLL_INTERVAL,
ARRAY_SIZE(mynet_n600_gpio_keys),
mynet_n600_gpio_keys);
/*
* Control signal for external LNAs 0 and 1
* Taken from GPL bootloader source:
* board/ar7240/db12x/alpha_gpio.c
*/
ath79_wmac_set_ext_lna_gpio(0, MYNET_N600_GPIO_EXTERNAL_LNA0);
ath79_wmac_set_ext_lna_gpio(1, MYNET_N600_GPIO_EXTERNAL_LNA1);
mynet_n600_get_mac("wlan24mac=", tmpmac);
ath79_register_wmac(art + MYNET_N600_WMAC_CALDATA_OFFSET, tmpmac);
mynet_n600_get_mac("wlan5mac=", tmpmac);
ap91_pci_init(art + MYNET_N600_PCIE_CALDATA_OFFSET, tmpmac);
ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_ONLY_MODE |
AR934X_ETH_CFG_SW_PHY_SWAP);
ath79_register_mdio(1, 0x0);
/* LAN */
mynet_n600_get_mac("lanmac=", ath79_eth1_data.mac_addr);
/* GMAC1 is connected to the internal switch */
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
ath79_register_eth(1);
/* WAN */
mynet_n600_get_mac("wanmac=", ath79_eth0_data.mac_addr);
/* GMAC0 is connected to the PHY4 of the internal switch */
ath79_switch_data.phy4_mii_en = 1;
ath79_switch_data.phy_poll_mask = MYNET_N600_WAN_PHY_MASK;
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
ath79_eth0_data.phy_mask = MYNET_N600_WAN_PHY_MASK;
ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev;
ath79_register_eth(0);
ath79_register_usb();
}
static void __init qihoo_c301_setup(void)
{
ath79_register_m25p80_multi(&flash);
ath79_gpio_function_enable(AR934X_GPIO_FUNC_JTAG_DISABLE);
ath79_gpio_output_select(QIHOO_C301_GPIO_LED_WAN,
AR934X_GPIO_OUT_LED_LINK4);
ath79_gpio_output_select(QIHOO_C301_GPIO_LED_LAN1,
AR934X_GPIO_OUT_LED_LINK1);
ath79_gpio_output_select(QIHOO_C301_GPIO_LED_LAN2,
AR934X_GPIO_OUT_LED_LINK2);
ath79_gpio_output_select(QIHOO_C301_GPIO_SPI_CS1,
AR934X_GPIO_OUT_SPI_CS1);
gpio_request_one(QIHOO_C301_GPIO_ETH_LEN_EN,
GPIOF_OUT_INIT_LOW | GPIOF_EXPORT_DIR_FIXED,
"Ethernet LED enable");
ath79_register_leds_gpio(-1, ARRAY_SIZE(qihoo_c301_leds_gpio),
qihoo_c301_leds_gpio);
ath79_register_gpio_keys_polled(-1, QIHOO_C301_KEYS_POLL_INTERVAL,
ARRAY_SIZE(qihoo_c301_gpio_keys),
qihoo_c301_gpio_keys);
ath79_wmac_set_ext_lna_gpio(0, QIHOO_C301_GPIO_EXTERNAL_LNA0);
ath79_wmac_set_ext_lna_gpio(1, QIHOO_C301_GPIO_EXTERNAL_LNA1);
qihoo_c301_get_mac("wlan24mac=", wlan24mac);
ath79_register_pci();
ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_ONLY_MODE |
AR934X_ETH_CFG_SW_PHY_SWAP);
ath79_register_mdio(1, 0x0);
/* LAN */
qihoo_c301_get_mac("lanmac=", ath79_eth1_data.mac_addr);
/* GMAC1 is connected to the internal switch */
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
ath79_register_eth(1);
/* WAN */
qihoo_c301_get_mac("wanmac=", ath79_eth0_data.mac_addr);
/* GMAC0 is connected to the PHY4 of the internal switch */
ath79_switch_data.phy4_mii_en = 1;
ath79_switch_data.phy_poll_mask = BIT(0);
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
ath79_eth0_data.phy_mask = BIT(0);
ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev;
ath79_register_eth(0);
gpio_request_one(QIHOO_C301_GPIO_USB_POWER,
GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
"USB power");
ath79_register_usb();
qihoo_c301_board = 1;
}
static void __init wr2041n_setup(void)
{
u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
u8 tmpmac[ETH_ALEN];
ath79_register_m25p80(&wr2041n_flash_data);
/* Disable JTAG to enable GPIO 0-4 */
ath79_gpio_function_enable(AR934X_GPIO_FUNC_JTAG_DISABLE);
ath79_register_leds_gpio(-1, ARRAY_SIZE(wr2041n_leds_gpio),
wr2041n_leds_gpio);
ath79_register_gpio_keys_polled(-1, WR2041N_KEYS_POLL_INTERVAL,
ARRAY_SIZE(wr2041n_gpio_keys),
wr2041n_gpio_keys);
ath79_init_mac(tmpmac, mac, 0);
ath79_register_wmac(art + WR2041N_WMAC_CALDATA_OFFSET, tmpmac);
ath79_init_mac(tmpmac, mac, 1);
// try to setup wlan led pin
ath79_wmac_set_led_pin(WR2041N_GPIO_WMAC_LED_WLAN);
ap91_pci_init(art + WR2041N_PCIE_CALDATA_OFFSET, tmpmac);
ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_ONLY_MODE);
ath79_register_mdio(1, 0x0);
/* LAN */
ath79_init_mac(ath79_eth1_data.mac_addr, mac, -1);
/* GMAC1 is connected to the internal switch */
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
ath79_register_eth(1);
/* WAN */
ath79_init_mac(ath79_eth0_data.mac_addr, mac, 2);
/* GMAC0 is connected to the PHY4 of the internal switch */
ath79_switch_data.phy4_mii_en = 1;
ath79_switch_data.phy_poll_mask = BIT(4);
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
ath79_eth0_data.phy_mask = BIT(4);
ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev;
ath79_register_eth(0);
ath79_gpio_output_select(WR2041N_GPIO_LED_WAN,
AR934X_GPIO_OUT_LED_LINK4);
ath79_gpio_output_select(WR2041N_GPIO_LED_LAN1,
AR934X_GPIO_OUT_LED_LINK3);
ath79_gpio_output_select(WR2041N_GPIO_LED_LAN2,
AR934X_GPIO_OUT_LED_LINK2);
ath79_gpio_output_select(WR2041N_GPIO_LED_LAN3,
AR934X_GPIO_OUT_LED_LINK1);
ath79_gpio_output_select(WR2041N_GPIO_LED_LAN4,
AR934X_GPIO_OUT_LED_LINK0);
}
