static int ath9k_tx99_init(struct ath_softc *sc)
{
struct ieee80211_hw *hw = sc->hw;
struct ath_hw *ah = sc->sc_ah;
struct ath_common *common = ath9k_hw_common(ah);
struct ath_tx_control txctl;
int r;
if (test_bit(ATH_OP_INVALID, &common->op_flags)) {
ath_err(common,
"driver is in invalid state unable to use TX99");
return -EINVAL;
}
sc->tx99_skb = ath9k_build_tx99_skb(sc);
if (!sc->tx99_skb)
return -ENOMEM;
memset(&txctl, 0, sizeof(txctl));
txctl.txq = sc->tx.txq_map[IEEE80211_AC_VO];
ath_reset(sc, NULL);
ath9k_ps_wakeup(sc);
ath9k_hw_disable_interrupts(ah);
atomic_set(&ah->intr_ref_cnt, -1);
ath_drain_all_txq(sc);
ath_stoprecv(sc);
sc->tx99_state = true;
ieee80211_stop_queues(hw);
if (sc->tx99_power == MAX_RATE_POWER + 1)
sc->tx99_power = MAX_RATE_POWER;
ath9k_hw_tx99_set_txpower(ah, sc->tx99_power);
r = ath9k_tx99_send(sc, sc->tx99_skb, &txctl);
if (r) {
ath_dbg(common, XMIT, "Failed to xmit TX99 skb\n");
return r;
}
ath_dbg(common, XMIT, "TX99 xmit started using %d ( %ddBm)\n",
sc->tx99_power,
sc->tx99_power / 2);
/* We leave the harware awake as it will be chugging on */
return 0;
}
/*
* Set/change channels. If the channel is really being changed, it's done
* by reseting the chip. To accomplish this we must first cleanup any pending
* DMA, then restart stuff.
*/
static int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
struct ath9k_channel *hchan)
{
struct ath_hw *ah = sc->sc_ah;
struct ath_common *common = ath9k_hw_common(ah);
struct ieee80211_conf *conf = &common->hw->conf;
bool fastcc = true, stopped;
struct ieee80211_channel *channel = hw->conf.channel;
struct ath9k_hw_cal_data *caldata = NULL;
int r;
if (sc->sc_flags & SC_OP_INVALID)
return -EIO;
sc->hw_busy_count = 0;
del_timer_sync(&common->ani.timer);
cancel_work_sync(&sc->paprd_work);
cancel_work_sync(&sc->hw_check_work);
cancel_delayed_work_sync(&sc->tx_complete_work);
cancel_delayed_work_sync(&sc->hw_pll_work);
ath9k_ps_wakeup(sc);
spin_lock_bh(&sc->sc_pcu_lock);
/*
* This is only performed if the channel settings have
* actually changed.
*
* To switch channels clear any pending DMA operations;
* wait long enough for the RX fifo to drain, reset the
* hardware at the new frequency, and then re-enable
* the relevant bits of the h/w.
*/
ath9k_hw_disable_interrupts(ah);
stopped = ath_drain_all_txq(sc, false);
if (!ath_stoprecv(sc))
stopped = false;
if (!ath9k_hw_check_alive(ah))
stopped = false;
/* XXX: do not flush receive queue here. We don't want
* to flush data frames already in queue because of
* changing channel. */
if (!stopped || !(sc->sc_flags & SC_OP_OFFCHANNEL))
fastcc = false;
if (!(sc->sc_flags & SC_OP_OFFCHANNEL))
caldata = &sc->caldata;
ath_dbg(common, ATH_DBG_CONFIG,
"(%u MHz) -> (%u MHz), conf_is_ht40: %d fastcc: %d\n",
sc->sc_ah->curchan->channel,
channel->center_freq, conf_is_ht40(conf),
fastcc);
r = ath9k_hw_reset(ah, hchan, caldata, fastcc);
if (r) {
ath_err(common,
"Unable to reset channel (%u MHz), reset status %d\n",
channel->center_freq, r);
goto ps_restore;
}
if (ath_startrecv(sc) != 0) {
ath_err(common, "Unable to restart recv logic\n");
r = -EIO;
goto ps_restore;
}
ath9k_cmn_update_txpow(ah, sc->curtxpow,
sc->config.txpowlimit, &sc->curtxpow);
ath9k_hw_set_interrupts(ah, ah->imask);
if (!(sc->sc_flags & (SC_OP_OFFCHANNEL))) {
if (sc->sc_flags & SC_OP_BEACONS)
ath_set_beacon(sc);
ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work, HZ/2);
if (!common->disable_ani)
ath_start_ani(common);
}
ps_restore:
ieee80211_wake_queues(hw);
spin_unlock_bh(&sc->sc_pcu_lock);
ath9k_ps_restore(sc);
return r;
}
void ath_cont_data(struct ath_softc *sc ,int val)
{
static struct sk_buff *skb = NULL;
struct ieee80211_frame *hdr;
static struct ieee80211com *ic;
static struct ath_buf *bf,*prev,*first;
static struct ath_desc *ds;
static struct ath_hal *ah;
static STAILQ_HEAD(tpc_buf,ath_buf) tmp_q;
static int is_inited=0;
struct ath_txq *txq;
const HAL_RATE_TABLE *rt;
u_int8_t *p;
u_int32_t flags, txrate, r,i;
u_int16_t hdrlen, framelen, dmalen,delay=0;
#define MIN(a,b) ((a) < (b) ? (a) : (b))
if(is_inited == 0)
{
STAILQ_INIT(&tmp_q);
is_inited=1;
}
/* enter CONT_DATA mode */
if (val && skb==NULL) {
skb = ath_alloc_skb(4096, 32);
if (skb == NULL)
goto out;
/* build output packet */
hdr = (struct ieee80211_frame *)skb_put(skb, sizeof(*hdr));
IEEE80211_ADDR_COPY(&hdr->i_addr1, test_addr);
IEEE80211_ADDR_COPY(&hdr->i_addr2, test_addr);
IEEE80211_ADDR_COPY(&hdr->i_addr3, test_addr);
hdr->i_dur[0] = 0x0;
hdr->i_dur[1] = 0x0;
hdr->i_seq[0] = 0x5a;
hdr->i_seq[1] = 0x5a;
hdr->i_fc[0] = IEEE80211_FC0_TYPE_DATA;
hdr->i_fc[1] = 0;
hdrlen = sizeof(*hdr);
for(r=0; r<2000; ) {
p = skb_put(skb, sizeof(PN9Data));
memcpy(p, PN9Data, sizeof(PN9Data));
r += sizeof(PN9Data);
}
framelen = hdrlen + r + IEEE80211_CRC_LEN;
ic = &sc->sc_ic;
ah = sc->sc_ah;
rt = sc->sc_currates;
if (rt==NULL) {
printk("no rate table\n");
goto out;
}
txrate = rt->info[rt->rateCount-1].rateCode; /* send at highest rate */
{
int rix;
if (sc->sc_txrate==0)
sc->sc_txrate = 6000;
for(rix=0; rix<rt->rateCount; rix++) {
if (rt->info[rix].rateKbps==sc->sc_txrate) {
txrate = rt->info[rix].rateCode;
printk("txrate set to %dKbps\n", sc->sc_txrate);
break;
}
}
}
ath_draintxq(sc);
prev=first=NULL;
/* send 20 frames for the Power Amp to settle down */
for(i=0;i<20;++i)
{
ATH_TXBUF_LOCK_BH(sc);
bf = STAILQ_FIRST(&sc->sc_txbuf);
if (bf != NULL) {
STAILQ_REMOVE_HEAD(&sc->sc_txbuf,bf_list);
}
ATH_TXBUF_UNLOCK_BH(sc);
if (bf==NULL) {
printk("no tx buf\n");
goto out;
}
if(!i) first=bf;
framelen = skb->len + IEEE80211_CRC_LEN;
dmalen = skb->len;
txq = sc->sc_ac2q[WME_AC_VO];
bf->bf_skbaddr = bus_map_single(sc->sc_bdev, skb->data, framelen, BUS_DMA_TODEVICE);
bf->bf_skb = skb;
bf->bf_node = 0;
flags = HAL_TXDESC_CLRDMASK;
ds = bf->bf_desc;
if(prev)
prev->bf_desc->ds_link = bf->bf_daddr; /* link from prev desc */
ds->ds_data = bf->bf_skbaddr;
printk("txpower set to %d\n", sc->sc_txpower);
r = ath_hal_setuptxdesc(ah, ds, framelen, hdrlen,
HAL_PKT_TYPE_NORMAL,
sc->sc_txpower,
txrate, /* tx rate */
15, /* max retries */
HAL_TXKEYIX_INVALID, /* no WEP */
1, /* select Omni Antenna 0 */
flags,
0, /* rts/cts rate */
0 /* rts/cts duration */
);
if (r==AH_FALSE) {
printk("fail setuptxdesc r(%d)\n", r);
goto out;
}
r = ath_hal_filltxdesc(ah, ds, skb->len, AH_TRUE, AH_TRUE,ds);
if (r==AH_FALSE) {
printk("fail fill tx desc r(%d)\n", r);
goto out;
}
ath_hal_setupxtxdesc(ah, ds
, txrate, 15 /* series 1 */
, txrate, 15 /* series 2 */
, txrate, 15 /* series 3 */
);
/* insert the buffers in to tmp_q */
STAILQ_INSERT_HEAD(&tmp_q,bf,bf_list);
#if 0
ATH_TXQ_LOCK_BH(txq);
ATH_TXQ_INSERT_TAIL(txq, bf, bf_list);
ATH_TXQ_UNLOCK_BH(txq);
#endif
prev=bf;
}
ath_hal_intrset(ah, 0); /* disable interrupts */
//sc->sc_imask = HAL_INT_RX | HAL_INT_TX
// | HAL_INT_RXEOL | HAL_INT_RXORN
// | HAL_INT_FATAL | HAL_INT_GLOBAL;
sc->sc_imask = 0;
//ath_hal_intrset(ah, sc->sc_imask);
bf->bf_desc->ds_link = NULL;
r = ath_hal_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
ath_hal_txstart(ah, txq->axq_qnum);
while(ath_hal_txprocdesc(ah,bf->bf_desc) == HAL_EINPROGRESS)
{
udelay(2000);
++delay;
}
/* sleep for 20ms */
udelay(20000);
printk("took %d msec to transmit the 20 frames \n",2*delay);
/* start TX99 mode */
ath_stoprecv(sc); /* stop recv side */
bf->bf_desc->ds_link = first->bf_daddr; /* link to self */
ath_hal_getdiagstate(ah, 19,(void *) sc->sc_prefetch,9,NULL,NULL);
ath_hal_getdiagstate(ah, 19, txq->axq_qnum, val,NULL,NULL);
ath_hal_txstart(ah, txq->axq_qnum);
}
/* leave CONT_DATA mode, reset the chip */
if (val==0 && skb) {
int j=0;
ath_hal_getdiagstate(ah, 19, 0, 0,NULL,NULL);
/* insert the buffers back into txbuf list */
ATH_TXBUF_LOCK_BH(sc);
bf = STAILQ_FIRST(&tmp_q);
while(bf)
{
bf->bf_skb=NULL;
STAILQ_REMOVE_HEAD(&tmp_q,bf_list);
STAILQ_INSERT_HEAD(&sc->sc_txbuf,bf,bf_list);
bf = STAILQ_FIRST(&tmp_q);
++j;
}
ATH_TXBUF_UNLOCK_BH(sc);
printk("inserted back %d buffers \n",j);
ic->ic_reset(ic->ic_dev);
skb = NULL;
bf = NULL;
}
if (val==7 && skb) {
ath_hal_getdiagstate(ah, 19, ds, 7,NULL,NULL);
}
out:
return;
#undef MIN
}
