static void reset_gui(struct atyfb_par *par)
{
aty_st_8(GEN_TEST_CNTL+1, 0x01, par);
aty_st_8(GEN_TEST_CNTL+1, 0x00, par);
aty_st_8(GEN_TEST_CNTL+1, 0x02, par);
mdelay(5);
}
static void aty_set_pll_1703(const struct fb_info *info,
const union aty_pll *pll)
{
struct atyfb_par *par = (struct atyfb_par *) info->par;
u32 program_bits;
u32 locationAddr;
char old_crtc_ext_disp;
old_crtc_ext_disp = aty_ld_8(CRTC_GEN_CNTL + 3, par);
aty_st_8(CRTC_GEN_CNTL + 3,
old_crtc_ext_disp | (CRTC_EXT_DISP_EN >> 24), par);
program_bits = pll->ics2595.program_bits;
locationAddr = pll->ics2595.locationAddr;
/* Program clock */
aty_dac_waste4(par);
(void) aty_ld_8(DAC_REGS + 2, par);
aty_st_8(DAC_REGS + 2, (locationAddr << 1) + 0x20, par);
aty_st_8(DAC_REGS + 2, 0, par);
aty_st_8(DAC_REGS + 2, (program_bits & 0xFF00) >> 8, par);
aty_st_8(DAC_REGS + 2, (program_bits & 0xFF), par);
(void) aty_ld_8(DAC_REGS, par); /* Clear DAC Counter */
aty_st_8(CRTC_GEN_CNTL + 3, old_crtc_ext_disp, par);
return;
}
static void aty_set_pll_8398(const struct fb_info *info,
const union aty_pll *pll)
{
struct atyfb_par *par = (struct atyfb_par *) info->par;
u32 program_bits;
u32 locationAddr;
char old_crtc_ext_disp;
char tmp;
old_crtc_ext_disp = aty_ld_8(CRTC_GEN_CNTL + 3, par);
aty_st_8(CRTC_GEN_CNTL + 3,
old_crtc_ext_disp | (CRTC_EXT_DISP_EN >> 24), par);
program_bits = pll->ics2595.program_bits;
locationAddr = pll->ics2595.locationAddr;
/* Program clock */
tmp = aty_ld_8(DAC_CNTL, par);
aty_st_8(DAC_CNTL, tmp | DAC_EXT_SEL_RS2 | DAC_EXT_SEL_RS3, par);
aty_st_8(DAC_REGS, locationAddr, par);
aty_st_8(DAC_REGS + 1, (program_bits & 0xff00) >> 8, par);
aty_st_8(DAC_REGS + 1, (program_bits & 0xff), par);
tmp = aty_ld_8(DAC_CNTL, par);
aty_st_8(DAC_CNTL, (tmp & ~DAC_EXT_SEL_RS2) | DAC_EXT_SEL_RS3,
par);
(void) aty_ld_8(DAC_REGS, par); /* Clear DAC Counter */
aty_st_8(CRTC_GEN_CNTL + 3, old_crtc_ext_disp, par);
return;
}
static void aty_st_pll_ct(int offset, u8 val, const struct atyfb_par *par)
{
/* write addr byte */
aty_st_8(CLOCK_CNTL_ADDR, ((offset << 2) & PLL_ADDR) | PLL_WR_EN, par);
/* write the register value */
aty_st_8(CLOCK_CNTL_DATA, val & PLL_DATA, par);
aty_st_8(CLOCK_CNTL_ADDR, ((offset << 2) & PLL_ADDR) & ~PLL_WR_EN, par);
}
static void aty_st_514(int offset, u8 val, const struct atyfb_par *par)
{
aty_st_8(DAC_CNTL, 1, par);
/* right addr byte */
aty_st_8(DAC_W_INDEX, offset & 0xff, par);
/* left addr byte */
aty_st_8(DAC_DATA, (offset >> 8) & 0xff, par);
aty_st_8(DAC_MASK, val, par);
aty_st_8(DAC_CNTL, 0, par);
}
static void reset_sdram(struct atyfb_par *par)
{
u8 temp;
temp = aty_ld_8(EXT_MEM_CNTL, par);
temp |= 0x02;
aty_st_8(EXT_MEM_CNTL, temp, par); // MEM_SDRAM_RESET = 1b
temp |= 0x08;
aty_st_8(EXT_MEM_CNTL, temp, par); // MEM_CYC_TEST = 10b
temp |= 0x0c;
aty_st_8(EXT_MEM_CNTL, temp, par); // MEM_CYC_TEST = 11b
mdelay(5);
temp &= 0xf3;
aty_st_8(EXT_MEM_CNTL, temp, par); // MEM_CYC_TEST = 00b
temp &= 0xfd;
aty_st_8(EXT_MEM_CNTL, temp, par); // MEM_SDRAM_REST = 0b
mdelay(5);
}
u8 aty_ld_pll_ct(int offset, const struct atyfb_par *par)
{
u8 res;
/* write addr byte */
aty_st_8(CLOCK_CNTL_ADDR, (offset << 2) & PLL_ADDR, par);
/* read the register value */
res = aty_ld_8(CLOCK_CNTL_DATA, par);
return res;
}
static void aty_StrobeClock(const struct atyfb_par *par)
{
u8 tmp;
udelay(26);
tmp = aty_ld_8(CLOCK_CNTL, par);
aty_st_8(CLOCK_CNTL + par->clk_wr_offset, tmp | CLOCK_STROBE, par);
return;
}
static void reset_clocks(struct atyfb_par *par, struct pll_ct *pll,
int hsync_enb)
{
reset_gui(par);
aty_st_pll(MCLK_FB_DIV, pll->mclk_fb_div, par);
aty_st_pll(SCLK_FB_DIV, pll->sclk_fb_div, par);
mdelay(15);
init_dll(par);
aty_st_8(GEN_TEST_CNTL+1, 0x00, par);
mdelay(5);
aty_st_8(CRTC_GEN_CNTL+3, 0x04, par);
mdelay(6);
reset_sdram(par);
aty_st_8(CRTC_GEN_CNTL+3,
hsync_enb ? 0x00 : 0x04, par);
aty_st_pll(SPLL_CNTL2, pll->spll_cntl2, par);
aty_st_pll(PLL_GEN_CNTL, pll->pll_gen_cntl, par);
aty_st_pll(PLL_VCLK_CNTL, pll->pll_vclk_cntl, par);
}
static void aty_ICS2595_put1bit(u8 data, const struct atyfb_par *par)
{
u8 tmp;
data &= 0x01;
tmp = aty_ld_8(CLOCK_CNTL, par);
aty_st_8(CLOCK_CNTL + par->clk_wr_offset,
(tmp & ~0x04) | (data << 2), par);
tmp = aty_ld_8(CLOCK_CNTL, par);
aty_st_8(CLOCK_CNTL + par->clk_wr_offset, (tmp & ~0x08) | (0 << 3),
par);
aty_StrobeClock(par);
tmp = aty_ld_8(CLOCK_CNTL, par);
aty_st_8(CLOCK_CNTL + par->clk_wr_offset, (tmp & ~0x08) | (1 << 3),
par);
aty_StrobeClock(par);
return;
}
static void aty_set_pll18818(const struct fb_info *info,
const union aty_pll *pll)
{
struct atyfb_par *par = (struct atyfb_par *) info->par;
u32 program_bits;
u32 locationAddr;
u32 i;
u8 old_clock_cntl;
u8 old_crtc_ext_disp;
old_clock_cntl = aty_ld_8(CLOCK_CNTL, par);
aty_st_8(CLOCK_CNTL + par->clk_wr_offset, 0, par);
old_crtc_ext_disp = aty_ld_8(CRTC_GEN_CNTL + 3, par);
aty_st_8(CRTC_GEN_CNTL + 3,
old_crtc_ext_disp | (CRTC_EXT_DISP_EN >> 24), par);
mdelay(15); /* delay for 50 (15) ms */
program_bits = pll->ics2595.program_bits;
locationAddr = pll->ics2595.locationAddr;
/* Program the clock chip */
aty_st_8(CLOCK_CNTL + par->clk_wr_offset, 0, par); /* Strobe = 0 */
aty_StrobeClock(par);
aty_st_8(CLOCK_CNTL + par->clk_wr_offset, 1, par); /* Strobe = 0 */
aty_StrobeClock(par);
aty_ICS2595_put1bit(1, par); /* Send start bits */
aty_ICS2595_put1bit(0, par); /* Start bit */
aty_ICS2595_put1bit(0, par); /* Read / ~Write */
for (i = 0; i < 5; i++) { /* Location 0..4 */
aty_ICS2595_put1bit(locationAddr & 1, par);
locationAddr >>= 1;
}
for (i = 0; i < 8 + 1 + 2 + 2; i++) {
aty_ICS2595_put1bit(program_bits & 1, par);
program_bits >>= 1;
}
mdelay(1); /* delay for 1 ms */
(void) aty_ld_8(DAC_REGS, par); /* Clear DAC Counter */
aty_st_8(CRTC_GEN_CNTL + 3, old_crtc_ext_disp, par);
aty_st_8(CLOCK_CNTL + par->clk_wr_offset,
old_clock_cntl | CLOCK_STROBE, par);
mdelay(50); /* delay for 50 (15) ms */
aty_st_8(CLOCK_CNTL + par->clk_wr_offset,
((pll->ics2595.locationAddr & 0x0F) | CLOCK_STROBE), par);
return;
}
static int aty_set_dac_ATT21C498(const struct fb_info *info,
const union aty_pll *pll, u32 bpp,
u32 accel)
{
struct atyfb_par *par = (struct atyfb_par *) info->par;
u32 dotClock;
int muxmode = 0;
int DACMask = 0;
dotClock = 100000000 / pll->ics2595.period_in_ps;
switch (bpp) {
case 8:
if (dotClock > 8000) {
DACMask = 0x24;
muxmode = 1;
} else
DACMask = 0x04;
break;
case 15:
DACMask = 0x16;
break;
case 16:
DACMask = 0x36;
break;
case 24:
DACMask = 0xE6;
break;
case 32:
DACMask = 0xE6;
break;
}
if (1 /* info->mach64DAC8Bit */ )
DACMask |= 0x02;
aty_dac_waste4(par);
aty_st_8(DAC_REGS + 2, DACMask, par);
aty_st_le32(BUS_CNTL, 0x890e20f1, par);
aty_st_le32(DAC_CNTL, 0x00072000, par);
return muxmode;
}
static inline u32 aty_ld_lcd(u8 lcd_reg, struct atyfb_par *par)
{
aty_st_8(LCD_INDEX, lcd_reg, par);
return aty_ld_le32(LCD_DATA, par);
}
int atyfb_xl_init(struct fb_info *info)
{
const struct xl_card_cfg_t * card = &card_cfg[xl_card];
struct atyfb_par *par = (struct atyfb_par *) info->par;
union aty_pll pll;
int i, err;
u32 temp;
aty_st_8(CONFIG_STAT0, 0x85, par);
mdelay(10);
/*
* The following needs to be set before the call
* to var_to_pll() below. They'll be re-set again
* to the same values in aty_init().
*/
par->ref_clk_per = 100000000UL/card->ref_crystal;
par->ram_type = card->mem_type;
info->fix.smem_len = card->mem_size;
if (xl_card == VICTORIA) {
// the MCLK, XCLK are 120MHz on victoria card
par->mclk_per = 1000000/120;
par->xclk_per = 1000000/120;
par->features &= ~M64F_MFB_TIMES_4;
}
/*
* Calculate mclk and xclk dividers, etc. The passed
* pixclock and bpp values don't matter yet, the vclk
* isn't programmed until later.
*/
if ((err = aty_pll_ct.var_to_pll(info, 39726, 8, &pll)))
return err;
aty_st_pll(LVDS_CNTL0, 0x00, par);
aty_st_pll(DLL2_CNTL, card->dll2_cntl, par);
aty_st_pll(V2PLL_CNTL, 0x10, par);
aty_st_pll(MPLL_CNTL, MPLL_GAIN, par);
aty_st_pll(VPLL_CNTL, VPLL_GAIN, par);
aty_st_pll(PLL_VCLK_CNTL, 0x00, par);
aty_st_pll(VFC_CNTL, 0x1B, par);
aty_st_pll(PLL_REF_DIV, pll.ct.pll_ref_div, par);
aty_st_pll(PLL_EXT_CNTL, pll.ct.pll_ext_cntl, par);
aty_st_pll(SPLL_CNTL2, 0x03, par);
aty_st_pll(PLL_GEN_CNTL, 0x44, par);
reset_clocks(par, &pll.ct, 0);
mdelay(10);
aty_st_pll(VCLK_POST_DIV, 0x03, par);
aty_st_pll(VCLK0_FB_DIV, 0xDA, par);
aty_st_pll(VCLK_POST_DIV, 0x0F, par);
aty_st_pll(VCLK1_FB_DIV, 0xF5, par);
aty_st_pll(VCLK_POST_DIV, 0x3F, par);
aty_st_pll(PLL_EXT_CNTL, 0x40 | pll.ct.pll_ext_cntl, par);
aty_st_pll(VCLK2_FB_DIV, 0x00, par);
aty_st_pll(VCLK_POST_DIV, 0xFF, par);
aty_st_pll(PLL_EXT_CNTL, 0xC0 | pll.ct.pll_ext_cntl, par);
aty_st_pll(VCLK3_FB_DIV, 0x00, par);
aty_st_8(BUS_CNTL, 0x01, par);
aty_st_le32(BUS_CNTL, card->bus_cntl | 0x08000000, par);
aty_st_le32(CRTC_GEN_CNTL, 0x04000200, par);
aty_st_le16(CONFIG_STAT0, 0x0020, par);
aty_st_le32(MEM_CNTL, 0x10151A33, par);
aty_st_le32(EXT_MEM_CNTL, 0xE0000C01, par);
aty_st_le16(CRTC_GEN_CNTL+2, 0x0000, par);
aty_st_le32(DAC_CNTL, card->dac_cntl, par);
aty_st_le16(GEN_TEST_CNTL, 0x0100, par);
aty_st_le32(CUSTOM_MACRO_CNTL, 0x003C0171, par);
aty_st_le32(MEM_BUF_CNTL, 0x00382848, par);
aty_st_le32(HW_DEBUG, card->hw_debug, par);
aty_st_le16(MEM_ADDR_CONFIG, 0x0000, par);
aty_st_le16(GP_IO+2, 0x0000, par);
aty_st_le16(GEN_TEST_CNTL, 0x0000, par);
aty_st_le16(EXT_DAC_REGS+2, 0x0000, par);
aty_st_le32(CRTC_INT_CNTL, 0x00000000, par);
aty_st_le32(TIMER_CONFIG, 0x00000000, par);
aty_st_le32(0xEC, 0x00000000, par);
aty_st_le32(0xFC, 0x00000000, par);
for (i=0; i<sizeof(lcd_tbl)/sizeof(lcd_tbl_t); i++) {
aty_st_lcd(lcd_tbl[i].lcd_reg, lcd_tbl[i].val, par);
}
aty_st_le16(CONFIG_STAT0, 0x00A4, par);
mdelay(10);
aty_st_8(BUS_CNTL+1, 0xA0, par);
mdelay(10);
reset_clocks(par, &pll.ct, 1);
mdelay(10);
// something about power management
aty_st_8(LCD_INDEX, 0x08, par);
aty_st_8(LCD_DATA, 0x0A, par);
aty_st_8(LCD_INDEX, 0x08, par);
aty_st_8(LCD_DATA+3, 0x02, par);
aty_st_8(LCD_INDEX, 0x08, par);
aty_st_8(LCD_DATA, 0x0B, par);
mdelay(2);
// enable display requests, enable CRTC
aty_st_8(CRTC_GEN_CNTL+3, 0x02, par);
// disable display
aty_st_8(CRTC_GEN_CNTL, 0x40, par);
// disable display requests, disable CRTC
aty_st_8(CRTC_GEN_CNTL+3, 0x04, par);
mdelay(10);
aty_st_pll(PLL_YCLK_CNTL, 0x25, par);
aty_st_le16(CUSTOM_MACRO_CNTL, 0x0179, par);
aty_st_le16(CUSTOM_MACRO_CNTL+2, 0x005E, par);
aty_st_le16(CUSTOM_MACRO_CNTL+2, card->custom_macro_cntl>>16, par);
aty_st_8(CUSTOM_MACRO_CNTL+1,
(card->custom_macro_cntl>>8) & 0xff, par);
aty_st_le32(MEM_ADDR_CONFIG, card->mem_addr_config, par);
aty_st_le32(MEM_CNTL, card->mem_cntl, par);
aty_st_le32(EXT_MEM_CNTL, card->ext_mem_cntl, par);
aty_st_8(CONFIG_STAT0, 0xA0 | card->mem_type, par);
aty_st_pll(PLL_YCLK_CNTL, 0x01, par);
mdelay(15);
aty_st_pll(PLL_YCLK_CNTL, card->pll_yclk_cntl, par);
mdelay(1);
reset_clocks(par, &pll.ct, 0);
mdelay(50);
reset_clocks(par, &pll.ct, 0);
mdelay(50);
// enable extended register block
aty_st_8(BUS_CNTL+3, 0x7B, par);
mdelay(1);
// disable extended register block
aty_st_8(BUS_CNTL+3, 0x73, par);
aty_st_8(CONFIG_STAT0, 0x80 | card->mem_type, par);
// disable display requests, disable CRTC
aty_st_8(CRTC_GEN_CNTL+3, 0x04, par);
// disable mapping registers in VGA aperture
aty_st_8(CONFIG_CNTL, aty_ld_8(CONFIG_CNTL, par) & ~0x04, par);
mdelay(50);
// enable display requests, enable CRTC
aty_st_8(CRTC_GEN_CNTL+3, 0x02, par);
// make GPIO's 14,15,16 all inputs
aty_st_8(LCD_INDEX, 0x07, par);
aty_st_8(LCD_DATA+3, 0x00, par);
// enable the display
aty_st_8(CRTC_GEN_CNTL, 0x00, par);
mdelay(17);
// reset the memory controller
aty_st_8(GEN_TEST_CNTL+1, 0x02, par);
mdelay(15);
aty_st_8(GEN_TEST_CNTL+1, 0x00, par);
mdelay(30);
// enable extended register block
aty_st_8(BUS_CNTL+3,
(u8)(aty_ld_8(BUS_CNTL+3, par) | 0x08),
par);
// set FIFO size to 512 (PIO)
aty_st_le32(GUI_CNTL,
aty_ld_le32(GUI_CNTL, par) & ~0x3,
par);
// enable CRT and disable lcd
aty_st_8(LCD_INDEX, 0x01, par);
temp = aty_ld_le32(LCD_DATA, par);
temp = (temp | 0x01) & ~0x02;
aty_st_le32(LCD_DATA, temp, par);
return 0;
}
static void aty_set_pll_408(const struct fb_info *info,
const union aty_pll *pll)
{
struct atyfb_par *par = (struct atyfb_par *) info->par;
u32 program_bits;
u32 locationAddr;
u8 tmpA, tmpB, tmpC;
char old_crtc_ext_disp;
old_crtc_ext_disp = aty_ld_8(CRTC_GEN_CNTL + 3, par);
aty_st_8(CRTC_GEN_CNTL + 3,
old_crtc_ext_disp | (CRTC_EXT_DISP_EN >> 24), par);
program_bits = pll->ics2595.program_bits;
locationAddr = pll->ics2595.locationAddr;
/* Program clock */
aty_dac_waste4(par);
tmpB = aty_ld_8(DAC_REGS + 2, par) | 1;
aty_dac_waste4(par);
aty_st_8(DAC_REGS + 2, tmpB, par);
tmpA = tmpB;
tmpC = tmpA;
tmpA |= 8;
tmpB = 1;
aty_st_8(DAC_REGS, tmpB, par);
aty_st_8(DAC_REGS + 2, tmpA, par);
udelay(400); /* delay for 400 us */
locationAddr = (locationAddr << 2) + 0x40;
tmpB = locationAddr;
tmpA = program_bits >> 8;
aty_st_8(DAC_REGS, tmpB, par);
aty_st_8(DAC_REGS + 2, tmpA, par);
tmpB = locationAddr + 1;
tmpA = (u8) program_bits;
aty_st_8(DAC_REGS, tmpB, par);
aty_st_8(DAC_REGS + 2, tmpA, par);
tmpB = locationAddr + 2;
tmpA = 0x77;
aty_st_8(DAC_REGS, tmpB, par);
aty_st_8(DAC_REGS + 2, tmpA, par);
udelay(400); /* delay for 400 us */
tmpA = tmpC & (~(1 | 8));
tmpB = 1;
aty_st_8(DAC_REGS, tmpB, par);
aty_st_8(DAC_REGS + 2, tmpA, par);
(void) aty_ld_8(DAC_REGS, par); /* Clear DAC Counter */
aty_st_8(CRTC_GEN_CNTL + 3, old_crtc_ext_disp, par);
return;
}
static int aty_set_dac_ATI68860_B(const struct fb_info *info,
const union aty_pll *pll, u32 bpp,
u32 accel)
{
struct atyfb_par *par = (struct atyfb_par *) info->par;
u32 gModeReg, devSetupRegA, temp, mask;
gModeReg = 0;
devSetupRegA = 0;
switch (bpp) {
case 8:
gModeReg = 0x83;
devSetupRegA =
0x60 | 0x00 /*(info->mach64DAC8Bit ? 0x00 : 0x01) */ ;
break;
case 15:
gModeReg = 0xA0;
devSetupRegA = 0x60;
break;
case 16:
gModeReg = 0xA1;
devSetupRegA = 0x60;
break;
case 24:
gModeReg = 0xC0;
devSetupRegA = 0x60;
break;
case 32:
gModeReg = 0xE3;
devSetupRegA = 0x60;
break;
}
if (!accel) {
gModeReg = 0x80;
devSetupRegA = 0x61;
}
temp = aty_ld_8(DAC_CNTL, par);
aty_st_8(DAC_CNTL, (temp & ~DAC_EXT_SEL_RS2) | DAC_EXT_SEL_RS3,
par);
aty_st_8(DAC_REGS + 2, 0x1D, par);
aty_st_8(DAC_REGS + 3, gModeReg, par);
aty_st_8(DAC_REGS, 0x02, par);
temp = aty_ld_8(DAC_CNTL, par);
aty_st_8(DAC_CNTL, temp | DAC_EXT_SEL_RS2 | DAC_EXT_SEL_RS3, par);
if (info->fix.smem_len < ONE_MB)
mask = 0x04;
else if (info->fix.smem_len == ONE_MB)
mask = 0x08;
else
mask = 0x0C;
/* The following assumes that the BIOS has correctly set R7 of the
* Device Setup Register A at boot time.
*/
#define A860_DELAY_L 0x80
temp = aty_ld_8(DAC_REGS, par);
aty_st_8(DAC_REGS, (devSetupRegA | mask) | (temp & A860_DELAY_L),
par);
temp = aty_ld_8(DAC_CNTL, par);
aty_st_8(DAC_CNTL, (temp & ~(DAC_EXT_SEL_RS2 | DAC_EXT_SEL_RS3)),
par);
aty_st_le32(BUS_CNTL, 0x890e20f1, par);
aty_st_le32(DAC_CNTL, 0x47052100, par);
return 0;
}
static inline void aty_st_lcd(u8 lcd_reg, u32 val,
struct atyfb_par *par)
{
aty_st_8(LCD_INDEX, lcd_reg, par);
aty_st_le32(LCD_DATA, val, par);
}