/************************************************************
* Function : clock_init()
* Description :
* - increase fbus clock (1.2V or higher level)
************************************************************/
void clock_init(void)
{
#if defined(AXP192_PMIC)
axp192_init(I2C_CH_MASTER0);
axp192_set_voltage(AXP192_ID_DCDC2, 1250); // CoreA 1200mV
axp192_set_voltage(AXP192_ID_DCDC1, 0); // CoreB Disable
#endif
#if defined(RN5T614_PMIC)
rn5t614_init(I2C_CH_MASTER0);
#if (HW_REV == 0x2004)
rn5t614_set_voltage(RN5T614_ID_DCDC1, 0);
rn5t614_set_power(RN5T614_ID_DCDC1, 0);
#else
rn5t614_set_voltage(RN5T614_ID_DCDC1, 1250);
rn5t614_set_power(RN5T614_ID_DCDC1, 1);
#endif
rn5t614_set_voltage(RN5T614_ID_LDO1, 1800);
rn5t614_set_power(RN5T614_ID_LDO1, 1);
rn5t614_set_voltage(RN5T614_ID_LDO3, 3000);
rn5t614_set_power(RN5T614_ID_LDO3, 1);
rn5t614_set_voltage(RN5T614_ID_LDO5, 3300);
rn5t614_set_power(RN5T614_ID_LDO5, 1);
rn5t614_set_voltage(RN5T614_ID_LDO6, 1200);
rn5t614_set_power(RN5T614_ID_LDO6, 1);
rn5t614_set_voltage(RN5T614_ID_LDO7, 1800);
rn5t614_set_power(RN5T614_ID_LDO7, 1);
#endif
tca_ckc_setfbusctrl( FBUS_CPU, ENABLE, 8000000); /*FBUS_CPU 800 MHz */ // 1.35V
// tca_ckc_setfbusctrl( FBUS_CPU, ENABLE, 6250000); /*FBUS_CPU 625 MHz */ // 1.2V
#if defined(DRAM_DDR3)
tca_ckc_setfbusctrl( FBUS_MEM, ENABLE, 5330000); /*FBUS_MEM 533 MHz */
#else
tca_ckc_setfbusctrl( FBUS_MEM, ENABLE, 3000000); /*FBUS_MEM 300 MHz */
#endif
tca_ckc_setfbusctrl( FBUS_DDI, ENABLE, 3120000); /*FBUS_DDI 312 MHz */
tca_ckc_setfbusctrl( FBUS_GPU, DISABLE, 3700000); /*FBUS_GRP 370 MHz */
tca_ckc_setfbusctrl( FBUS_IO, ENABLE, 1960000); /*FBUS_IOB 196 MHz */
tca_ckc_setfbusctrl( FBUS_VBUS, DISABLE, 2770000); /*FBUS_VBUS 277 MHz */
tca_ckc_setfbusctrl( FBUS_VCORE, DISABLE, 2770000); /*FBUS_VCODEC 277 MHz */
tca_ckc_setfbusctrl( FBUS_HSIO, ENABLE, 2500000); /*FBUS_HSIO 250 MHz */
tca_ckc_setfbusctrl( FBUS_SMU, ENABLE, 1000000); /*FBUS_SMU 196 MHz */
}
void clock_init(void)
{
#if defined(AXP192_PMIC)
axp192_init(I2C_CORE0_CH0);
axp192_set_voltage(AXP192_ID_DCDC2, 1200); // CoreA 1200mV
#endif
tca_ckc_setfbusctrl( CLKCTRL0, ENABLE, 0, 8000000, DIRECTPLL5); /*FBUS_CPU 800 MHz*/ // 1.2V
tca_ckc_setfbusctrl( CLKCTRL1, ENABLE, 0, 2500000, DIRECTPLL1); /*FBUS_DDI 290 MHz*/
tca_ckc_setfbusctrl( CLKCTRL2, ENABLE, 0, 3200000, DIRECTPLL3); /*FBUS_MEM 320 MHz */
tca_ckc_setfbusctrl( CLKCTRL3, DISABLE, 0, 2500000, DIRECTPLL1); /*FBUS_GRP 320 MHz */
tca_ckc_setfbusctrl( CLKCTRL4, ENABLE, 0, 1680000, DIRECTPLL3); /*FBUS_IOB 190 MHz */
tca_ckc_setfbusctrl( CLKCTRL5, DISABLE, 0, 2970000, DIRECTPLL0); /*FBUS_VBUS 300 MHz */
tca_ckc_setfbusctrl( CLKCTRL6, DISABLE, 0, 2500000, DIRECTPLL1); /*FBUS_VCODEC 290 MHz */
tca_ckc_setfbusctrl( CLKCTRL7, ENABLE, 0, 2000000, DIRECTPLL5); /*FBUS_SMU 200 MHz */
tca_ckc_setfbusctrl( CLKCTRL8, ENABLE, 0, 2160000, DIRECTPLL2); /*FBUS_HSIO 240 MHz */
tca_ckc_setfbusctrl( CLKCTRL9, DISABLE, 0, 2970000, DIRECTPLL0); /*CAMBUS 330 MHz */
}