const u8 *get_sr_vlt_table(u32 silicon_type, int freq_id)
{
u32 *vlt_table;
int i;
int ret;
u32 vddvar_adj;
u32 vlt;
u32 vddvar_a9_min = avs_get_vddvar_a9_vlt_min();
u32 vddvar_min = avs_get_vddvar_vlt_min();
u32 min_vlt_table[] = {
INIT_A9_VLT_TABLE(vddvar_a9_min,
vddvar_a9_min, vddvar_a9_min,
vddvar_a9_min, vddvar_a9_min),
INIT_OTHER_VLT_TABLE(vddvar_min, vddvar_min,
vddvar_min, vddvar_min),
INIT_LPM_VLT_IDS(MSR_RETN_VAL, MSR_RETN_VAL, MSR_RETN_VAL),
INIT_UNUSED_VLT_IDS(MSR_RETN_VAL)
};
pr_info("%s silicon_type = %d, freq_id = %d\n", __func__,
silicon_type, freq_id);
if (silicon_type >= SILICON_TYPE_MAX || freq_id >= A9_FREQ_MAX)
BUG();
switch (freq_id) {
case A9_FREQ_1000_MHZ:
vlt_table = pmu_vlt_table_1g[silicon_type];
vddvar_adj = DEFAULT_AGING_MARGIN_1G;
break;
case A9_FREQ_1200_MHZ:
vlt_table = pmu_vlt_table_1200m[silicon_type];
vddvar_adj = DEFAULT_AGING_MARGIN_1200M;
break;
case A9_FREQ_1500_MHZ:
/* Right now 1.5Ghz table hasn't been defined */
default:
BUG();
}
ret = avs_get_vddvar_aging_margin(silicon_type, freq_id);
if (ret >= 0)
vddvar_adj = (u32)ret;
for (i = 0; i < ACTIVE_VOLTAGE_OFFSET; i++)
vlt_id_table[i] = bcmpmu_rgltr_get_volt_id(vlt_table[i]);
for (i = ACTIVE_VOLTAGE_OFFSET; i < SR_VLT_LUT_SIZE; i++) {
vlt = vlt_table[i] + vddvar_adj;
vlt_id_table[i] = bcmpmu_rgltr_get_volt_id(max(vlt,
min_vlt_table[i]));
}
return vlt_id_table;
}
int get_vddvar_retn_vlt_id(void)
{
u32 ret_vlt = MSR_RETN_VAL;
/* Right now the retn value is same for all the silicon types
In case tomorrow if it changes, we will modify the retn value
returned accordingly
*/
#ifdef CONFIG_KONA_AVS
u32 min = avs_get_vddvar_ret_vlt_min();
u32 silicon_type = avs_get_silicon_type();
switch (silicon_type) {
case SILICON_TYPE_SLOW:
ret_vlt = max(ret_vlt, min);
break;
case SILICON_TYPE_TYP_SLOW:
ret_vlt = max(ret_vlt, min);
break;
case SILICON_TYPE_TYPICAL:
ret_vlt = max(ret_vlt, min);
break;
case SILICON_TYPE_TYP_FAST:
ret_vlt = max(ret_vlt, min);
break;
case SILICON_TYPE_FAST:
ret_vlt = max(ret_vlt, min);
break;
default:
BUG();
}
#endif
pr_info("MSR retention_voltage: %umV\n", ret_vlt);
return bcmpmu_rgltr_get_volt_id(ret_vlt);
}
int get_vddfix_vlt_adj(u32 vddfix_vlt)
{
int voltage = bcmpmu_rgltr_get_volt_val(vddfix_vlt);
int adj_val, silicon_type = SILICON_TYPE_SLOW;
u32 ddr_freq, ddr_freq_id;
/* Convert uV to mV */
voltage = voltage/1000;
ddr_freq = kona_memc_get_ddr_clk_freq();
if (ddr_freq < 400000000)
ddr_freq_id = DDR_FREQ_400M;
else
ddr_freq_id = DDR_FREQ_450M;
#ifdef CONFIG_KONA_AVS
adj_val = avs_get_vddfix_adj(ddr_freq_id);
if (adj_val == 0) {
if (ddr_freq_id == DDR_FREQ_450M) {
silicon_type = avs_get_silicon_type();
voltage = sdsr1_active_voltage_450m[silicon_type];
} else
voltage = DEFAULT_VDDFIX_VOLTAGE;
} else
voltage = DEFAULT_VDDFIX_VOLTAGE + adj_val;
#else
if (ddr_freq_id == DDR_FREQ_450M)
voltage = sdsr1_active_voltage_450m[silicon_type];
else
voltage = DEFAULT_VDDFIX_VOLTAGE;
#endif
pr_info("SDSR1 active voltage: %dmV\n", voltage);
return bcmpmu_rgltr_get_volt_id(voltage);
}
u8 *get_sr_vlt_table(u32 silicon_type, int freq_id)
{
u32 *vlt_table;
int i;
u32 vlt_adj, temp;
pr_info("%s silicon_type = %d, freq_id = %d\n", __func__,
silicon_type, freq_id);
if (silicon_type > SILICON_TYPE_MAX || freq_id > A9_FREQ_MAX)
BUG();
switch (freq_id) {
case A9_FREQ_1000_MHZ:
vlt_table = pmu_vlt_table_1g[silicon_type];
vlt_adj = DEFAULT_AGING_MARGIN_1G;
break;
case A9_FREQ_1200_MHZ:
vlt_table = pmu_vlt_table_1200m[silicon_type];
vlt_adj = DEFAULT_AGING_MARGIN_1200M;
break;
case A9_FREQ_1400_MHZ:
default:
BUG();
}
for (i = 0; i < SR_VLT_LUT_SIZE; i++) {
temp = vlt_table[i] + vlt_adj;
vlt_id_table[i] = bcmpmu_rgltr_get_volt_id(temp);
volt_dbg_log.pwr_mgr_volt_tbl[i] = vlt_id_table[i];
}
volt_dbg_log.si_type = silicon_type;
return vlt_id_table;
}
int get_vddfix_vlt_adj(u32 vddfix_vlt)
{
int voltage = bcmpmu_rgltr_get_volt_val(vddfix_vlt);
/* Convert uV to mV */
voltage = voltage/1000;
#ifdef CONFIG_KONA_AVS
voltage += avs_get_vddfix_adj();
#endif
pr_info("SDSR1 active voltage: %dmV\n", voltage);
return bcmpmu_rgltr_get_volt_id(voltage);
}
int get_vddfix_retn_vlt_id(u32 reg_val)
{
int vddfix_ret = reg_val;
#ifdef CONFIG_KONA_AVS
u32 vlt = SDSR1_RETN_VAL;
u32 vddfix_min = avs_get_vddfix_ret_vlt_min();
vlt = max(vlt, vddfix_min);
vddfix_ret = bcmpmu_rgltr_get_volt_id(vlt);
pr_info("SDSR1(AVS) min retn voltage: %dmV, curr val: %umV\n",
vlt, bcmpmu_rgltr_get_volt_val(reg_val)/1000);
BUG_ON(vddfix_ret < 0);
#endif
return vddfix_ret;
}
const u8 *get_sr_vlt_table(u32 silicon_type, int freq_id)
{
u32 *vlt_table;
int i;
pr_info("%s silicon_type = %d, freq_id = %d\n", __func__,
silicon_type, freq_id);
if (silicon_type > SILICON_TYPE_MAX || freq_id > A9_FREQ_MAX)
BUG();
switch (freq_id) {
case A9_FREQ_1000_MHZ:
vlt_table = pmu_vlt_table_1g[silicon_type];
break;
case A9_FREQ_1200_MHZ:
vlt_table = pmu_vlt_table_1200m[silicon_type];
break;
case A9_FREQ_1500_MHZ:
default:
BUG();
}
for (i = 0; i < SR_VLT_LUT_SIZE; i++)
vlt_id_table[i] = bcmpmu_rgltr_get_volt_id(vlt_table[i]);
return vlt_id_table;
}
