static int mii_probe(struct net_device *dev, int phy_mode) { struct bfin_mac_local *lp = netdev_priv(dev); struct phy_device *phydev; unsigned short sysctl; u32 sclk, mdc_div; /* Enable PHY output early */ if (!(bfin_read_VR_CTL() & CLKBUFOE)) bfin_write_VR_CTL(bfin_read_VR_CTL() | CLKBUFOE); sclk = get_sclk(); mdc_div = ((sclk / MDC_CLK) / 2) - 1; sysctl = bfin_read_EMAC_SYSCTL(); sysctl = (sysctl & ~MDCDIV) | SET_MDCDIV(mdc_div); bfin_write_EMAC_SYSCTL(sysctl); phydev = phy_find_first(lp->mii_bus); if (!phydev) { netdev_err(dev, "no phy device found\n"); return -ENODEV; } if (phy_mode != PHY_INTERFACE_MODE_RMII && phy_mode != PHY_INTERFACE_MODE_MII) { netdev_err(dev, "invalid phy interface mode\n"); return -EINVAL; } phydev = phy_connect(dev, phydev_name(phydev), &bfin_mac_adjust_link, phy_mode); if (IS_ERR(phydev)) { netdev_err(dev, "could not attach PHY\n"); return PTR_ERR(phydev); } /* mask with MAC supported features */ phydev->supported &= (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full | SUPPORTED_Autoneg | SUPPORTED_Pause | SUPPORTED_Asym_Pause | SUPPORTED_MII | SUPPORTED_TP); phydev->advertising = phydev->supported; lp->old_link = 0; lp->old_speed = 0; lp->old_duplex = -1; lp->phydev = phydev; phy_attached_print(phydev, "mdc_clk=%dHz(mdc_div=%d)@sclk=%dMHz)\n", MDC_CLK, mdc_div, sclk / 1000000); return 0; }
static int __init net2272_init(void) { #if IS_ENABLED(CONFIG_USB_NET2272) int ret; ret = gpio_request(GPIO_PH15, driver_name); if (ret) return ret; ret = gpio_request(GPIO_PH13, "net2272"); if (ret) { gpio_free(GPIO_PH15); return ret; } /* Set PH15 Low make /AMS2 work properly */ gpio_direction_output(GPIO_PH15, 0); /* enable CLKBUF output */ bfin_write_VR_CTL(bfin_read_VR_CTL() | CLKBUFOE); /* Reset the USB chip */ gpio_direction_output(GPIO_PH13, 0); mdelay(2); gpio_set_value(GPIO_PH13, 1); #endif return 0; }
static int __init net2272_init(void) { #if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE) int ret; ret = gpio_request(GPIO_PH15, driver_name); if (ret) return ret; ret = gpio_request(GPIO_PH13, "net2272"); if (ret) { gpio_free(GPIO_PH15); return ret; } /* */ gpio_direction_output(GPIO_PH15, 0); /* */ bfin_write_VR_CTL(bfin_read_VR_CTL() | CLKBUFOE); /* */ gpio_direction_output(GPIO_PH13, 0); mdelay(2); gpio_set_value(GPIO_PH13, 1); #endif return 0; }
static int bfin_miiphy_init(struct eth_device *dev, int *opmode) { const unsigned short pins[] = CONFIG_BFIN_MAC_PINS; u16 phydat; size_t count; /* Enable PHY output */ bfin_write_VR_CTL(bfin_read_VR_CTL() | CLKBUFOE); /* Set all the pins to peripheral mode */ peripheral_request_list(pins, "bfin_mac"); /* Odd word alignment for Receive Frame DMA word */ /* Configure checksum support and rcve frame word alignment */ bfin_write_EMAC_SYSCTL(RXDWA | RXCKS | SET_MDCDIV(MDC_FREQ_TO_DIV(CONFIG_PHY_CLOCK_FREQ))); /* turn on auto-negotiation and wait for link to come up */ bfin_miiphy_write(dev->name, CONFIG_PHY_ADDR, MII_BMCR, BMCR_ANENABLE); count = 0; while (1) { ++count; if (bfin_miiphy_read(dev->name, CONFIG_PHY_ADDR, MII_BMSR, &phydat)) return -1; if (phydat & BMSR_LSTATUS) break; if (count > 30000) { printf("%s: link down, check cable\n", dev->name); return -1; } udelay(100); } /* see what kind of link we have */ if (bfin_miiphy_read(dev->name, CONFIG_PHY_ADDR, MII_LPA, &phydat)) return -1; if (phydat & LPA_DUPLEX) *opmode = FDMODE; else *opmode = 0; bfin_write_EMAC_MMC_CTL(RSTC | CROLL); /* Initialize the TX DMA channel registers */ bfin_write_DMA2_X_COUNT(0); bfin_write_DMA2_X_MODIFY(4); bfin_write_DMA2_Y_COUNT(0); bfin_write_DMA2_Y_MODIFY(0); /* Initialize the RX DMA channel registers */ bfin_write_DMA1_X_COUNT(0); bfin_write_DMA1_X_MODIFY(4); bfin_write_DMA1_Y_COUNT(0); bfin_write_DMA1_Y_MODIFY(0); return 0; }
static int check_voltage(void) { /* Make sure voltage limits are within datasheet spec */ uint16_t vr_ctl = bfin_read_VR_CTL(); #ifdef __ADSPBF54x__ /* 0.9V <= VDDINT <= 1.1V */ if ((vr_ctl & 0xc) && (vr_ctl & 0xc0) == 0xc0) return 1; #else /* for the parts w/out qualification yet */ (void)vr_ctl; #endif return 0; }
static int mii_probe(struct net_device *dev) { struct bfin_mac_local *lp = netdev_priv(dev); struct phy_device *phydev = NULL; unsigned short sysctl; int i; u32 sclk, mdc_div; /* Enable PHY output early */ if (!(bfin_read_VR_CTL() & PHYCLKOE)) bfin_write_VR_CTL(bfin_read_VR_CTL() | PHYCLKOE); sclk = get_sclk(); mdc_div = ((sclk / MDC_CLK) / 2) - 1; sysctl = bfin_read_EMAC_SYSCTL(); sysctl = (sysctl & ~MDCDIV) | SET_MDCDIV(mdc_div); bfin_write_EMAC_SYSCTL(sysctl); /* search for connect PHY device */ for (i = 0; i < PHY_MAX_ADDR; i++) { struct phy_device *const tmp_phydev = lp->mii_bus->phy_map[i]; if (!tmp_phydev) continue; /* no PHY here... */ phydev = tmp_phydev; break; /* found it */ } /* now we are supposed to have a proper phydev, to attach to... */ if (!phydev) { printk(KERN_INFO "%s: Don't found any phy device at all\n", dev->name); return -ENODEV; } #if defined(CONFIG_BFIN_MAC_RMII) phydev = phy_connect(dev, dev_name(&phydev->dev), &bfin_mac_adjust_link, 0, PHY_INTERFACE_MODE_RMII); #else phydev = phy_connect(dev, dev_name(&phydev->dev), &bfin_mac_adjust_link, 0, PHY_INTERFACE_MODE_MII); #endif if (IS_ERR(phydev)) { printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name); return PTR_ERR(phydev); } /* mask with MAC supported features */ phydev->supported &= (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full | SUPPORTED_Autoneg | SUPPORTED_Pause | SUPPORTED_Asym_Pause | SUPPORTED_MII | SUPPORTED_TP); phydev->advertising = phydev->supported; lp->old_link = 0; lp->old_speed = 0; lp->old_duplex = -1; lp->phydev = phydev; printk(KERN_INFO "%s: attached PHY driver [%s] " "(mii_bus:phy_addr=%s, irq=%d, mdc_clk=%dHz(mdc_div=%d)" "@sclk=%dMHz)\n", DRV_NAME, phydev->drv->name, dev_name(&phydev->dev), phydev->irq, MDC_CLK, mdc_div, sclk/1000000); return 0; }
int do_reginfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { #if defined(CONFIG_8xx) volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; volatile sysconf8xx_t *sysconf = &immap->im_siu_conf; volatile sit8xx_t *timers = &immap->im_sit; /* Hopefully more PowerPC knowledgable people will add code to display * other useful registers */ printf ("\nSystem Configuration registers\n" "\tIMMR\t0x%08X\n", get_immr(0)); printf("\tSIUMCR\t0x%08X", sysconf->sc_siumcr); printf("\tSYPCR\t0x%08X\n",sysconf->sc_sypcr); printf("\tSWT\t0x%08X", sysconf->sc_swt); printf("\tSWSR\t0x%04X\n", sysconf->sc_swsr); printf("\tSIPEND\t0x%08X\tSIMASK\t0x%08X\n", sysconf->sc_sipend, sysconf->sc_simask); printf("\tSIEL\t0x%08X\tSIVEC\t0x%08X\n", sysconf->sc_siel, sysconf->sc_sivec); printf("\tTESR\t0x%08X\tSDCR\t0x%08X\n", sysconf->sc_tesr, sysconf->sc_sdcr); printf ("Memory Controller Registers\n" "\tBR0\t0x%08X\tOR0\t0x%08X \n", memctl->memc_br0, memctl->memc_or0); printf("\tBR1\t0x%08X\tOR1\t0x%08X \n", memctl->memc_br1, memctl->memc_or1); printf("\tBR2\t0x%08X\tOR2\t0x%08X \n", memctl->memc_br2, memctl->memc_or2); printf("\tBR3\t0x%08X\tOR3\t0x%08X \n", memctl->memc_br3, memctl->memc_or3); printf("\tBR4\t0x%08X\tOR4\t0x%08X \n", memctl->memc_br4, memctl->memc_or4); printf("\tBR5\t0x%08X\tOR5\t0x%08X \n", memctl->memc_br5, memctl->memc_or5); printf("\tBR6\t0x%08X\tOR6\t0x%08X \n", memctl->memc_br6, memctl->memc_or6); printf("\tBR7\t0x%08X\tOR7\t0x%08X \n", memctl->memc_br7, memctl->memc_or7); printf ("\n" "\tmamr\t0x%08X\tmbmr\t0x%08X \n", memctl->memc_mamr, memctl->memc_mbmr ); printf("\tmstat\t0x%08X\tmptpr\t0x%08X \n", memctl->memc_mstat, memctl->memc_mptpr ); printf("\tmdr\t0x%08X \n", memctl->memc_mdr); printf ("\nSystem Integration Timers\n" "\tTBSCR\t0x%08X\tRTCSC\t0x%08X \n", timers->sit_tbscr, timers->sit_rtcsc); printf("\tPISCR\t0x%08X \n", timers->sit_piscr); /* * May be some CPM info here? */ #elif defined (CONFIG_405GP) printf ("\n405GP registers; MSR=%08x\n",mfmsr()); printf ("\nUniversal Interrupt Controller Regs\n" "uicsr uicer uiccr uicpr uictr uicmsr uicvr uicvcr" "\n" "%08x %08x %08x %08x %08x %08x %08x %08x\n", mfdcr(uicsr), mfdcr(uicer), mfdcr(uiccr), mfdcr(uicpr), mfdcr(uictr), mfdcr(uicmsr), mfdcr(uicvr), mfdcr(uicvcr)); puts ("\nMemory (SDRAM) Configuration\n" "besra besrsa besrb besrsb bear mcopt1 rtr pmit\n"); mtdcr(memcfga,mem_besra); printf ("%08x ", mfdcr(memcfgd)); mtdcr(memcfga,mem_besrsa); printf ("%08x ", mfdcr(memcfgd)); mtdcr(memcfga,mem_besrb); printf ("%08x ", mfdcr(memcfgd)); mtdcr(memcfga,mem_besrsb); printf ("%08x ", mfdcr(memcfgd)); mtdcr(memcfga,mem_bear); printf ("%08x ", mfdcr(memcfgd)); mtdcr(memcfga,mem_mcopt1); printf ("%08x ", mfdcr(memcfgd)); mtdcr(memcfga,mem_rtr); printf ("%08x ", mfdcr(memcfgd)); mtdcr(memcfga,mem_pmit); printf ("%08x ", mfdcr(memcfgd)); puts ("\n" "mb0cf mb1cf mb2cf mb3cf sdtr1 ecccf eccerr\n"); mtdcr(memcfga,mem_mb0cf); printf ("%08x ", mfdcr(memcfgd)); mtdcr(memcfga,mem_mb1cf); printf ("%08x ", mfdcr(memcfgd)); mtdcr(memcfga,mem_mb2cf); printf ("%08x ", mfdcr(memcfgd)); mtdcr(memcfga,mem_mb3cf); printf ("%08x ", mfdcr(memcfgd)); mtdcr(memcfga,mem_sdtr1); printf ("%08x ", mfdcr(memcfgd)); mtdcr(memcfga,mem_ecccf); printf ("%08x ", mfdcr(memcfgd)); mtdcr(memcfga,mem_eccerr); printf ("%08x ", mfdcr(memcfgd)); printf ("\n\n" "DMA Channels\n" "dmasr dmasgc dmaadr\n" "%08x %08x %08x\n" "dmacr_0 dmact_0 dmada_0 dmasa_0 dmasb_0\n" "%08x %08x %08x %08x %08x\n" "dmacr_1 dmact_1 dmada_1 dmasa_1 dmasb_1\n" "%08x %08x %08x %08x %08x\n", mfdcr(dmasr), mfdcr(dmasgc),mfdcr(dmaadr), mfdcr(dmacr0), mfdcr(dmact0),mfdcr(dmada0), mfdcr(dmasa0), mfdcr(dmasb0), mfdcr(dmacr1), mfdcr(dmact1),mfdcr(dmada1), mfdcr(dmasa1), mfdcr(dmasb1)); printf ( "dmacr_2 dmact_2 dmada_2 dmasa_2 dmasb_2\n" "%08x %08x %08x %08x %08x\n" "dmacr_3 dmact_3 dmada_3 dmasa_3 dmasb_3\n" "%08x %08x %08x %08x %08x\n", mfdcr(dmacr2), mfdcr(dmact2),mfdcr(dmada2), mfdcr(dmasa2), mfdcr(dmasb2), mfdcr(dmacr3), mfdcr(dmact3),mfdcr(dmada3), mfdcr(dmasa3), mfdcr(dmasb3) ); puts ("\n" "External Bus\n" "pbear pbesr0 pbesr1 epcr\n"); mtdcr(ebccfga,pbear); printf ("%08x ", mfdcr(ebccfgd)); mtdcr(ebccfga,pbesr0); printf ("%08x ", mfdcr(ebccfgd)); mtdcr(ebccfga,pbesr1); printf ("%08x ", mfdcr(ebccfgd)); mtdcr(ebccfga,epcr); printf ("%08x ", mfdcr(ebccfgd)); puts ("\n" "pb0cr pb0ap pb1cr pb1ap pb2cr pb2ap pb3cr pb3ap\n"); mtdcr(ebccfga,pb0cr); printf ("%08x ", mfdcr(ebccfgd)); mtdcr(ebccfga,pb0ap); printf ("%08x ", mfdcr(ebccfgd)); mtdcr(ebccfga,pb1cr); printf ("%08x ", mfdcr(ebccfgd)); mtdcr(ebccfga,pb1ap); printf ("%08x ", mfdcr(ebccfgd)); mtdcr(ebccfga,pb2cr); printf ("%08x ", mfdcr(ebccfgd)); mtdcr(ebccfga,pb2ap); printf ("%08x ", mfdcr(ebccfgd)); mtdcr(ebccfga,pb3cr); printf ("%08x ", mfdcr(ebccfgd)); mtdcr(ebccfga,pb3ap); printf ("%08x ", mfdcr(ebccfgd)); puts ("\n" "pb4cr pb4ap pb5cr bp5ap pb6cr pb6ap pb7cr pb7ap\n"); mtdcr(ebccfga,pb4cr); printf ("%08x ", mfdcr(ebccfgd)); mtdcr(ebccfga,pb4ap); printf ("%08x ", mfdcr(ebccfgd)); mtdcr(ebccfga,pb5cr); printf ("%08x ", mfdcr(ebccfgd)); mtdcr(ebccfga,pb5ap); printf ("%08x ", mfdcr(ebccfgd)); mtdcr(ebccfga,pb6cr); printf ("%08x ", mfdcr(ebccfgd)); mtdcr(ebccfga,pb6ap); printf ("%08x ", mfdcr(ebccfgd)); mtdcr(ebccfga,pb7cr); printf ("%08x ", mfdcr(ebccfgd)); mtdcr(ebccfga,pb7ap); printf ("%08x ", mfdcr(ebccfgd)); puts ("\n\n"); #elif defined(CONFIG_405EP) printf ("\n405EP registers; MSR=%08x\n",mfmsr()); printf ("\nUniversal Interrupt Controller Regs\n" "uicsr uicer uiccr uicpr uictr uicmsr uicvr uicvcr" "\n" "%08x %08x %08x %08x %08x %08x %08x %08x\n", mfdcr(uicsr), mfdcr(uicer), mfdcr(uiccr), mfdcr(uicpr), mfdcr(uictr), mfdcr(uicmsr), mfdcr(uicvr), mfdcr(uicvcr)); puts ("\nMemory (SDRAM) Configuration\n" "mcopt1 rtr pmit mb0cf mb1cf sdtr1\n"); mtdcr(memcfga,mem_mcopt1); printf ("%08x ", mfdcr(memcfgd)); mtdcr(memcfga,mem_rtr); printf ("%08x ", mfdcr(memcfgd)); mtdcr(memcfga,mem_pmit); printf ("%08x ", mfdcr(memcfgd)); mtdcr(memcfga,mem_mb0cf); printf ("%08x ", mfdcr(memcfgd)); mtdcr(memcfga,mem_mb1cf); printf ("%08x ", mfdcr(memcfgd)); mtdcr(memcfga,mem_sdtr1); printf ("%08x ", mfdcr(memcfgd)); printf ("\n\n" "DMA Channels\n" "dmasr dmasgc dmaadr\n" "%08x %08x %08x\n" "dmacr_0 dmact_0 dmada_0 dmasa_0 dmasb_0\n" "%08x %08x %08x %08x %08x\n" "dmacr_1 dmact_1 dmada_1 dmasa_1 dmasb_1\n" "%08x %08x %08x %08x %08x\n", mfdcr(dmasr), mfdcr(dmasgc),mfdcr(dmaadr), mfdcr(dmacr0), mfdcr(dmact0),mfdcr(dmada0), mfdcr(dmasa0), mfdcr(dmasb0), mfdcr(dmacr1), mfdcr(dmact1),mfdcr(dmada1), mfdcr(dmasa1), mfdcr(dmasb1)); printf ( "dmacr_2 dmact_2 dmada_2 dmasa_2 dmasb_2\n" "%08x %08x %08x %08x %08x\n" "dmacr_3 dmact_3 dmada_3 dmasa_3 dmasb_3\n" "%08x %08x %08x %08x %08x\n", mfdcr(dmacr2), mfdcr(dmact2),mfdcr(dmada2), mfdcr(dmasa2), mfdcr(dmasb2), mfdcr(dmacr3), mfdcr(dmact3),mfdcr(dmada3), mfdcr(dmasa3), mfdcr(dmasb3) ); puts ("\n" "External Bus\n" "pbear pbesr0 pbesr1 epcr\n"); mtdcr(ebccfga,pbear); printf ("%08x ", mfdcr(ebccfgd)); mtdcr(ebccfga,pbesr0); printf ("%08x ", mfdcr(ebccfgd)); mtdcr(ebccfga,pbesr1); printf ("%08x ", mfdcr(ebccfgd)); mtdcr(ebccfga,epcr); printf ("%08x ", mfdcr(ebccfgd)); puts ("\n" "pb0cr pb0ap pb1cr pb1ap pb2cr pb2ap pb3cr pb3ap\n"); mtdcr(ebccfga,pb0cr); printf ("%08x ", mfdcr(ebccfgd)); mtdcr(ebccfga,pb0ap); printf ("%08x ", mfdcr(ebccfgd)); mtdcr(ebccfga,pb1cr); printf ("%08x ", mfdcr(ebccfgd)); mtdcr(ebccfga,pb1ap); printf ("%08x ", mfdcr(ebccfgd)); mtdcr(ebccfga,pb2cr); printf ("%08x ", mfdcr(ebccfgd)); mtdcr(ebccfga,pb2ap); printf ("%08x ", mfdcr(ebccfgd)); mtdcr(ebccfga,pb3cr); printf ("%08x ", mfdcr(ebccfgd)); mtdcr(ebccfga,pb3ap); printf ("%08x ", mfdcr(ebccfgd)); puts ("\n" "pb4cr pb4ap\n"); mtdcr(ebccfga,pb4cr); printf ("%08x ", mfdcr(ebccfgd)); mtdcr(ebccfga,pb4ap); printf ("%08x ", mfdcr(ebccfgd)); puts ("\n\n"); #elif defined(CONFIG_5xx) volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile memctl5xx_t *memctl = &immap->im_memctl; volatile sysconf5xx_t *sysconf = &immap->im_siu_conf; volatile sit5xx_t *timers = &immap->im_sit; volatile car5xx_t *car = &immap->im_clkrst; volatile uimb5xx_t *uimb = &immap->im_uimb; puts ("\nSystem Configuration registers\n"); printf("\tIMMR\t0x%08X\tSIUMCR\t0x%08X \n", get_immr(0), sysconf->sc_siumcr); printf("\tSYPCR\t0x%08X\tSWSR\t0x%04X \n" ,sysconf->sc_sypcr, sysconf->sc_swsr); printf("\tSIPEND\t0x%08X\tSIMASK\t0x%08X \n", sysconf->sc_sipend, sysconf->sc_simask); printf("\tSIEL\t0x%08X\tSIVEC\t0x%08X \n", sysconf->sc_siel, sysconf->sc_sivec); printf("\tTESR\t0x%08X\n", sysconf->sc_tesr); puts ("\nMemory Controller Registers\n"); printf("\tBR0\t0x%08X\tOR0\t0x%08X \n", memctl->memc_br0, memctl->memc_or0); printf("\tBR1\t0x%08X\tOR1\t0x%08X \n", memctl->memc_br1, memctl->memc_or1); printf("\tBR2\t0x%08X\tOR2\t0x%08X \n", memctl->memc_br2, memctl->memc_or2); printf("\tBR3\t0x%08X\tOR3\t0x%08X \n", memctl->memc_br3, memctl->memc_or3); printf("\tDMBR\t0x%08X\tDMOR\t0x%08X \n", memctl->memc_dmbr, memctl->memc_dmor ); printf("\tMSTAT\t0x%08X\n", memctl->memc_mstat); puts ("\nSystem Integration Timers\n"); printf("\tTBSCR\t0x%08X\tRTCSC\t0x%08X \n", timers->sit_tbscr, timers->sit_rtcsc); printf("\tPISCR\t0x%08X \n", timers->sit_piscr); puts ("\nClocks and Reset\n"); printf("\tSCCR\t0x%08X\tPLPRCR\t0x%08X \n", car->car_sccr, car->car_plprcr); puts ("\nU-Bus to IMB3 Bus Interface\n"); printf("\tUMCR\t0x%08X\tUIPEND\t0x%08X \n", uimb->uimb_umcr, uimb->uimb_uipend); puts ("\n\n"); #elif defined(CONFIG_MPC5200) puts ("\nMPC5200 registers\n"); printf ("MBAR=%08x\n", CONFIG_SYS_MBAR); puts ("Memory map registers\n"); printf ("\tCS0: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n", *(volatile ulong*)MPC5XXX_CS0_START, *(volatile ulong*)MPC5XXX_CS0_STOP, *(volatile ulong*)MPC5XXX_CS0_CFG, (*(volatile ulong*)MPC5XXX_ADDECR & 0x00010000) ? 1 : 0); printf ("\tCS1: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n", *(volatile ulong*)MPC5XXX_CS1_START, *(volatile ulong*)MPC5XXX_CS1_STOP, *(volatile ulong*)MPC5XXX_CS1_CFG, (*(volatile ulong*)MPC5XXX_ADDECR & 0x00020000) ? 1 : 0); printf ("\tCS2: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n", *(volatile ulong*)MPC5XXX_CS2_START, *(volatile ulong*)MPC5XXX_CS2_STOP, *(volatile ulong*)MPC5XXX_CS2_CFG, (*(volatile ulong*)MPC5XXX_ADDECR & 0x00040000) ? 1 : 0); printf ("\tCS3: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n", *(volatile ulong*)MPC5XXX_CS3_START, *(volatile ulong*)MPC5XXX_CS3_STOP, *(volatile ulong*)MPC5XXX_CS3_CFG, (*(volatile ulong*)MPC5XXX_ADDECR & 0x00080000) ? 1 : 0); printf ("\tCS4: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n", *(volatile ulong*)MPC5XXX_CS4_START, *(volatile ulong*)MPC5XXX_CS4_STOP, *(volatile ulong*)MPC5XXX_CS4_CFG, (*(volatile ulong*)MPC5XXX_ADDECR & 0x00100000) ? 1 : 0); printf ("\tCS5: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n", *(volatile ulong*)MPC5XXX_CS5_START, *(volatile ulong*)MPC5XXX_CS5_STOP, *(volatile ulong*)MPC5XXX_CS5_CFG, (*(volatile ulong*)MPC5XXX_ADDECR & 0x00200000) ? 1 : 0); printf ("\tCS6: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n", *(volatile ulong*)MPC5XXX_CS6_START, *(volatile ulong*)MPC5XXX_CS6_STOP, *(volatile ulong*)MPC5XXX_CS6_CFG, (*(volatile ulong*)MPC5XXX_ADDECR & 0x04000000) ? 1 : 0); printf ("\tCS7: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n", *(volatile ulong*)MPC5XXX_CS7_START, *(volatile ulong*)MPC5XXX_CS7_STOP, *(volatile ulong*)MPC5XXX_CS7_CFG, (*(volatile ulong*)MPC5XXX_ADDECR & 0x08000000) ? 1 : 0); printf ("\tBOOTCS: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n", *(volatile ulong*)MPC5XXX_BOOTCS_START, *(volatile ulong*)MPC5XXX_BOOTCS_STOP, *(volatile ulong*)MPC5XXX_BOOTCS_CFG, (*(volatile ulong*)MPC5XXX_ADDECR & 0x02000000) ? 1 : 0); printf ("\tSDRAMCS0: %08lX\n", *(volatile ulong*)MPC5XXX_SDRAM_CS0CFG); printf ("\tSDRAMCS1: %08lX\n", *(volatile ulong*)MPC5XXX_SDRAM_CS1CFG); #elif defined(CONFIG_MPC86xx) mpc86xx_reginfo(); #elif defined(CONFIG_BLACKFIN) puts("\nSystem Configuration registers\n"); puts("\nPLL Registers\n"); printf("\tPLL_DIV: 0x%04x PLL_CTL: 0x%04x\n", bfin_read_PLL_DIV(), bfin_read_PLL_CTL()); printf("\tPLL_STAT: 0x%04x PLL_LOCKCNT: 0x%04x\n", bfin_read_PLL_STAT(), bfin_read_PLL_LOCKCNT()); printf("\tVR_CTL: 0x%04x\n", bfin_read_VR_CTL()); puts("\nEBIU AMC Registers\n"); printf("\tEBIU_AMGCTL: 0x%04x\n", bfin_read_EBIU_AMGCTL()); printf("\tEBIU_AMBCTL0: 0x%08x EBIU_AMBCTL1: 0x%08x\n", bfin_read_EBIU_AMBCTL0(), bfin_read_EBIU_AMBCTL1()); # ifdef EBIU_MODE printf("\tEBIU_MBSCTL: 0x%08x EBIU_ARBSTAT: 0x%08x\n", bfin_read_EBIU_MBSCTL(), bfin_read_EBIU_ARBSTAT()); printf("\tEBIU_MODE: 0x%08x EBIU_FCTL: 0x%08x\n", bfin_read_EBIU_MODE(), bfin_read_EBIU_FCTL()); # endif # ifdef EBIU_RSTCTL puts("\nEBIU DDR Registers\n"); printf("\tEBIU_DDRCTL0: 0x%08x EBIU_DDRCTL1: 0x%08x\n", bfin_read_EBIU_DDRCTL0(), bfin_read_EBIU_DDRCTL1()); printf("\tEBIU_DDRCTL2: 0x%08x EBIU_DDRCTL3: 0x%08x\n", bfin_read_EBIU_DDRCTL2(), bfin_read_EBIU_DDRCTL3()); printf("\tEBIU_DDRQUE: 0x%08x EBIU_RSTCTL 0x%04x\n", bfin_read_EBIU_DDRQUE(), bfin_read_EBIU_RSTCTL()); printf("\tEBIU_ERRADD: 0x%08x EBIU_ERRMST: 0x%04x\n", bfin_read_EBIU_ERRADD(), bfin_read_EBIU_ERRMST()); # else puts("\nEBIU SDC Registers\n"); printf("\tEBIU_SDRRC: 0x%04x EBIU_SDBCTL: 0x%04x\n", bfin_read_EBIU_SDRRC(), bfin_read_EBIU_SDBCTL()); printf("\tEBIU_SDSTAT: 0x%04x EBIU_SDGCTL: 0x%08x\n", bfin_read_EBIU_SDSTAT(), bfin_read_EBIU_SDGCTL()); # endif #endif /* CONFIG_BLACKFIN */ return 0; }
static int mii_probe(struct net_device *dev, int phy_mode) { struct bfin_mac_local *lp = netdev_priv(dev); struct phy_device *phydev = NULL; unsigned short sysctl; int i; u32 sclk, mdc_div; if (!(bfin_read_VR_CTL() & CLKBUFOE)) bfin_write_VR_CTL(bfin_read_VR_CTL() | CLKBUFOE); sclk = get_sclk(); mdc_div = ((sclk / MDC_CLK) / 2) - 1; sysctl = bfin_read_EMAC_SYSCTL(); sysctl = (sysctl & ~MDCDIV) | SET_MDCDIV(mdc_div); bfin_write_EMAC_SYSCTL(sysctl); for (i = 0; i < PHY_MAX_ADDR; ++i) { struct phy_device *const tmp_phydev = lp->mii_bus->phy_map[i]; if (!tmp_phydev) continue; phydev = tmp_phydev; break; } if (!phydev) { netdev_err(dev, "no phy device found\n"); return -ENODEV; } if (phy_mode != PHY_INTERFACE_MODE_RMII && phy_mode != PHY_INTERFACE_MODE_MII) { netdev_err(dev, "invalid phy interface mode\n"); return -EINVAL; } phydev = phy_connect(dev, dev_name(&phydev->dev), &bfin_mac_adjust_link, 0, phy_mode); if (IS_ERR(phydev)) { netdev_err(dev, "could not attach PHY\n"); return PTR_ERR(phydev); } phydev->supported &= (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full | SUPPORTED_Autoneg | SUPPORTED_Pause | SUPPORTED_Asym_Pause | SUPPORTED_MII | SUPPORTED_TP); phydev->advertising = phydev->supported; lp->old_link = 0; lp->old_speed = 0; lp->old_duplex = -1; lp->phydev = phydev; pr_info("attached PHY driver [%s] " "(mii_bus:phy_addr=%s, irq=%d, mdc_clk=%dHz(mdc_div=%d)@sclk=%dMHz)\n", phydev->drv->name, dev_name(&phydev->dev), phydev->irq, MDC_CLK, mdc_div, sclk/1000000); return 0; }
static int do_reginfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { #if defined(CONFIG_8xx) volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; volatile sysconf8xx_t *sysconf = &immap->im_siu_conf; volatile sit8xx_t *timers = &immap->im_sit; /* Hopefully more PowerPC knowledgable people will add code to display * other useful registers */ printf ("\nSystem Configuration registers\n" "\tIMMR\t0x%08X\n", get_immr(0)); printf("\tSIUMCR\t0x%08X", sysconf->sc_siumcr); printf("\tSYPCR\t0x%08X\n",sysconf->sc_sypcr); printf("\tSWT\t0x%08X", sysconf->sc_swt); printf("\tSWSR\t0x%04X\n", sysconf->sc_swsr); printf("\tSIPEND\t0x%08X\tSIMASK\t0x%08X\n", sysconf->sc_sipend, sysconf->sc_simask); printf("\tSIEL\t0x%08X\tSIVEC\t0x%08X\n", sysconf->sc_siel, sysconf->sc_sivec); printf("\tTESR\t0x%08X\tSDCR\t0x%08X\n", sysconf->sc_tesr, sysconf->sc_sdcr); printf ("Memory Controller Registers\n" "\tBR0\t0x%08X\tOR0\t0x%08X \n", memctl->memc_br0, memctl->memc_or0); printf("\tBR1\t0x%08X\tOR1\t0x%08X \n", memctl->memc_br1, memctl->memc_or1); printf("\tBR2\t0x%08X\tOR2\t0x%08X \n", memctl->memc_br2, memctl->memc_or2); printf("\tBR3\t0x%08X\tOR3\t0x%08X \n", memctl->memc_br3, memctl->memc_or3); printf("\tBR4\t0x%08X\tOR4\t0x%08X \n", memctl->memc_br4, memctl->memc_or4); printf("\tBR5\t0x%08X\tOR5\t0x%08X \n", memctl->memc_br5, memctl->memc_or5); printf("\tBR6\t0x%08X\tOR6\t0x%08X \n", memctl->memc_br6, memctl->memc_or6); printf("\tBR7\t0x%08X\tOR7\t0x%08X \n", memctl->memc_br7, memctl->memc_or7); printf ("\n" "\tmamr\t0x%08X\tmbmr\t0x%08X \n", memctl->memc_mamr, memctl->memc_mbmr ); printf("\tmstat\t0x%08X\tmptpr\t0x%08X \n", memctl->memc_mstat, memctl->memc_mptpr ); printf("\tmdr\t0x%08X \n", memctl->memc_mdr); printf ("\nSystem Integration Timers\n" "\tTBSCR\t0x%08X\tRTCSC\t0x%08X \n", timers->sit_tbscr, timers->sit_rtcsc); printf("\tPISCR\t0x%08X \n", timers->sit_piscr); /* * May be some CPM info here? */ #elif defined (CONFIG_4xx) ppc4xx_reginfo(); #elif defined(CONFIG_5xx) volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile memctl5xx_t *memctl = &immap->im_memctl; volatile sysconf5xx_t *sysconf = &immap->im_siu_conf; volatile sit5xx_t *timers = &immap->im_sit; volatile car5xx_t *car = &immap->im_clkrst; volatile uimb5xx_t *uimb = &immap->im_uimb; puts ("\nSystem Configuration registers\n"); printf("\tIMMR\t0x%08X\tSIUMCR\t0x%08X \n", get_immr(0), sysconf->sc_siumcr); printf("\tSYPCR\t0x%08X\tSWSR\t0x%04X \n" ,sysconf->sc_sypcr, sysconf->sc_swsr); printf("\tSIPEND\t0x%08X\tSIMASK\t0x%08X \n", sysconf->sc_sipend, sysconf->sc_simask); printf("\tSIEL\t0x%08X\tSIVEC\t0x%08X \n", sysconf->sc_siel, sysconf->sc_sivec); printf("\tTESR\t0x%08X\n", sysconf->sc_tesr); puts ("\nMemory Controller Registers\n"); printf("\tBR0\t0x%08X\tOR0\t0x%08X \n", memctl->memc_br0, memctl->memc_or0); printf("\tBR1\t0x%08X\tOR1\t0x%08X \n", memctl->memc_br1, memctl->memc_or1); printf("\tBR2\t0x%08X\tOR2\t0x%08X \n", memctl->memc_br2, memctl->memc_or2); printf("\tBR3\t0x%08X\tOR3\t0x%08X \n", memctl->memc_br3, memctl->memc_or3); printf("\tDMBR\t0x%08X\tDMOR\t0x%08X \n", memctl->memc_dmbr, memctl->memc_dmor ); printf("\tMSTAT\t0x%08X\n", memctl->memc_mstat); puts ("\nSystem Integration Timers\n"); printf("\tTBSCR\t0x%08X\tRTCSC\t0x%08X \n", timers->sit_tbscr, timers->sit_rtcsc); printf("\tPISCR\t0x%08X \n", timers->sit_piscr); puts ("\nClocks and Reset\n"); printf("\tSCCR\t0x%08X\tPLPRCR\t0x%08X \n", car->car_sccr, car->car_plprcr); puts ("\nU-Bus to IMB3 Bus Interface\n"); printf("\tUMCR\t0x%08X\tUIPEND\t0x%08X \n", uimb->uimb_umcr, uimb->uimb_uipend); puts ("\n\n"); #elif defined(CONFIG_MPC5200) puts ("\nMPC5200 registers\n"); printf ("MBAR=%08x\n", CONFIG_SYS_MBAR); puts ("Memory map registers\n"); printf ("\tCS0: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n", *(volatile ulong*)MPC5XXX_CS0_START, *(volatile ulong*)MPC5XXX_CS0_STOP, *(volatile ulong*)MPC5XXX_CS0_CFG, (*(volatile ulong*)MPC5XXX_ADDECR & 0x00010000) ? 1 : 0); printf ("\tCS1: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n", *(volatile ulong*)MPC5XXX_CS1_START, *(volatile ulong*)MPC5XXX_CS1_STOP, *(volatile ulong*)MPC5XXX_CS1_CFG, (*(volatile ulong*)MPC5XXX_ADDECR & 0x00020000) ? 1 : 0); printf ("\tCS2: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n", *(volatile ulong*)MPC5XXX_CS2_START, *(volatile ulong*)MPC5XXX_CS2_STOP, *(volatile ulong*)MPC5XXX_CS2_CFG, (*(volatile ulong*)MPC5XXX_ADDECR & 0x00040000) ? 1 : 0); printf ("\tCS3: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n", *(volatile ulong*)MPC5XXX_CS3_START, *(volatile ulong*)MPC5XXX_CS3_STOP, *(volatile ulong*)MPC5XXX_CS3_CFG, (*(volatile ulong*)MPC5XXX_ADDECR & 0x00080000) ? 1 : 0); printf ("\tCS4: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n", *(volatile ulong*)MPC5XXX_CS4_START, *(volatile ulong*)MPC5XXX_CS4_STOP, *(volatile ulong*)MPC5XXX_CS4_CFG, (*(volatile ulong*)MPC5XXX_ADDECR & 0x00100000) ? 1 : 0); printf ("\tCS5: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n", *(volatile ulong*)MPC5XXX_CS5_START, *(volatile ulong*)MPC5XXX_CS5_STOP, *(volatile ulong*)MPC5XXX_CS5_CFG, (*(volatile ulong*)MPC5XXX_ADDECR & 0x00200000) ? 1 : 0); printf ("\tCS6: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n", *(volatile ulong*)MPC5XXX_CS6_START, *(volatile ulong*)MPC5XXX_CS6_STOP, *(volatile ulong*)MPC5XXX_CS6_CFG, (*(volatile ulong*)MPC5XXX_ADDECR & 0x04000000) ? 1 : 0); printf ("\tCS7: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n", *(volatile ulong*)MPC5XXX_CS7_START, *(volatile ulong*)MPC5XXX_CS7_STOP, *(volatile ulong*)MPC5XXX_CS7_CFG, (*(volatile ulong*)MPC5XXX_ADDECR & 0x08000000) ? 1 : 0); printf ("\tBOOTCS: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n", *(volatile ulong*)MPC5XXX_BOOTCS_START, *(volatile ulong*)MPC5XXX_BOOTCS_STOP, *(volatile ulong*)MPC5XXX_BOOTCS_CFG, (*(volatile ulong*)MPC5XXX_ADDECR & 0x02000000) ? 1 : 0); printf ("\tSDRAMCS0: %08lX\n", *(volatile ulong*)MPC5XXX_SDRAM_CS0CFG); printf ("\tSDRAMCS1: %08lX\n", *(volatile ulong*)MPC5XXX_SDRAM_CS1CFG); #elif defined(CONFIG_MPC86xx) mpc86xx_reginfo(); #elif defined(CONFIG_MPC85xx) mpc85xx_reginfo(); #elif defined(CONFIG_BLACKFIN) puts("\nSystem Configuration registers\n"); #ifndef __ADSPBF60x__ puts("\nPLL Registers\n"); printf("\tPLL_DIV: 0x%04x PLL_CTL: 0x%04x\n", bfin_read_PLL_DIV(), bfin_read_PLL_CTL()); printf("\tPLL_STAT: 0x%04x PLL_LOCKCNT: 0x%04x\n", bfin_read_PLL_STAT(), bfin_read_PLL_LOCKCNT()); printf("\tVR_CTL: 0x%04x\n", bfin_read_VR_CTL()); puts("\nEBIU AMC Registers\n"); printf("\tEBIU_AMGCTL: 0x%04x\n", bfin_read_EBIU_AMGCTL()); printf("\tEBIU_AMBCTL0: 0x%08x EBIU_AMBCTL1: 0x%08x\n", bfin_read_EBIU_AMBCTL0(), bfin_read_EBIU_AMBCTL1()); # ifdef EBIU_MODE printf("\tEBIU_MBSCTL: 0x%08x EBIU_ARBSTAT: 0x%08x\n", bfin_read_EBIU_MBSCTL(), bfin_read_EBIU_ARBSTAT()); printf("\tEBIU_MODE: 0x%08x EBIU_FCTL: 0x%08x\n", bfin_read_EBIU_MODE(), bfin_read_EBIU_FCTL()); # endif # ifdef EBIU_RSTCTL puts("\nEBIU DDR Registers\n"); printf("\tEBIU_DDRCTL0: 0x%08x EBIU_DDRCTL1: 0x%08x\n", bfin_read_EBIU_DDRCTL0(), bfin_read_EBIU_DDRCTL1()); printf("\tEBIU_DDRCTL2: 0x%08x EBIU_DDRCTL3: 0x%08x\n", bfin_read_EBIU_DDRCTL2(), bfin_read_EBIU_DDRCTL3()); printf("\tEBIU_DDRQUE: 0x%08x EBIU_RSTCTL 0x%04x\n", bfin_read_EBIU_DDRQUE(), bfin_read_EBIU_RSTCTL()); printf("\tEBIU_ERRADD: 0x%08x EBIU_ERRMST: 0x%04x\n", bfin_read_EBIU_ERRADD(), bfin_read_EBIU_ERRMST()); # else puts("\nEBIU SDC Registers\n"); printf("\tEBIU_SDRRC: 0x%04x EBIU_SDBCTL: 0x%04x\n", bfin_read_EBIU_SDRRC(), bfin_read_EBIU_SDBCTL()); printf("\tEBIU_SDSTAT: 0x%04x EBIU_SDGCTL: 0x%08x\n", bfin_read_EBIU_SDSTAT(), bfin_read_EBIU_SDGCTL()); # endif #else puts("\nCGU Registers\n"); printf("\tCGU_DIV: 0x%08x CGU_CTL: 0x%08x\n", bfin_read_CGU_DIV(), bfin_read_CGU_CTL()); printf("\tCGU_STAT: 0x%08x CGU_LOCKCNT: 0x%08x\n", bfin_read_CGU_STAT(), bfin_read_CGU_CLKOUTSEL()); puts("\nSMC DDR Registers\n"); printf("\tDDR_CFG: 0x%08x DDR_TR0: 0x%08x\n", bfin_read_DMC0_CFG(), bfin_read_DMC0_TR0()); printf("\tDDR_TR1: 0x%08x DDR_TR2: 0x%08x\n", bfin_read_DMC0_TR1(), bfin_read_DMC0_TR2()); printf("\tDDR_MR: 0x%08x DDR_EMR1: 0x%08x\n", bfin_read_DMC0_MR(), bfin_read_DMC0_EMR1()); printf("\tDDR_CTL: 0x%08x DDR_STAT: 0x%08x\n", bfin_read_DMC0_CTL(), bfin_read_DMC0_STAT()); printf("\tDDR_DLLCTL:0x%08x\n", bfin_read_DMC0_DLLCTL()); #endif #endif /* CONFIG_BLACKFIN */ return 0; }
void init_clocks(void) { /* Kill any active DMAs as they may trigger external memory accesses * in the middle of reprogramming things, and that'll screw us up. * For example, any automatic DMAs left by U-Boot for splash screens. */ size_t i; for (i = 0; i < MAX_DMA_CHANNELS; ++i) { struct dma_register *dma = dma_io_base_addr[i]; dma->cfg = 0; } do_sync(); #ifdef SIC_IWR0 bfin_write_SIC_IWR0(IWR_ENABLE(0)); # ifdef SIC_IWR1 /* BF52x system reset does not properly reset SIC_IWR1 which * will screw up the bootrom as it relies on MDMA0/1 waking it * up from IDLE instructions. See this report for more info: * http://blackfin.uclinux.org/gf/tracker/4323 */ if (ANOMALY_05000435) bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11)); else bfin_write_SIC_IWR1(IWR_DISABLE_ALL); # endif # ifdef SIC_IWR2 bfin_write_SIC_IWR2(IWR_DISABLE_ALL); # endif #else bfin_write_SIC_IWR(IWR_ENABLE(0)); #endif do_sync(); #ifdef EBIU_SDGCTL bfin_write_EBIU_SDGCTL(bfin_read_EBIU_SDGCTL() | SRFS); do_sync(); #endif #ifdef CLKBUFOE bfin_write16(VR_CTL, bfin_read_VR_CTL() | CLKBUFOE); do_sync(); __asm__ __volatile__("IDLE;"); #endif bfin_write_PLL_LOCKCNT(0x300); do_sync(); bfin_write16(PLL_CTL, PLL_CTL_VAL); __asm__ __volatile__("IDLE;"); bfin_write_PLL_DIV(CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV); #ifdef EBIU_SDGCTL bfin_write_EBIU_SDRRC(mem_SDRRC); bfin_write_EBIU_SDGCTL((bfin_read_EBIU_SDGCTL() & SDGCTL_WIDTH) | mem_SDGCTL); #else bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() & ~(SRREQ)); do_sync(); bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() | 0x1); bfin_write_EBIU_DDRCTL0(mem_DDRCTL0); bfin_write_EBIU_DDRCTL1(mem_DDRCTL1); bfin_write_EBIU_DDRCTL2(mem_DDRCTL2); #ifdef CONFIG_MEM_EBIU_DDRQUE bfin_write_EBIU_DDRQUE(CONFIG_MEM_EBIU_DDRQUE); #endif #endif do_sync(); bfin_read16(0); }