int bladerf_init_device(struct bladerf *dev) { int status; unsigned int actual; uint32_t val; /* Readback the GPIO values to see if they are default or already set */ status = bladerf_config_gpio_read( dev, &val ); if (status != 0) { log_warning("Failed to read GPIO config, skipping device initialization: %s\n", bladerf_strerror(status)); return 0; } if ((val&0x7f) == 0) { log_verbose( "Default GPIO value found - initializing device\n" ); /* Set the GPIO pins to enable the LMS and select the low band */ bladerf_config_gpio_write( dev, 0x57 ); /* Disable the front ends */ lms_enable_rffe(dev, BLADERF_MODULE_TX, false); lms_enable_rffe(dev, BLADERF_MODULE_RX, false); /* Set the internal LMS register to enable RX and TX */ bladerf_lms_write( dev, 0x05, 0x3e ); /* LMS FAQ: Improve TX spurious emission performance */ bladerf_lms_write( dev, 0x47, 0x40 ); /* LMS FAQ: Improve ADC performance */ bladerf_lms_write( dev, 0x59, 0x29 ); /* LMS FAQ: Common mode voltage for ADC */ bladerf_lms_write( dev, 0x64, 0x36 ); /* LMS FAQ: Higher LNA Gain */ bladerf_lms_write( dev, 0x79, 0x37 ); /* Set a default saplerate */ bladerf_set_sample_rate( dev, BLADERF_MODULE_TX, 1000000, &actual ); bladerf_set_sample_rate( dev, BLADERF_MODULE_RX, 1000000, &actual ); /* Set a default frequency of 1GHz */ bladerf_set_frequency( dev, BLADERF_MODULE_TX, 1000000000 ); bladerf_set_frequency( dev, BLADERF_MODULE_RX, 1000000000 ); /* Set the calibrated VCTCXO DAC value */ bladerf_dac_write( dev, dev->dac_trim ); } /* TODO: Read this return from the SPI calls */ return 0; }
int bladerf_init_device(struct bladerf *dev) { unsigned int actual; uint32_t val; /* Readback the GPIO values to see if they are default or already set */ bladerf_config_gpio_read( dev, &val ); if (val == 0) { log_verbose( "Default GPIO value found - initializing device\n" ); /* Set the GPIO pins to enable the LMS and select the low band */ bladerf_config_gpio_write( dev, 0x57 ); /* Set the internal LMS register to enable RX and TX */ bladerf_lms_write( dev, 0x05, 0x3e ); /* LMS FAQ: Improve TX spurious emission performance */ bladerf_lms_write( dev, 0x47, 0x40 ); /* LMS FAQ: Improve ADC performance */ bladerf_lms_write( dev, 0x59, 0x29 ); /* LMS FAQ: Common mode voltage for ADC */ bladerf_lms_write( dev, 0x64, 0x36 ); /* LMS FAQ: Higher LNA Gain */ bladerf_lms_write( dev, 0x79, 0x37 ); /* FPGA workaround: Set IQ polarity for RX */ bladerf_lms_write( dev, 0x5a, 0xa0 ); /* Set a default saplerate */ bladerf_set_sample_rate( dev, BLADERF_MODULE_TX, 1000000, &actual ); bladerf_set_sample_rate( dev, BLADERF_MODULE_RX, 1000000, &actual ); /* Enable TX and RX */ bladerf_enable_module( dev, BLADERF_MODULE_TX, false ); bladerf_enable_module( dev, BLADERF_MODULE_RX, false ); /* Set a default frequency of 1GHz */ bladerf_set_frequency( dev, BLADERF_MODULE_TX, 1000000000 ); bladerf_set_frequency( dev, BLADERF_MODULE_RX, 1000000000 ); /* Set the calibrated VCTCXO DAC value */ bladerf_dac_write( dev, dev->dac_trim ); } /* TODO: Read this return from the SPI calls */ return 0; }
int bladerf_set_sampling(struct bladerf *dev, bladerf_sampling sampling) { uint8_t val ; int status = 0 ; if (sampling == BLADERF_SAMPLING_INTERNAL) { /* Disconnect the ADC input from the outside world */ status = bladerf_lms_read( dev, 0x09, &val ); if (status) { log_warning( "Could not read LMS to connect ADC to external pins\n" ); goto bladerf_set_sampling__done ; } val &= ~(1<<7) ; status = bladerf_lms_write( dev, 0x09, val ); if (status) { log_warning( "Could not write LMS to connect ADC to external pins\n" ); goto bladerf_set_sampling__done; } /* Turn on RXVGA2 */ status = bladerf_lms_read( dev, 0x64, &val ); if (status) { log_warning( "Could not read LMS to enable RXVGA2\n" ); goto bladerf_set_sampling__done; } val |= (1<<1) ; status = bladerf_lms_write( dev, 0x64, val ); if (status) { log_warning( "Could not write LMS to enable RXVGA2\n" ); goto bladerf_set_sampling__done; } } else { /* Turn off RXVGA2 */ status = bladerf_lms_read( dev, 0x64, &val ); if (status) { log_warning( "Could not read the LMS to disable RXVGA2\n" ); goto bladerf_set_sampling__done; } val &= ~(1<<1) ; status = bladerf_lms_write( dev, 0x64, val ); if (status) { log_warning( "Could not write the LMS to disable RXVGA2\n" ); goto bladerf_set_sampling__done; } /* Connect the external ADC pins to the internal ADC input */ status = bladerf_lms_read( dev, 0x09, &val ); if (status) { log_warning( "Could not read the LMS to connect ADC to internal pins\n" ); goto bladerf_set_sampling__done; } val |= (1<<7) ; status = bladerf_lms_write( dev, 0x09, val ); if (status) { log_warning( "Could not write the LMS to connect ADC to internal pins\n" ); } } bladerf_set_sampling__done: return status; }