void sdram_init(void) { __maybe_unused struct am335x_baseboard_id header; puts("sdram_init \n"); if (read_eeprom(&header) < 0) puts("Could not get board ID.\n"); if (board_is_evm_sk(&header)) { /* * EVM SK 1.2A and later use gpio0_7 to enable DDR3. * This is safe enough to do on older revs. */ gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en"); gpio_direction_output(GPIO_DDR_VTT_EN, 1); } if (board_is_evm_sk(&header)) config_ddr(303, MT41J128MJT125_IOCTRL_VALUE, &ddr3_data, &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0); else if (board_is_bone_lt(&header)) config_ddr(400, MT41K256M16HA125E_IOCTRL_VALUE, &ddr3_beagleblack_data, &ddr3_beagleblack_cmd_ctrl_data, &ddr3_beagleblack_emif_reg_data, 0); else if (board_is_evm_15_or_later(&header)) config_ddr(303, MT41J512M8RH125_IOCTRL_VALUE, &ddr3_evm_data, &ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data, 0); else config_ddr(266, MT47H128M16RT25E_IOCTRL_VALUE, &ddr2_data, &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0); udelay(500); }
void enable_board_pin_mux(struct am335x_baseboard_id *header) { /* Do board-specific muxes. */ if (board_is_bone(header)) { /* Beaglebone pinmux */ configure_module_pin_mux(i2c1_pin_mux); configure_module_pin_mux(mii1_pin_mux); configure_module_pin_mux(mmc0_pin_mux); #if defined(CONFIG_NAND) configure_module_pin_mux(nand_pin_mux); #elif defined(CONFIG_NOR) configure_module_pin_mux(bone_norcape_pin_mux); #else configure_module_pin_mux(mmc1_pin_mux); #endif } else if (board_is_gp_evm(header)) { /* General Purpose EVM */ unsigned short profile = detect_daughter_board_profile(); configure_module_pin_mux(rgmii1_pin_mux); configure_module_pin_mux(mmc0_pin_mux); /* In profile #2 i2c1 and spi0 conflict. */ if (profile & ~PROFILE_2) configure_module_pin_mux(i2c1_pin_mux); /* Profiles 2 & 3 don't have NAND */ #ifdef CONFIG_NAND if (profile & ~(PROFILE_2 | PROFILE_3)) configure_module_pin_mux(nand_pin_mux); #endif else if (profile == PROFILE_2) { configure_module_pin_mux(mmc1_pin_mux); configure_module_pin_mux(spi0_pin_mux); } } else if (board_is_idk(header)) { /* Industrial Motor Control (IDK) */ configure_module_pin_mux(mii1_pin_mux); configure_module_pin_mux(mmc0_no_cd_pin_mux); } else if (board_is_evm_sk(header)) { /* Starter Kit EVM */ configure_module_pin_mux(i2c1_pin_mux); configure_module_pin_mux(gpio0_7_pin_mux); configure_module_pin_mux(rgmii1_pin_mux); configure_module_pin_mux(mmc0_pin_mux_sk_evm); } else if (board_is_bone_lt(header)) { /* Beaglebone LT pinmux */ configure_module_pin_mux(i2c1_pin_mux); configure_module_pin_mux(mii1_pin_mux); configure_module_pin_mux(mmc0_pin_mux); #if defined(CONFIG_NAND) configure_module_pin_mux(nand_pin_mux); #elif defined(CONFIG_NOR) configure_module_pin_mux(bone_norcape_pin_mux); #else configure_module_pin_mux(mmc1_pin_mux); #endif } else { puts("Unknown board, cannot configure pinmux."); hang(); } }
const struct dpll_params *get_dpll_ddr_params(void) { struct am335x_baseboard_id header; puts("get_dpll_ddr_params\n"); enable_i2c0_pin_mux(); i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); if (read_eeprom(&header) < 0) puts("Could not get board ID.\n"); // usleep(2); if (board_is_evm_sk(&header)) return &dpll_ddr_evm_sk; else if (board_is_bone_lt(&header)) return &dpll_ddr_bone_black; else if (board_is_evm_15_or_later(&header)) return &dpll_ddr_evm_sk; else return &dpll_ddr; // usleep(3); }
/* * early system init of muxing and clocks. */ void s_init(void) { /* WDT1 is already running when the bootloader gets control * Disable it to avoid "random" resets */ writel(0xAAAA, &wdtimer->wdtwspr); while (readl(&wdtimer->wdtwwps) != 0x0) ; writel(0x5555, &wdtimer->wdtwspr); while (readl(&wdtimer->wdtwwps) != 0x0) ; #ifdef CONFIG_SPL_BUILD /* Setup the PLLs and the clocks for the peripherals */ pll_init(); /* Enable RTC32K clock */ rtc32k_enable(); /* UART softreset */ u32 regVal; #ifdef CONFIG_SERIAL1 enable_uart0_pin_mux(); #endif /* CONFIG_SERIAL1 */ #ifdef CONFIG_SERIAL2 enable_uart1_pin_mux(); #endif /* CONFIG_SERIAL2 */ #ifdef CONFIG_SERIAL3 enable_uart2_pin_mux(); #endif /* CONFIG_SERIAL3 */ #ifdef CONFIG_SERIAL4 enable_uart3_pin_mux(); #endif /* CONFIG_SERIAL4 */ #ifdef CONFIG_SERIAL5 enable_uart4_pin_mux(); #endif /* CONFIG_SERIAL5 */ #ifdef CONFIG_SERIAL6 enable_uart5_pin_mux(); #endif /* CONFIG_SERIAL6 */ regVal = readl(&uart_base->uartsyscfg); regVal |= UART_RESET; writel(regVal, &uart_base->uartsyscfg); while ((readl(&uart_base->uartsyssts) & UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK) ; /* Disable smart idle */ regVal = readl(&uart_base->uartsyscfg); regVal |= UART_SMART_IDLE_EN; writel(regVal, &uart_base->uartsyscfg); gd = &gdata; preloader_console_init(); /* Initalize the board header */ enable_i2c0_pin_mux(); i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); if (read_eeprom() < 0) puts("Could not get board ID.\n"); enable_board_pin_mux(&header); if (board_is_evm_sk()) { /* * EVM SK 1.2A and later use gpio0_7 to enable DDR3. * This is safe enough to do on older revs. */ gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en"); gpio_direction_output(GPIO_DDR_VTT_EN, 1); } if (board_is_evm_sk() || board_is_bone_lt()) config_ddr(303, MT41J128MJT125_IOCTRL_VALUE, &ddr3_data, &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data); else if (board_is_evm_15_or_later()) config_ddr(303, MT41J512M8RH125_IOCTRL_VALUE, &ddr3_evm_data, &ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data); else config_ddr(266, MT47H128M16RT25E_IOCTRL_VALUE, &ddr2_data, &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data); #endif }
int board_eth_init(bd_t *bis) { int rv, n = 0; uint8_t mac_addr[6]; uint32_t mac_hi, mac_lo; __maybe_unused struct am335x_baseboard_id header; /* try reading mac address from efuse */ mac_lo = readl(&cdev->macid0l); mac_hi = readl(&cdev->macid0h); mac_addr[0] = mac_hi & 0xFF; mac_addr[1] = (mac_hi & 0xFF00) >> 8; mac_addr[2] = (mac_hi & 0xFF0000) >> 16; mac_addr[3] = (mac_hi & 0xFF000000) >> 24; mac_addr[4] = mac_lo & 0xFF; mac_addr[5] = (mac_lo & 0xFF00) >> 8; #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) if (!getenv("ethaddr")) { printf("<ethaddr> not set. Validating first E-fuse MAC\n"); if (is_valid_ether_addr(mac_addr)) eth_setenv_enetaddr("ethaddr", mac_addr); } #ifdef CONFIG_DRIVER_TI_CPSW mac_lo = readl(&cdev->macid1l); mac_hi = readl(&cdev->macid1h); mac_addr[0] = mac_hi & 0xFF; mac_addr[1] = (mac_hi & 0xFF00) >> 8; mac_addr[2] = (mac_hi & 0xFF0000) >> 16; mac_addr[3] = (mac_hi & 0xFF000000) >> 24; mac_addr[4] = mac_lo & 0xFF; mac_addr[5] = (mac_lo & 0xFF00) >> 8; if (!getenv("eth1addr")) { if (is_valid_ether_addr(mac_addr)) eth_setenv_enetaddr("eth1addr", mac_addr); } if (read_eeprom(&header) < 0) puts("Could not get board ID.\n"); if (board_is_bone(&header) || board_is_bone_lt(&header) || board_is_idk(&header)) { writel(MII_MODE_ENABLE, &cdev->miisel); cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_MII; } else { writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel); cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RGMII; } rv = cpsw_register(&cpsw_data); if (rv < 0) printf("Error %d registering CPSW switch\n", rv); else n += rv; #endif /* * * CPSW RGMII Internal Delay Mode is not supported in all PVT * operating points. So we must set the TX clock delay feature * in the AR8051 PHY. Since we only support a single ethernet * device in U-Boot, we only do this for the first instance. */ #define AR8051_PHY_DEBUG_ADDR_REG 0x1d #define AR8051_PHY_DEBUG_DATA_REG 0x1e #define AR8051_DEBUG_RGMII_CLK_DLY_REG 0x5 #define AR8051_RGMII_TX_CLK_DLY 0x100 if (board_is_evm_sk(&header) || board_is_gp_evm(&header)) { const char *devname; devname = miiphy_get_current_dev(); miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_ADDR_REG, AR8051_DEBUG_RGMII_CLK_DLY_REG); miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_DATA_REG, AR8051_RGMII_TX_CLK_DLY); } #endif #if defined(CONFIG_USB_ETHER) && \ (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USBETH_SUPPORT)) if (is_valid_ether_addr(mac_addr)) eth_setenv_enetaddr("usbnet_devaddr", mac_addr); rv = usb_eth_initialize(bis); if (rv < 0) printf("Error %d registering USB_ETHER\n", rv); else n += rv; #endif return n; }
void am33xx_spl_board_init(void) { struct am335x_baseboard_id header; int mpu_vdd; puts("am33xx_spl_board_init \n"); if (read_eeprom(&header) < 0) puts("Could not get board ID.\n"); /* Get the frequency */ dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev); if (board_is_bone(&header) || board_is_bone_lt(&header)) { /* BeagleBone PMIC Code */ int usb_cur_lim; /* * Only perform PMIC configurations if board rev > A1 * on Beaglebone White */ //if (board_is_bone(&header) && !strncmp(header.version, // "00A1", 4)) // return; //if (i2c_probe(TPS65217_CHIP_PM)) // return; /* * On Beaglebone White we need to ensure we have AC power * before increasing the frequency. */ /* if (board_is_bone(&header)) { uchar pmic_status_reg; if (tps65217_reg_read(TPS65217_STATUS, &pmic_status_reg)) return; if (!(pmic_status_reg & TPS65217_PWR_SRC_AC_BITMASK)) { puts("No AC power, disabling frequency switch\n"); return; } }*/ /* * Override what we have detected since we know if we have * a Beaglebone Black it supports 1GHz. */ // if (board_is_bone_lt(&header)) dpll_mpu_opp100.m = MPUPLL_M_1000; /* * Increase USB current limit to 1300mA or 1800mA and set * the MPU voltage controller as needed. */ // if (dpll_mpu_opp100.m == MPUPLL_M_1000) { // usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA; // mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV; // } else { // usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA; // mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV; // } // if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, // TPS65217_POWER_PATH, // usb_cur_lim, // TPS65217_USB_INPUT_CUR_LIMIT_MASK)) // puts("tps65217_reg_write failure\n"); /* Set DCDC3 (CORE) voltage to 1.125V */ // if (tps65217_voltage_update(TPS65217_DEFDCDC3, // TPS65217_DCDC_VOLT_SEL_1125MV)) { // puts("tps65217_voltage_update failure\n"); // return; // } /* Set CORE Frequencies to OPP100 */ do_setup_dpll(&dpll_core_regs, &dpll_core_opp100); /* Set DCDC2 (MPU) voltage */ // if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) { // puts("tps65217_voltage_update failure\n"); // return; // } /* * Set LDO3, LDO4 output voltage to 3.3V for Beaglebone. * Set LDO3 to 1.8V and LDO4 to 3.3V for Beaglebone Black. */ // if (board_is_bone(&header)) { // if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, // TPS65217_DEFLS1, // TPS65217_LDO_VOLTAGE_OUT_3_3, // TPS65217_LDO_MASK)) // puts("tps65217_reg_write failure\n"); // } else { /// if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, // TPS65217_DEFLS1, // TPS65217_LDO_VOLTAGE_OUT_1_8, // TPS65217_LDO_MASK)) // puts("tps65217_reg_write failure\n"); // } // /// if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, // TPS65217_DEFLS2, // TPS65217_LDO_VOLTAGE_OUT_3_3, // TPS65217_LDO_MASK)) // puts("tps65217_reg_write failure\n"); } else { int sil_rev; /* * The GP EVM, IDK and EVM SK use a TPS65910 PMIC. For all * MPU frequencies we support we use a CORE voltage of * 1.1375V. For MPU voltage we need to switch based on * the frequency we are running at. */ // if (i2c_probe(TPS65910_CTRL_I2C_ADDR)) // return; /* * Depending on MPU clock and PG we will need a different * VDD to drive at that speed. */ // sil_rev = readl(&cdev->deviceid) >> 28; // mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev, // dpll_mpu_opp100.m); // /* Tell the TPS65910 to use i2c */ // tps65910_set_i2c_control(); /* First update MPU voltage. */ // if (tps65910_voltage_update(MPU, mpu_vdd)) // return; /* Second, update the CORE voltage. */ // if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_3)) // return; /* Set CORE Frequencies to OPP100 */ // do_setup_dpll(&dpll_core_regs, &dpll_core_opp100); } /* Set MPU Frequency to what we detected now that voltages are set */ do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100); puts("spl_board_init end \n"); }