int get_voltrail_opp(int rail_offset) { int opp; switch (rail_offset) { case VOLT_MPU: opp = DRA7_MPU_OPP; /* DRA71x supports only OPP_NOM for MPU */ if (board_is_dra71x_evm()) opp = OPP_NOM; break; case VOLT_CORE: opp = DRA7_CORE_OPP; /* DRA71x supports only OPP_NOM for CORE */ if (board_is_dra71x_evm()) opp = OPP_NOM; break; case VOLT_GPU: opp = DRA7_GPU_OPP; /* DRA71x supports only OPP_NOM for GPU */ if (board_is_dra71x_evm()) opp = OPP_NOM; break; case VOLT_EVE: opp = DRA7_DSPEVE_OPP; /* * DRA71x does not support OPP_OD for EVE. * If OPP_OD is selected by menuconfig, fallback * to OPP_NOM. */ if (board_is_dra71x_evm() && opp == OPP_OD) opp = OPP_NOM; break; case VOLT_IVA: opp = DRA7_IVA_OPP; /* * DRA71x does not support OPP_OD for IVA. * If OPP_OD is selected by menuconfig, fallback * to OPP_NOM. */ if (board_is_dra71x_evm() && opp == OPP_OD) opp = OPP_NOM; break; default: opp = OPP_NOM; } return opp; }
void do_board_detect(void) { char *bname = NULL; int rc; rc = ti_i2c_eeprom_dra7_get(CONFIG_EEPROM_BUS_ADDRESS, CONFIG_EEPROM_CHIP_ADDRESS); if (rc) printf("ti_i2c_eeprom_init failed %d\n", rc); if (board_is_dra74x_evm()) { bname = "DRA74x EVM"; } else if (board_is_dra72x_evm()) { bname = "DRA72x EVM"; } else if (board_is_dra71x_evm()) { bname = "DRA71x EVM"; } else { /* If EEPROM is not populated */ if (is_dra72x()) bname = "DRA72x EVM"; else bname = "DRA74x EVM"; } if (bname) snprintf(sysinfo.board_string, SYSINFO_BOARD_NAME_MAX_LEN, "Board: %s REV %s\n", bname, board_ti_get_rev()); }
int board_late_init(void) { #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG char *name = "unknown"; if (is_dra72x()) { if (board_is_dra72x_revc_or_later()) name = "dra72x-revc"; else if (board_is_dra71x_evm()) name = "dra71x"; else name = "dra72x"; } else { name = "dra7xx"; } set_board_info_env(name); /* * Default FIT boot on HS devices. Non FIT images are not allowed * on HS devices. */ if (get_device_type() == HS_DEVICE) env_set("boot_fit", "1"); omap_die_id_serial(); omap_set_fastboot_vars(); #endif return 0; }
int board_late_init(void) { #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG char *name = "unknown"; if (is_dra72x()) { if (board_is_dra72x_revc_or_later()) name = "dra72x-revc"; else if (board_is_dra71x_evm()) name = "dra71x"; else name = "dra72x"; } else if (is_dra76x_abz()) { name = "dra76x_abz"; } else if (is_dra76x_acd()) { name = "dra76x_acd"; } else { name = "dra7xx"; } set_board_info_env(name); /* * Default FIT boot on HS devices. Non FIT images are not allowed * on HS devices. */ if (get_device_type() == HS_DEVICE) env_set("boot_fit", "1"); omap_die_id_serial(); omap_set_fastboot_vars(); /* * Hook the LDO1 regulator to EN pin. This applies only to LP8733 * Rest all regulators are hooked to EN Pin at reset. */ if (board_is_dra71x_evm()) palmas_i2c_write_u8(LP873X_I2C_SLAVE_ADDR, 0x9, 0x7); #endif #if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL) if (device_okay("/ocp/omap_dwc3_1@48880000")) enable_usb_clocks(0); if (device_okay("/ocp/omap_dwc3_2@488c0000")) enable_usb_clocks(1); #endif return 0; }
void board_mmc_poweron_ldo(uint voltage) { if (board_is_dra71x_evm()) { if (voltage == LDO_VOLT_3V0) voltage = 0x19; else if (voltage == LDO_VOLT_1V8) voltage = 0xa; lp873x_mmc1_poweron_ldo(voltage); } else if (board_is_dra76x_evm()) { palmas_mmc1_poweron_ldo(LDO4_VOLTAGE, LDO4_CTRL, voltage); } else { palmas_mmc1_poweron_ldo(LDO1_VOLTAGE, LDO1_CTRL, voltage); } }
void vcores_init(void) { if (board_is_dra74x_evm()) { *omap_vcores = &dra752_volts; } else if (board_is_dra72x_evm()) { *omap_vcores = &dra722_volts; } else if (board_is_dra71x_evm()) { *omap_vcores = &dra718_volts; } else { /* If EEPROM is not populated */ if (is_dra72x()) *omap_vcores = &dra722_volts; else *omap_vcores = &dra752_volts; } }
int board_fit_config_name_match(const char *name) { if (is_dra72x()) { if (board_is_dra71x_evm()) { if (!strcmp(name, "dra71-evm")) return 0; }else if(board_is_dra72x_revc_or_later()) { if (!strcmp(name, "dra72-evm-revc")) return 0; } else if (!strcmp(name, "dra72-evm")) { return 0; } } else if (!is_dra72x() && !strcmp(name, "dra7-evm")) { return 0; } return -1; }
void recalibrate_iodelay(void) { struct pad_conf_entry const *pads, *delta_pads = NULL; struct iodelay_cfg_entry const *iodelay; int npads, niodelays, delta_npads = 0; int ret; switch (omap_revision()) { case DRA722_ES1_0: case DRA722_ES2_0: pads = dra72x_core_padconf_array_common; npads = ARRAY_SIZE(dra72x_core_padconf_array_common); if (board_is_dra71x_evm()) { pads = dra71x_core_padconf_array; npads = ARRAY_SIZE(dra71x_core_padconf_array); iodelay = dra71_iodelay_cfg_array; niodelays = ARRAY_SIZE(dra71_iodelay_cfg_array); } else if (board_is_dra72x_revc_or_later()) { delta_pads = dra72x_rgmii_padconf_array_revc; delta_npads = ARRAY_SIZE(dra72x_rgmii_padconf_array_revc); iodelay = dra72_iodelay_cfg_array_revc; niodelays = ARRAY_SIZE(dra72_iodelay_cfg_array_revc); } else { delta_pads = dra72x_rgmii_padconf_array_revb; delta_npads = ARRAY_SIZE(dra72x_rgmii_padconf_array_revb); iodelay = dra72_iodelay_cfg_array_revb; niodelays = ARRAY_SIZE(dra72_iodelay_cfg_array_revb); } break; case DRA752_ES1_0: case DRA752_ES1_1: pads = dra74x_core_padconf_array; npads = ARRAY_SIZE(dra74x_core_padconf_array); iodelay = dra742_es1_1_iodelay_cfg_array; niodelays = ARRAY_SIZE(dra742_es1_1_iodelay_cfg_array); break; default: case DRA752_ES2_0: pads = dra74x_core_padconf_array; npads = ARRAY_SIZE(dra74x_core_padconf_array); iodelay = dra742_es2_0_iodelay_cfg_array; niodelays = ARRAY_SIZE(dra742_es2_0_iodelay_cfg_array); /* Setup port1 and port2 for rgmii with 'no-id' mode */ clrset_spare_register(1, 0, RGMII2_ID_MODE_N_MASK | RGMII1_ID_MODE_N_MASK); break; } /* Setup I/O isolation */ ret = __recalibrate_iodelay_start(); if (ret) goto err; /* Do the muxing here */ do_set_mux32((*ctrl)->control_padconf_core_base, pads, npads); /* Now do the weird minor deltas that should be safe */ if (delta_npads) do_set_mux32((*ctrl)->control_padconf_core_base, delta_pads, delta_npads); /* Setup IOdelay configuration */ ret = do_set_iodelay((*ctrl)->iodelay_config_base, iodelay, niodelays); err: /* Closeup.. remove isolation */ __recalibrate_iodelay_end(ret); }
void recalibrate_iodelay(void) { struct pad_conf_entry const *pads, *delta_pads = NULL; struct iodelay_cfg_entry const *iodelay; int npads, niodelays, delta_npads = 0; int ret; switch (omap_revision()) { case DRA722_ES1_0: case DRA722_ES2_0: case DRA722_ES2_1: pads = dra72x_core_padconf_array_common; npads = ARRAY_SIZE(dra72x_core_padconf_array_common); if (board_is_dra71x_evm()) { pads = dra71x_core_padconf_array; npads = ARRAY_SIZE(dra71x_core_padconf_array); iodelay = dra71_iodelay_cfg_array; niodelays = ARRAY_SIZE(dra71_iodelay_cfg_array); /* If SW8 on the EVM is set to enable NAND then * overwrite the pins used by VOUT3 with NAND. */ if (!nand_sw_detect()) { delta_pads = dra71x_nand_padconf_array; delta_npads = ARRAY_SIZE(dra71x_nand_padconf_array); } else { delta_pads = dra71x_vout3_padconf_array; delta_npads = ARRAY_SIZE(dra71x_vout3_padconf_array); } } else if (board_is_dra72x_revc_or_later()) { delta_pads = dra72x_rgmii_padconf_array_revc; delta_npads = ARRAY_SIZE(dra72x_rgmii_padconf_array_revc); iodelay = dra72_iodelay_cfg_array_revc; niodelays = ARRAY_SIZE(dra72_iodelay_cfg_array_revc); } else { delta_pads = dra72x_rgmii_padconf_array_revb; delta_npads = ARRAY_SIZE(dra72x_rgmii_padconf_array_revb); iodelay = dra72_iodelay_cfg_array_revb; niodelays = ARRAY_SIZE(dra72_iodelay_cfg_array_revb); } break; case DRA752_ES1_0: case DRA752_ES1_1: pads = dra74x_core_padconf_array; npads = ARRAY_SIZE(dra74x_core_padconf_array); iodelay = dra742_es1_1_iodelay_cfg_array; niodelays = ARRAY_SIZE(dra742_es1_1_iodelay_cfg_array); break; case DRA762_ACD_ES1_0: case DRA762_ES1_0: pads = dra76x_core_padconf_array; npads = ARRAY_SIZE(dra76x_core_padconf_array); iodelay = dra76x_es1_0_iodelay_cfg_array; niodelays = ARRAY_SIZE(dra76x_es1_0_iodelay_cfg_array); break; default: case DRA752_ES2_0: case DRA762_ABZ_ES1_0: pads = dra74x_core_padconf_array; npads = ARRAY_SIZE(dra74x_core_padconf_array); iodelay = dra742_es2_0_iodelay_cfg_array; niodelays = ARRAY_SIZE(dra742_es2_0_iodelay_cfg_array); /* Setup port1 and port2 for rgmii with 'no-id' mode */ clrset_spare_register(1, 0, RGMII2_ID_MODE_N_MASK | RGMII1_ID_MODE_N_MASK); break; } /* Setup I/O isolation */ ret = __recalibrate_iodelay_start(); if (ret) goto err; /* Do the muxing here */ do_set_mux32((*ctrl)->control_padconf_core_base, pads, npads); /* Now do the weird minor deltas that should be safe */ if (delta_npads) do_set_mux32((*ctrl)->control_padconf_core_base, delta_pads, delta_npads); if (is_dra76x()) /* Set mux for MCAN instead of DCAN1 */ clrsetbits_le32((*ctrl)->control_core_control_spare_rw, MCAN_SEL_ALT_MASK, MCAN_SEL); /* Setup IOdelay configuration */ ret = do_set_iodelay((*ctrl)->iodelay_config_base, iodelay, niodelays); err: /* Closeup.. remove isolation */ __recalibrate_iodelay_end(ret); }