int ph1_pro4_sbc_init(const struct uniphier_board_data *bd) { /* * Only CS1 is connected to support card. * BKSZ[1:0] should be set to "01". */ writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL10); writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL11); writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL12); writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL14); if (boot_is_swapped()) { /* * Boot Swap On: boot from external NOR/SRAM * 0x42000000-0x43ffffff is a mirror of 0x40000000-0x41ffffff. * * 0x40000000-0x41efffff, 0x42000000-0x43efffff: memory bank * 0x41f00000-0x41ffffff, 0x43f00000-0x43ffffff: peripherals */ writel(0x0000bc01, SBBASE0); } else { /* * Boot Swap Off: boot from mask ROM * 0x40000000-0x41ffffff: mask ROM * 0x42000000-0x43efffff: memory bank (31MB) * 0x43f00000-0x43ffffff: peripherals (1MB) */ writel(0x0000be01, SBBASE0); /* dummy */ writel(0x0200be01, SBBASE1); } return 0; }
void sbc_init(void) { /* only address/data multiplex mode is supported */ /* * Only CS1 is connected to support card. * BKSZ[1:0] should be set to "01". */ writel(SBCTRL0_ADMULTIPLX_MEM_VALUE, SBCTRL10); writel(SBCTRL1_ADMULTIPLX_MEM_VALUE, SBCTRL11); writel(SBCTRL2_ADMULTIPLX_MEM_VALUE, SBCTRL12); if (boot_is_swapped()) { /* * Boot Swap On: boot from external NOR/SRAM * 0x02000000-0x03ffffff is a mirror of 0x00000000-0x01ffffff. * * 0x00000000-0x01efffff, 0x02000000-0x03efffff: memory bank * 0x01f00000-0x01ffffff, 0x03f00000-0x03ffffff: peripherals */ writel(0x0000bc01, SBBASE0); } else { /* * Boot Swap Off: boot from mask ROM * 0x00000000-0x01ffffff: mask ROM * 0x02000000-0x03efffff: memory bank (31MB) * 0x03f00000-0x03ffffff: peripherals (1MB) */ writel(0x0000be01, SBBASE0); /* dummy */ writel(0x0200be01, SBBASE1); } sg_set_pinsel(99, 1); /* GPIO26 -> EA24 */ }
u32 spl_boot_device_raw(void) { if (boot_is_swapped()) return BOOT_DEVICE_NOR; switch (uniphier_get_soc_type()) { #if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3) case SOC_UNIPHIER_PH1_SLD3: return ph1_sld3_boot_device(); #endif #if defined(CONFIG_ARCH_UNIPHIER_PH1_LD4) || \ defined(CONFIG_ARCH_UNIPHIER_PH1_PRO4) || \ defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8) case SOC_UNIPHIER_PH1_LD4: case SOC_UNIPHIER_PH1_PRO4: case SOC_UNIPHIER_PH1_SLD8: return ph1_ld4_boot_device(); #endif #if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO5) case SOC_UNIPHIER_PH1_PRO5: return ph1_pro5_boot_device(); #endif #if defined(CONFIG_ARCH_UNIPHIER_PROXSTREAM2) || \ defined(CONFIG_ARCH_UNIPHIER_PH1_LD6B) case SOC_UNIPHIER_PROXSTREAM2: case SOC_UNIPHIER_PH1_LD6B: return proxstream2_boot_device(); #endif default: return BOOT_DEVICE_NONE; } }
u32 spl_boot_device(void) { u32 boot_mode; if (boot_is_swapped()) return BOOT_DEVICE_NOR; boot_mode = get_boot_mode_sel(); return boot_device_table[boot_mode].type; }
static int do_pinmon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { int mode_sel, i; printf("Boot Swap: %s\n\n", boot_is_swapped() ? "ON" : "OFF"); mode_sel = get_boot_mode_sel(); puts("Boot Mode Pin:\n"); for (i = 0; boot_device_table[i].info; i++) printf(" %c %02x %s\n", i == mode_sel ? '*' : ' ', i, boot_device_table[i].info); return 0; }
static int do_pinmon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { struct boot_device_info *table; u32 mode_sel, n = 0; mode_sel = get_boot_mode_sel(); printf("Boot Swap: %s\n\n", boot_is_swapped() ? "ON" : "OFF"); puts("Boot Mode Pin:\n"); for (table = boot_device_table; strlen(table->info); table++) { printf(" %c %02x %s\n", n == mode_sel ? '*' : ' ', n, table->info); n++; } return 0; }
static int do_pinmon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { printf("Boot Swap: %s\n\n", boot_is_swapped() ? "ON" : "OFF"); switch (uniphier_get_soc_id()) { #if defined(CONFIG_ARCH_UNIPHIER_SLD3) case UNIPHIER_SLD3_ID: uniphier_sld3_boot_mode_show(); break; #endif #if defined(CONFIG_ARCH_UNIPHIER_LD4) || defined(CONFIG_ARCH_UNIPHIER_PRO4) || \ defined(CONFIG_ARCH_UNIPHIER_SLD8) case UNIPHIER_LD4_ID: case UNIPHIER_PRO4_ID: case UNIPHIER_SLD8_ID: uniphier_ld4_boot_mode_show(); break; #endif #if defined(CONFIG_ARCH_UNIPHIER_PRO5) case UNIPHIER_PRO5_ID: uniphier_pro5_boot_mode_show(); break; #endif #if defined(CONFIG_ARCH_UNIPHIER_PXS2) || defined(CONFIG_ARCH_UNIPHIER_LD6B) case UNIPHIER_PXS2_ID: case UNIPHIER_LD6B_ID: uniphier_pxs2_boot_mode_show(); break; #endif #if defined(CONFIG_ARCH_UNIPHIER_LD11) || defined(CONFIG_ARCH_UNIPHIER_LD20) case UNIPHIER_LD11_ID: case UNIPHIER_LD20_ID: uniphier_ld20_boot_mode_show(); break; #endif default: break; } return 0; }
void sbc_init(void) { u32 tmp; /* system bus output enable */ tmp = readl(PC0CTRL); tmp &= 0xfffffcff; writel(tmp, PC0CTRL); /* * Only CS1 is connected to support card. * BKSZ[1:0] should be set to "01". */ writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL10); writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL11); writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL12); writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL14); if (boot_is_swapped()) { /* * Boot Swap On: boot from external NOR/SRAM * 0x02000000-0x03ffffff is a mirror of 0x00000000-0x01ffffff. * * 0x00000000-0x01efffff, 0x02000000-0x03efffff: memory bank * 0x01f00000-0x01ffffff, 0x03f00000-0x03ffffff: peripherals */ writel(0x0000bc01, SBBASE0); } else { /* * Boot Swap Off: boot from mask ROM * 0x00000000-0x01ffffff: mask ROM * 0x02000000-0x03efffff: memory bank (31MB) * 0x03f00000-0x03ffffff: peripherals (1MB) */ writel(0x0000be01, SBBASE0); /* dummy */ writel(0x0200be01, SBBASE1); } }
void sbc_init(void) { u32 tmp; /* system bus output enable */ tmp = readl(PC0CTRL); tmp &= 0xfffffcff; writel(tmp, PC0CTRL); /* XECS1: sub/boot memory (boot swap = off/on) */ writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10); writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11); writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL12); writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL14); /* XECS0: boot/sub memory (boot swap = off/on) */ writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL00); writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL01); writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL02); writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL04); /* XECS3: peripherals */ writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL30); writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL31); writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL32); writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL34); /* base address regsiters */ writel(0x0000bc01, SBBASE0); writel(0x0400bc01, SBBASE1); writel(0x0800bf01, SBBASE3); /* enable access to sub memory when boot swap is on */ if (boot_is_swapped()) sg_set_pinsel(155, 1); /* PORT24 -> XECS0 */ sg_set_pinsel(156, 1); /* PORT25 -> XECS3 */ }
static int do_pinmon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { printf("Boot Swap: %s\n\n", boot_is_swapped() ? "ON" : "OFF"); switch (uniphier_get_soc_type()) { #if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3) case SOC_UNIPHIER_PH1_SLD3: ph1_sld3_boot_mode_show(); break; #endif #if defined(CONFIG_ARCH_UNIPHIER_PH1_LD4) || \ defined(CONFIG_ARCH_UNIPHIER_PH1_PRO4) || \ defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8) case SOC_UNIPHIER_PH1_LD4: case SOC_UNIPHIER_PH1_PRO4: case SOC_UNIPHIER_PH1_SLD8: ph1_ld4_boot_mode_show(); break; #endif #if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO5) case SOC_UNIPHIER_PH1_PRO5: ph1_pro5_boot_mode_show(); break; #endif #if defined(CONFIG_ARCH_UNIPHIER_PROXSTREAM2) || \ defined(CONFIG_ARCH_UNIPHIER_PH1_LD6B) case SOC_UNIPHIER_PROXSTREAM2: case SOC_UNIPHIER_PH1_LD6B: proxstream2_boot_mode_show(); break; #endif default: break; } return 0; }
void sbc_init(void) { #if defined(CONFIG_PFC_MICRO_SUPPORT_CARD) /* * Only CS1 is connected to support card. * BKSZ[1:0] should be set to "01". */ writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL10); writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL11); writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL12); writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL14); if (boot_is_swapped()) { /* * Boot Swap On: boot from external NOR/SRAM * 0x02000000-0x03ffffff is a mirror of 0x00000000-0x01ffffff. * * 0x00000000-0x01efffff, 0x02000000-0x03efffff: memory bank * 0x01f00000-0x01ffffff, 0x03f00000-0x03ffffff: peripherals */ writel(0x0000bc01, SBBASE0); } else { /* * Boot Swap Off: boot from mask ROM * 0x00000000-0x01ffffff: mask ROM * 0x02000000-0x3effffff: memory bank (31MB) * 0x03f00000-0x3fffffff: peripherals (1MB) */ writel(0x0000be01, SBBASE0); /* dummy */ writel(0x0200be01, SBBASE1); } #elif defined(CONFIG_DCC_MICRO_SUPPORT_CARD) #if !defined(CONFIG_SPL_BUILD) /* XECS0: boot/sub memory (boot swap = off/on) */ writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL00); writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL01); writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL02); writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL04); #endif /* XECS1: sub/boot memory (boot swap = off/on) */ writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10); writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11); writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL12); writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL14); /* XECS3: peripherals */ writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL30); writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL31); writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL32); writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL34); writel(0x0000bc01, SBBASE0); /* boot memory */ writel(0x0400bc01, SBBASE1); /* sub memory */ writel(0x0800bf01, SBBASE3); /* peripherals */ #if !defined(CONFIG_SPL_BUILD) sg_set_pinsel(318, 5); /* PORT22 -> XECS0 */ #endif sg_set_pinsel(313, 5); /* PORT15 -> XECS3 */ writel(0x00000001, SG_LOADPINCTRL); #endif /* CONFIG_XXX_MICRO_SUPPORT_CARD */ }