static void
via_sata_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa,
int satareg_shift)
{
struct pciide_channel *cp;
struct ata_channel *wdc_cp;
struct wdc_regs *wdr;
pcireg_t interface;
int channel;
interface = PCI_INTERFACE(pa->pa_class);
if (via_sata_chip_map_common(sc, pa) == 0)
return;
if (interface == 0) {
ATADEBUG_PRINT(("via_sata_chip_map interface == 0\n"),
DEBUG_PROBE);
interface = PCIIDE_INTERFACE_BUS_MASTER_DMA |
PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1);
}
sc->sc_wdcdev.sc_atac.atac_probe = wdc_sataprobe;
sc->sc_wdcdev.wdc_maxdrives = 1;
for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
channel++) {
cp = &sc->pciide_channels[channel];
if (pciide_chansetup(sc, channel, interface) == 0)
continue;
wdc_cp = &cp->ata_channel;
wdr = CHAN_TO_WDC_REGS(wdc_cp);
wdr->sata_iot = sc->sc_ba5_st;
wdr->sata_baseioh = sc->sc_ba5_sh;
if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh,
(wdc_cp->ch_channel << satareg_shift) + 0x0, 4,
&wdr->sata_status) != 0) {
aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
"couldn't map channel %d sata_status regs\n",
wdc_cp->ch_channel);
continue;
}
if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh,
(wdc_cp->ch_channel << satareg_shift) + 0x4, 4,
&wdr->sata_error) != 0) {
aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
"couldn't map channel %d sata_error regs\n",
wdc_cp->ch_channel);
continue;
}
if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh,
(wdc_cp->ch_channel << satareg_shift) + 0x8, 4,
&wdr->sata_control) != 0) {
aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
"couldn't map channel %d sata_control regs\n",
wdc_cp->ch_channel);
continue;
}
pciide_mapchan(pa, cp, interface, pciide_pci_intr);
}
}
/* ARGSUSED */
static void
mvusb_attach(device_t parent, device_t self, void *aux)
{
struct mvusb_softc *sc = device_private(self);
struct marvell_attach_args *mva = aux;
usbd_status r;
aprint_normal(": Marvell USB 2.0 Interface\n");
aprint_naive("\n");
sc->sc.sc_dev = self;
sc->sc.sc_bus.hci_private = sc;
sc->sc_model = mva->mva_model;
sc->sc_rev = mva->mva_revision;
sc->sc_iot = mva->mva_iot;
/* Map I/O registers for marvell usb */
if (bus_space_subregion(mva->mva_iot, mva->mva_ioh, mva->mva_offset,
mva->mva_size, &sc->sc_ioh)) {
aprint_error_dev(self, "can't map registers\n");
return;
}
mvusb_init(sc, mva->mva_tags);
/* Map I/O registers for ehci */
sc->sc.sc_size = MARVELL_USB_EHCI_SIZE;
if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, MARVELL_USB_EHCI_BASE,
sc->sc.sc_size, &sc->sc.ioh)) {
aprint_error_dev(self, "can't subregion registers\n");
return;
}
sc->sc.iot = sc->sc_iot;
sc->sc.sc_bus.dmatag = mva->mva_dmat;
/* Disable interrupts, so we don't get any spurious ones. */
sc->sc.sc_offs = EREAD1(&sc->sc, EHCI_CAPLENGTH);
DPRINTF(("%s: offs=%d\n", device_xname(self), sc->sc.sc_offs));
EOWRITE2(&sc->sc, EHCI_USBINTR, 0);
marvell_intr_establish(mva->mva_irq, IPL_USB, ehci_intr, sc);
sc->sc.sc_bus.usbrev = USBREV_2_0;
/* Figure out vendor for root hub descriptor. */
sc->sc.sc_id_vendor = 0x0000; /* XXXXX */
strcpy(sc->sc.sc_vendor, "Marvell");
sc->sc.sc_vendor_init = mvusb_vendor_init;
sc->sc.sc_vendor_port_status = mvusb_vendor_port_status;
r = ehci_init(&sc->sc);
if (r != USBD_NORMAL_COMPLETION) {
aprint_error_dev(self, "init failed, error=%d\n", r);
return;
}
/* Attach usb device. */
sc->sc.sc_child = config_found(self, &sc->sc.sc_bus, usbctlprint);
}
static void
sec_attach(device_t parent, device_t self, void *aux)
{
struct podulebus_attach_args *pa = aux;
struct sec_softc *sc = device_private(self);
int i;
sc->sc_sbic.sc_dev = self;
/* Set up bus spaces */
sc->sc_pod_t = pa->pa_fast_t;
bus_space_map(pa->pa_fast_t, pa->pa_fast_base, 0x1000, 0,
&sc->sc_pod_h);
sc->sc_mod_t = pa->pa_mod_t;
bus_space_map(pa->pa_mod_t, pa->pa_mod_base, 0x1000, 0,
&sc->sc_mod_h);
sc->sc_sbic.sc_regt = sc->sc_mod_t;
bus_space_subregion(sc->sc_mod_t, sc->sc_mod_h, SEC_SBIC + 0, 1,
&sc->sc_sbic.sc_asr_regh);
bus_space_subregion(sc->sc_mod_t, sc->sc_mod_h, SEC_SBIC + 1, 1,
&sc->sc_sbic.sc_data_regh);
sc->sc_sbic.sc_id = 7;
sc->sc_sbic.sc_clkfreq = SEC_CLKFREQ;
sc->sc_sbic.sc_dmamode = SBIC_CTL_BURST_DMA;
sc->sc_sbic.sc_adapter.adapt_request = wd33c93_scsi_request;
sc->sc_sbic.sc_adapter.adapt_minphys = minphys;
sc->sc_sbic.sc_dmasetup = sec_dmasetup;
sc->sc_sbic.sc_dmago = sec_dmago;
sc->sc_sbic.sc_dmastop = sec_dmastop;
sc->sc_sbic.sc_reset = sec_reset;
sc->sc_mpr = 0;
bus_space_write_1(sc->sc_pod_t, sc->sc_pod_h, SEC_MPR, sc->sc_mpr);
for (i = 0; i < SEC_NPAGES; i++) {
sec_setpage(sc, i);
bus_space_set_region_2(sc->sc_mod_t, sc->sc_mod_h,
SEC_SRAM, 0, SEC_PAGESIZE / 2);
}
wd33c93_attach(&sc->sc_sbic);
evcnt_attach_dynamic(&sc->sc_intrcnt, EVCNT_TYPE_INTR, NULL,
device_xname(self), "intr");
sc->sc_ih = podulebus_irq_establish(pa->pa_ih, IPL_BIO, sec_intr,
sc, &sc->sc_intrcnt);
sec_cli(sc);
sc->sc_mpr |= SEC_MPR_IE;
bus_space_write_1(sc->sc_pod_t, sc->sc_pod_h, SEC_MPR, sc->sc_mpr);
pmf_device_register1(sc->sc_sbic.sc_dev, NULL, NULL, sec_shutdown);
}
/*
* Attach the wdsc driver
*/
void
wdsc_attach(struct device *parent, struct device *self, void *aux)
{
struct wdsc_softc *wsc = (struct wdsc_softc *)self;
struct wd33c93_softc *sc = &wsc->sc_wd33c93;
struct hpc_attach_args *haa = aux;
int err;
sc->sc_regt = haa->ha_st;
wsc->sc_dmat = haa->ha_dmat;
wsc->sc_hpcdma.hpc = haa->hpc_regs;
if ((err = bus_space_subregion(haa->ha_st, haa->ha_sh,
haa->ha_devoff + 3, 1, &sc->sc_asr_regh)) != 0) {
printf(": unable to map asr reg, err=%d\n", err);
return;
}
if ((err = bus_space_subregion(haa->ha_st, haa->ha_sh,
haa->ha_devoff + 3 + 4, 1, &sc->sc_data_regh)) != 0) {
printf(": unable to map data reg, err=%d\n", err);
return;
}
if (bus_dmamap_create(wsc->sc_dmat, MAXPHYS,
wsc->sc_hpcdma.hpc->scsi_dma_segs,
wsc->sc_hpcdma.hpc->scsi_dma_segs_size,
wsc->sc_hpcdma.hpc->scsi_dma_segs_size,
BUS_DMA_WAITOK, &wsc->sc_dmamap) != 0) {
printf(": failed to create dmamap\n");
return;
}
sc->sc_dmasetup = wdsc_dmasetup;
sc->sc_dmago = wdsc_dmago;
sc->sc_dmastop = wdsc_dmastop;
sc->sc_reset = wdsc_reset;
sc->sc_id = 0; /* Host ID = 0 */
sc->sc_clkfreq = 200; /* 20MHz */
sc->sc_dmamode = SBIC_CTL_BURST_DMA;
if (hpc_intr_establish(haa->ha_irq, IPL_BIO,
wd33c93_intr, wsc, self->dv_xname) == NULL) {
printf(": unable to establish interrupt!\n");
return;
}
hpcdma_init(haa, &wsc->sc_hpcdma, wsc->sc_hpcdma.hpc->scsi_dma_segs);
wd33c93_attach(sc, &wdsc_switch);
}
static void
tegra_ahcisata_attach(device_t parent, device_t self, void *aux)
{
struct tegra_ahcisata_softc * const sc = device_private(self);
struct tegraio_attach_args * const tio = aux;
const struct tegra_locators * const loc = &tio->tio_loc;
prop_dictionary_t prop = device_properties(self);
const char *pin;
sc->sc_bst = tio->tio_bst;
bus_space_subregion(tio->tio_bst, tio->tio_bsh,
loc->loc_offset, loc->loc_size, &sc->sc_bsh);
sc->sc.sc_atac.atac_dev = self;
sc->sc.sc_dmat = tio->tio_dmat;
sc->sc.sc_ahcit = tio->tio_bst;
sc->sc.sc_ahcis = loc->loc_size - TEGRA_AHCISATA_OFFSET;
bus_space_subregion(tio->tio_bst, tio->tio_bsh,
loc->loc_offset + TEGRA_AHCISATA_OFFSET,
loc->loc_size - TEGRA_AHCISATA_OFFSET, &sc->sc.sc_ahcih);
sc->sc.sc_ahci_quirks = AHCI_QUIRK_SKIP_RESET;
aprint_naive("\n");
aprint_normal(": SATA\n");
if (prop_dictionary_get_cstring_nocopy(prop, "power-gpio", &pin)) {
sc->sc_pin_power = tegra_gpio_acquire(pin, GPIO_PIN_OUTPUT);
if (sc->sc_pin_power)
tegra_gpio_write(sc->sc_pin_power, 1);
}
tegra_car_periph_sata_enable();
tegra_xusbpad_sata_enable();
tegra_ahcisata_init(sc);
sc->sc_ih = intr_establish(loc->loc_intr, IPL_BIO, IST_LEVEL,
ahci_intr, &sc->sc);
if (sc->sc_ih == NULL) {
aprint_error_dev(self, "couldn't establish interrupt %d\n",
loc->loc_intr);
return;
}
aprint_normal_dev(self, "interrupting on irq %d\n", loc->loc_intr);
ahci_attach(&sc->sc);
}
void
ssspi_attach(struct device *parent, struct device *self, void *aux)
{
struct ssspi_softc *sc = (struct ssspi_softc*)self;
struct s3c2xx0_attach_args *sa = (struct s3c2xx0_attach_args *)aux;
bus_space_tag_t iot = sa->sa_iot;
static bus_space_handle_t spi_ioh = 0;
/* we map all registers for SPI0 and SPI1 at once, then
use subregions */
if (spi_ioh == 0) {
if (bus_space_map(iot, S3C2410_SPI0_BASE,
2 * S3C24X0_SPI_SIZE,
0, &spi_ioh)) {
aprint_error(": can't map registers\n");
return;
}
}
aprint_normal("\n");
sc->index = sa->sa_index;
sc->iot = iot;
bus_space_subregion(iot, spi_ioh, sc->index == 0 ? 0 : S3C24X0_SPI_SIZE,
S3C24X0_SPI_SIZE, &sc->ioh);
/*
* Attach child devices
*/
config_search(ssspi_search, self, NULL);
}
int
i80321_io_bs_map(void *t, bus_addr_t bpa, bus_size_t size, int flags,
bus_space_handle_t *bshp)
{
struct i80321_softc *sc = t;
uint32_t busbase;
if (bpa >= sc->sc_ioout_xlate &&
bpa < (sc->sc_ioout_xlate + VERDE_OUT_XLATE_IO_WIN_SIZE)) {
busbase = sc->sc_ioout_xlate;
} else
return (EINVAL);
if ((bpa + size) >= (busbase + VERDE_OUT_XLATE_IO_WIN_SIZE))
return (EINVAL);
/*
* Found the window -- PCI I/O space is mapped at a fixed
* virtual address by board-specific code. Translate the
* bus address to the virtual address.
*/
bus_space_subregion(sc->sc_st, sc->sc_io_sh, (bpa - busbase), size,
bshp);
return (0);
}
static void
exynos_wdt_attach(device_t parent, device_t self, void *aux)
{
struct exynos_wdt_softc * const sc = device_private(self);
struct exyo_attach_args * const exyo = aux;
prop_dictionary_t dict = device_properties(self);
sc->sc_dev = self;
sc->sc_bst = exyo->exyo_core_bst;
if (bus_space_subregion(sc->sc_bst, exyo->exyo_core_bsh,
exyo->exyo_loc.loc_offset, exyo->exyo_loc.loc_size, &sc->sc_wdog_bsh)) {
aprint_error(": failed to map registers\n");
return;
}
/*
* This runs at the Exynos Pclk.
*/
prop_dictionary_get_uint32(dict, "frequency", &sc->sc_freq);
sc->sc_wdog_wtcon = exynos_wdt_wdog_read(sc, EXYNOS_WDT_WTCON);
sc->sc_wdog_armed = (sc->sc_wdog_wtcon & WTCON_ENABLE)
&& (sc->sc_wdog_wtcon & WTCON_RESET_ENABLE);
if (sc->sc_wdog_armed) {
sc->sc_wdog_prescaler =
__SHIFTOUT(sc->sc_wdog_wtcon, WTCON_PRESCALER) + 1;
sc->sc_wdog_clock_select =
__SHIFTOUT(sc->sc_wdog_wtcon, WTCON_CLOCK_SELECT);
sc->sc_freq /= sc->sc_wdog_prescaler;
sc->sc_freq >>= 4 + sc->sc_wdog_clock_select;
sc->sc_wdog_wtdat = exynos_wdt_wdog_read(sc, EXYNOS_WDT_WTDAT);
sc->sc_wdog_period = (sc->sc_wdog_wtdat + 1) / sc->sc_freq;
} else {
void
panel_attach(struct device *parent, struct device *self, void *aux)
{
struct panel_softc *sc = (struct panel_softc *)self;
struct hpc_attach_args *haa = aux;
sc->sc_iot = haa->ha_st;
if (bus_space_subregion(haa->ha_st, haa->ha_sh, haa->ha_devoff + 3, 1,
&sc->sc_ioh)) {
printf(": can't map registers\n");
return;
}
sc->sc_irq = haa->ha_irq;
sc->sc_ih = hpc_intr_establish(sc->sc_irq, IPL_BIO, panel_intr, sc,
sc->sc_dev.dv_xname);
if (sc->sc_ih == NULL) {
printf(": can't establish interrupt\n");
return;
}
if (sys_config.system_subtype == IP22_INDY)
printf(": power and volume buttons\n");
else
printf(": power button\n");
timeout_set(&sc->sc_repeat_tmo, panel_repeat, sc);
}
static void
joy_isapnp_attach(device_t parent, device_t self, void *aux)
{
struct joy_softc *sc = device_private(self);
struct isapnp_attach_args *ipa = aux;
bus_space_handle_t ioh;
aprint_normal("\n");
if (isapnp_config(ipa->ipa_iot, ipa->ipa_memt, ipa)) {
aprint_error_dev(self, "error in region allocation\n");
return;
}
if (ipa->ipa_io[0].length == 8) {
if (bus_space_subregion(ipa->ipa_iot, ipa->ipa_io[0].h, 1, 1,
&ioh) < 0) {
aprint_error_dev(self, "error in region allocation\n");
return;
}
} else
ioh = ipa->ipa_io[0].h;
sc->sc_iot = ipa->ipa_iot;
sc->sc_ioh = ioh;
sc->sc_dev = self;
aprint_normal_dev(self, "%s %s\n", ipa->ipa_devident,
ipa->ipa_devclass);
joyattach(sc);
}
static void
obiouart_attach(device_t parent, device_t self, void *aux)
{
struct com_obio_softc *osc = device_private(self);
struct com_softc *sc = &osc->sc_sc;
struct obio_attach_args *obio = aux;
bus_space_tag_t bst;
bus_space_handle_t bsh = 0;
bus_addr_t iobase;
sc->sc_dev = self;
bst = obio->obio_bst;
iobase = obio->obio_base + obio->obio_offset;
sc->sc_frequency = ROCKCHIP_UART_FREQ;
sc->sc_type = COM_TYPE_NORMAL;
if (com_is_console(bst, iobase, &bsh) == 0 &&
bus_space_subregion(bst, obio->obio_bsh, obio->obio_size, 0, &bsh)) {
panic(": can't map registers\n");
return;
}
COM_INIT_REGS(sc->sc_regs, bst, bsh, iobase);
com_attach_subr(sc);
aprint_naive("\n");
KASSERT(obio->obio_intr != OBIOCF_INTR_DEFAULT);
osc->sc_ih = intr_establish(obio->obio_intr, IPL_SERIAL, IST_LEVEL,
comintr, sc);
if (osc->sc_ih == NULL)
panic("%s: failed to establish interrup %d",
device_xname(self), obio->obio_intr);
}
int
ne_neptune_match(device_t parent, cfdata_t match, void *aux)
{
struct neptune_attach_args *na = aux;
bus_space_tag_t nict = na->na_bst;
bus_space_handle_t nich;
bus_space_tag_t asict;
bus_space_handle_t asich;
int rv = 0;
if (na->na_addr == NEPTUNECF_ADDR_DEFAULT)
na->na_addr = 0x300;
/* Make sure this is a valid NE[12]000 i/o address. */
if ((na->na_addr & 0x1f) != 0)
return (0);
/* Map i/o space. */
if (bus_space_map(nict, na->na_addr, NE2000_NPORTS*2, 0, &nich))
return (0);
asict = nict;
if (bus_space_subregion(nict, nich, NE2000_ASIC_OFFSET,
NE2000_ASIC_NPORTS*2, &asich))
goto out;
/* Look for an NE2000-compatible card. */
rv = ne2000_detect(nict, nich, asict, asich);
out:
bus_space_unmap(nict, nich, NE2000_NPORTS);
return (rv != 0) ? 1 : 0;
}
static void
awin_tve_attach(device_t parent, device_t self, void *aux)
{
struct awin_tve_softc *sc = device_private(self);
struct awinio_attach_args * const aio = aux;
const struct awin_locators * const loc = &aio->aio_loc;
prop_dictionary_t cfg = device_properties(self);
int8_t tcon_unit = -1;
sc->sc_dev = self;
sc->sc_bst = aio->aio_core_bst;
bus_space_subregion(sc->sc_bst, aio->aio_core_bsh,
loc->loc_offset, loc->loc_size, &sc->sc_bsh);
if (prop_dictionary_get_int8(cfg, "tcon_unit", &tcon_unit)) {
sc->sc_tcon_unit = tcon_unit;
} else {
sc->sc_tcon_unit = 0; /* default value */
}
sc->sc_tcon_pll = awin_tcon_get_clk_pll(sc->sc_tcon_unit);
switch (sc->sc_tcon_pll) {
case 3:
awin_pll3_enable();
break;
case 7:
awin_pll7_enable();
break;
default:
panic("awin_tve pll");
}
/* for now assume we're always at 0 */
awin_reg_set_clear(aio->aio_core_bst, aio->aio_ccm_bsh,
AWIN_AHB_GATING1_REG, AWIN_AHB_GATING1_TVE0, 0);
aprint_naive("\n");
aprint_normal(": TV Encoder / VGA output\n");
if (tcon_unit >= 0) {
aprint_verbose_dev(self, ": using TCON%d, pll%d\n",
sc->sc_tcon_unit, sc->sc_tcon_pll);
}
sc->sc_i2c_blklen = 16;
#if 0
sc->sc_ih = intr_establish(loc->loc_intr, IPL_SCHED, IST_LEVEL,
awin_tve_intr, sc);
if (sc->sc_ih == NULL) {
aprint_error_dev(self, "couldn't establish interrupt %d\n",
loc->loc_intr);
return;
}
aprint_normal_dev(self, "interrupting on irq %d\n", loc->loc_intr);
#endif
awin_tve_i2c_init(sc);
awin_tve_enable(sc);
awin_tve_read_edid(sc);
}
void
mcclock_mace_attach(struct device *parent, struct device *self, void *aux)
{
struct mcclock_mace_softc *sc = (void *)self;
struct mace_attach_args *maa = aux;
sc->sc_st = maa->maa_st;
/* XXX should be bus_space_map() */
if (bus_space_subregion(maa->maa_st, maa->maa_sh,
maa->maa_offset, 0, &sc->sc_sh))
panic("mcclock_mace_attach: couldn't map");
/*
* We want a fixed format: 24-hour, BCD data, so just force the
* RTC to this mode; if there was junk there we'll be able to
* fix things up later when we discover the time read back is
* no good.
*/
ds1687_write(sc, DS1687_CONTROLA, DS1687_DV1 | DS1687_BANK1);
ds1687_write(sc, DS1687_CONTROLB, DS1687_24HRS);
/* XXXrkb: init kickstart/wakeup stuff */
if (!(ds1687_read(sc, DS1687_CONTROLD) & DS1687_VRT))
printf(": lithium cell is dead, RTC unreliable");
printf("\n");
clockattach(&sc->sc_dev, &mcclock_mace_clockfns);
}
static void
amlogic_com_attach(device_t parent, device_t self, void *aux)
{
struct amlogic_com_softc * const asc = device_private(self);
struct com_softc * const sc = &asc->asc_sc;
struct amlogicio_attach_args * const aio = aux;
const struct amlogic_locators * const loc = &aio->aio_loc;
bus_space_tag_t iot = aio->aio_core_a4x_bst;
const bus_addr_t iobase = AMLOGIC_CORE_BASE + loc->loc_offset;
bus_space_handle_t ioh;
amlogic_com_ports |= __BIT(loc->loc_port);
sc->sc_dev = self;
sc->sc_frequency = AMLOGIC_UART_FREQ;
sc->sc_type = COM_TYPE_NORMAL;
if (com_is_console(iot, iobase, &ioh) == 0
&& bus_space_subregion(iot, aio->aio_bsh,
loc->loc_offset / 4, loc->loc_size, &ioh)) {
panic(": can't map registers");
}
COM_INIT_REGS(sc->sc_regs, iot, ioh, iobase);
com_attach_subr(sc);
aprint_naive("\n");
KASSERT(loc->loc_intr != AMLOGICIO_INTR_DEFAULT);
asc->asc_ih = intr_establish(loc->loc_intr, IPL_SERIAL,
IST_EDGE | IST_MPSAFE, comintr, sc);
if (asc->asc_ih == NULL)
panic("%s: failed to establish interrupt %d",
device_xname(self), loc->loc_intr);
}
int
tslot_mem_map(pcmcia_chipset_handle_t pch, int kind, bus_addr_t addr,
bus_size_t size, struct pcmcia_mem_handle *pmh, bus_size_t *offsetp,
int *windowp)
{
struct tslot_data *td = (struct tslot_data *)pch;
int slot;
slot = kind & PCMCIA_MEM_ATTR ? TS102_RANGE_ATTR : TS102_RANGE_COMMON;
#ifdef TSLOT_DEBUG
printf("[mem map %d %x-%x", slot, addr, size);
#endif
addr += pmh->addr;
pmh->memt = &td->td_rr;
bus_space_subregion(&td->td_rr, td->td_space[slot],
addr, size, &pmh->memh);
pmh->realsize = TS102_ARBITRARY_MAP_SIZE - addr;
*offsetp = 0;
*windowp = slot;
#ifdef TSLOT_DEBUG
printf("->%p/%x]", pmh->memh, size);
#endif
return (0);
}
static struct resource *
mvs_alloc_resource(device_t dev, device_t child, int type, int *rid,
u_long start, u_long end, u_long count, u_int flags)
{
struct mvs_controller *ctlr = device_get_softc(dev);
int unit = ((struct mvs_channel *)device_get_softc(child))->unit;
struct resource *res = NULL;
int offset = PORT_BASE(unit & 0x03);
long st;
switch (type) {
case SYS_RES_MEMORY:
st = rman_get_start(ctlr->r_mem);
res = rman_reserve_resource(&ctlr->sc_iomem, st + offset,
st + offset + PORT_SIZE - 1, PORT_SIZE, RF_ACTIVE, child);
if (res) {
bus_space_handle_t bsh;
bus_space_tag_t bst;
bsh = rman_get_bushandle(ctlr->r_mem);
bst = rman_get_bustag(ctlr->r_mem);
bus_space_subregion(bst, bsh, offset, PORT_SIZE, &bsh);
rman_set_bushandle(res, bsh);
rman_set_bustag(res, bst);
}
break;
case SYS_RES_IRQ:
if (*rid == ATA_IRQ_RID)
res = ctlr->irq.r_irq;
break;
}
return (res);
}
static int
ne_mainbus_match(device_t parent, cfdata_t cf, void *aux)
{
struct mainbus_attach_args *maa = (struct mainbus_attach_args *)aux;
bus_space_tag_t nict = &t_sh7706lan_bus_io;
bus_space_handle_t nich;
bus_space_tag_t asict;
bus_space_handle_t asich;
int rv = 0;
if (strcmp(maa->ma_name, "ne") != 0)
return 0;
/* Map i/o space. */
if (bus_space_map(nict, 0x10000300, NE2000_NPORTS, 0, &nich))
return 0;
asict = nict;
if (bus_space_subregion(nict, nich, NE2000_ASIC_OFFSET,
NE2000_ASIC_NPORTS, &asich))
goto out;
/* Look for an NE2000-compatible card. */
rv = ne2000_detect(nict, nich, asict, asich);
out:
bus_space_unmap(nict, nich, NE2000_NPORTS);
return rv;
}
int
com_ioc_probe(struct device *parent, void *match, void *aux)
{
struct cfdata *cf = match;
struct ioc_attach_args *iaa = aux;
bus_space_tag_t iot = iaa->iaa_memt;
bus_space_handle_t ioh;
int rv = 0, console = 0;
if (strcmp(iaa->iaa_name, com_cd.cd_name) != 0)
return 0;
if (comconsiot != NULL)
console = iaa->iaa_memh + iaa->iaa_base ==
comconsiot->bus_base + comconsaddr;
/* if it's in use as console, it's there. */
if (!(console && !comconsattached)) {
if (bus_space_subregion(iot, iaa->iaa_memh,
iaa->iaa_base, COM_NPORTS, &ioh) == 0)
rv = comprobe1(iot, ioh);
} else
rv = 1;
/* make a config stanza with exact locators match over a generic line */
if (cf->cf_loc[0] != -1)
rv += rv;
return rv;
}
static int
at91st_attach(device_t dev)
{
struct at91_softc *sc = device_get_softc(device_get_parent(dev));
timer_softc = device_get_softc(dev);
timer_softc->sc_st = sc->sc_st;
timer_softc->sc_dev = dev;
if (bus_space_subregion(sc->sc_st, sc->sc_sh, AT91RM92_ST_BASE,
AT91RM92_ST_SIZE, &timer_softc->sc_sh) != 0)
panic("couldn't subregion timer registers");
/*
* Real time counter increments every clock cycle, need to set before
* initializing clocks so that DELAY works.
*/
WR4(ST_RTMR, 1);
/* Disable all interrupts */
WR4(ST_IDR, 0xffffffff);
/* disable watchdog timer */
WR4(ST_WDMR, 0);
timer_softc->sc_wet = EVENTHANDLER_REGISTER(watchdog_list,
at91st_watchdog, dev, 0);
device_printf(dev,
"watchdog registered, timeout intervall max. 64 sec\n");
return (0);
}
static int
ebus_activate_resource(device_t bus, device_t child, int type, int rid,
struct resource *res)
{
struct ebus_softc *sc;
struct ebus_rinfo *eri;
bus_space_tag_t bt;
bus_space_handle_t bh;
int i, rv;
sc = device_get_softc(bus);
if ((sc->sc_flags & EBUS_PCI) != 0 && type == SYS_RES_MEMORY) {
for (i = 0; i < sc->sc_nrange; i++) {
eri = &sc->sc_rinfo[i];
if (rman_is_region_manager(res, &eri->eri_rman) != 0) {
bt = rman_get_bustag(eri->eri_res);
rv = bus_space_subregion(bt,
rman_get_bushandle(eri->eri_res),
rman_get_start(res) -
rman_get_start(eri->eri_res),
rman_get_size(res), &bh);
if (rv != 0)
return (rv);
rman_set_bustag(res, bt);
rman_set_bushandle(res, bh);
return (rman_activate_resource(res));
}
}
return (EINVAL);
}
return (bus_generic_activate_resource(bus, child, type, rid, res));
}
static void
bcmmdio_ccb_attach(device_t parent, device_t self, void *aux)
{
struct bcmmdio_softc * const sc = device_private(self);
struct bcmccb_attach_args * const ccbaa = aux;
const struct bcm_locators * const loc = &ccbaa->ccbaa_loc;
sc->sc_dev = self;
sc->sc_bst = ccbaa->ccbaa_ccb_bst;
sc->sc_lock = mutex_obj_alloc(MUTEX_DEFAULT, IPL_VM);
bus_space_subregion(sc->sc_bst, ccbaa->ccbaa_ccb_bsh,
loc->loc_offset, loc->loc_size, &sc->sc_bsh);
uint32_t miimgt = bcmmdio_read_4(sc, MIIMGT);
uint32_t div = __SHIFTOUT(miimgt, MIIMGT_MDCDIV);
if (div == 0) {
div = 33; // divisor to get 2MHz
miimgt &= ~MIIMGT_MDCDIV;
miimgt |= __SHIFTIN(div, MIIMGT_MDCDIV);
bcmmdio_write_4(sc, MIIMGT, miimgt);
}
uint32_t freq = 66000000 / div;
aprint_naive("\n");
aprint_normal(": MDIO bus @ %u MHz\n", freq / 1000000);
}
static int
at91pit_attach(device_t dev)
{
struct at91_softc *sc = device_get_softc(device_get_parent(dev));
struct resource *irq;
int rid = 0;
void *ih;
pit_softc = device_get_softc(dev);
pit_softc->sc_st = sc->sc_st;
pit_softc->sc_dev = dev;
if (bus_space_subregion(sc->sc_st, sc->sc_sh, at91_pit_base(),
at91_pit_size(), &pit_softc->sc_sh) != 0)
panic("couldn't subregion pit registers");
irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 1, 1, 1,
RF_ACTIVE | RF_SHAREABLE);
if (!irq)
panic("Unable to allocate IRQ for the system timer");
else
bus_setup_intr(dev, irq, INTR_TYPE_CLK,
clock_intr, NULL, NULL, &ih);
device_printf(dev, "AT91SAM9x pit registered\n");
return (0);
}
static void
sii3114_mapchan(struct pciide_channel *cp)
{
struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.ch_wdc;
struct wdc_channel *wdc_cp = &cp->wdc_channel;
int i;
cp->compat = 0;
cp->ih = sc->sc_pci_ih;
wdc_cp->cmd_iot = sc->sc_ba5_st;
if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh,
satalink_ba5_regmap[wdc_cp->ch_channel].ba5_IDE_TF0,
9, &wdc_cp->cmd_baseioh) != 0) {
aprint_error("%s: couldn't subregion %s cmd base\n",
sc->sc_wdcdev.sc_dev.dv_xname, cp->name);
goto bad;
}
wdc_cp->ctl_iot = sc->sc_ba5_st;
if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh,
satalink_ba5_regmap[wdc_cp->ch_channel].ba5_IDE_TF8,
1, &cp->ctl_baseioh) != 0) {
aprint_error("%s: couldn't subregion %s ctl base\n",
sc->sc_wdcdev.sc_dev.dv_xname, cp->name);
goto bad;
}
wdc_cp->ctl_ioh = cp->ctl_baseioh;
for (i = 0; i < WDC_NREG; i++) {
if (bus_space_subregion(wdc_cp->cmd_iot, wdc_cp->cmd_baseioh,
i, i == 0 ? 4 : 1,
&wdc_cp->cmd_iohs[i]) != 0) {
aprint_error("%s: couldn't subregion %s channel "
"cmd regs\n",
sc->sc_wdcdev.sc_dev.dv_xname, cp->name);
goto bad;
}
}
wdc_cp->data32iot = wdc_cp->cmd_iot;
wdc_cp->data32ioh = wdc_cp->cmd_iohs[0];
wdcattach(wdc_cp);
return;
bad:
cp->wdc_channel.ch_flags |= WDCF_DISABLED;
}
static int
wdc_obio_probe(device_t parent, cfdata_t cfp, void *aux)
{
struct obio_attach_args *oa = aux;
struct ata_channel ch;
struct wdc_softc wdc;
struct wdc_regs wdr;
int result = 0;
int i;
if (oa->oa_nio < 1)
return (0);
if (oa->oa_nirq < 1)
return (0);
if (oa->oa_io[0].or_addr == IOBASEUNK)
return (0);
if (oa->oa_irq[0].or_irq == IRQUNK)
return (0);
memset(&wdc, 0, sizeof(wdc));
memset(&ch, 0, sizeof(ch));
ch.ch_atac = &wdc.sc_atac;
wdc.regs = &wdr;
wdr.cmd_iot = oa->oa_iot;
if (bus_space_map(wdr.cmd_iot, oa->oa_io[0].or_addr,
WDC_OBIO_REG_SIZE, 0, &wdr.cmd_baseioh)) {
goto out;
}
for (i = 0; i < WDC_OBIO_REG_NPORTS; i++) {
if (bus_space_subregion(wdr.cmd_iot, wdr.cmd_baseioh,
i * 2, (i == 0) ? 2 : 1, &wdr.cmd_iohs[i])) {
goto outunmap;
}
}
wdc_init_shadow_regs(&ch);
wdr.ctl_iot = oa->oa_iot;
if (bus_space_map(wdr.ctl_iot,
oa->oa_io[0].or_addr + WDC_OBIO_AUXREG_OFFSET,
WDC_OBIO_AUXREG_SIZE, 0, &wdr.ctl_ioh)) {
goto outunmap;
}
result = wdcprobe(&ch);
if (result) {
oa->oa_nio = 1;
oa->oa_io[0].or_size = WDC_OBIO_REG_SIZE;
oa->oa_nirq = 1;
oa->oa_niomem = 0;
}
bus_space_unmap(wdr.ctl_iot, wdr.ctl_ioh, WDC_OBIO_AUXREG_SIZE);
outunmap:
bus_space_unmap(wdr.cmd_iot, wdr.cmd_baseioh, WDC_OBIO_REG_SIZE);
out:
return (result);
}
/*
* Install interface into kernel networking data structures.
*/
void
ne_xsurf_attach(device_t parent, device_t self, void *aux)
{
struct ne_xsurf_softc *zsc = device_private(self);
struct ne2000_softc *nsc = &zsc->sc_ne2000;
struct dp8390_softc *dsc = &nsc->sc_dp8390;
struct xsurfbus_attach_args *xap = aux;
bus_space_tag_t nict = &zsc->sc_bst;
bus_space_handle_t nich;
bus_space_tag_t asict = nict;
bus_space_handle_t asich;
dsc->sc_dev = self;
dsc->sc_mediachange = rtl80x9_mediachange;
dsc->sc_mediastatus = rtl80x9_mediastatus;
dsc->init_card = rtl80x9_init_card;
dsc->sc_media_init = rtl80x9_media_init;
zsc->sc_bst.base = xap->xaa_base;
zsc->sc_bst.absm = &amiga_bus_stride_2;
aprint_normal("\n");
/* Map i/o space. */
if (bus_space_map(nict, NE_XSURF_NICBASE,
NE_XSURF_NPORTS, 0, &nich)) {
aprint_error_dev(self, "can't map nic i/o space\n");
return;
}
if (bus_space_subregion(nict, nich, NE2000_ASIC_OFFSET,
NE_XSURF_ASICSIZE, &asich)) {
aprint_error_dev(self, "can't map asic i/o space\n");
return;
}
dsc->sc_regt = nict;
dsc->sc_regh = nich;
nsc->sc_asict = asict;
nsc->sc_asich = asich;
/* This interface is always enabled. */
dsc->sc_enabled = 1;
/*
* Do generic NE2000 attach. This will read the station address
* from the EEPROM.
*/
ne2000_attach(nsc, NULL);
zsc->sc_isr.isr_intr = dp8390_intr;
zsc->sc_isr.isr_arg = dsc;
zsc->sc_isr.isr_ipl = 2;
add_isr(&zsc->sc_isr);
}
static void
awin_otg_attach(device_t parent, device_t self, void *aux)
{
struct awin_otg_softc *sc = device_private(self);
struct awinio_attach_args * const aio = aux;
const struct awin_locators * const loc = &aio->aio_loc;
aprint_naive("\n");
aprint_normal(": OTG\n");
if (awin_chip_id() == AWIN_CHIP_ID_A31) {
awin_reg_set_clear(aio->aio_core_bst, aio->aio_ccm_bsh,
AWIN_USB_CLK_REG,
AWIN_A31_USB_CLK_USBPHY0_ENABLE |
AWIN_A31_USB_CLK_PHY0_ENABLE, 0);
awin_reg_set_clear(aio->aio_core_bst, aio->aio_ccm_bsh,
AWIN_AHB_GATING0_REG, AWIN_A31_AHB_GATING0_USB0, 0);
awin_reg_set_clear(aio->aio_core_bst, aio->aio_ccm_bsh,
AWIN_A31_AHB_RESET0_REG, AWIN_A31_AHB_RESET0_USBOTG_RST, 0);
} else {
awin_reg_set_clear(aio->aio_core_bst, aio->aio_ccm_bsh,
AWIN_AHB_GATING0_REG, AWIN_AHB_GATING0_USB0, 0);
awin_reg_set_clear(aio->aio_core_bst, aio->aio_ccm_bsh,
AWIN_USB_CLK_REG,
AWIN_USB_CLK_USBPHY_ENABLE|AWIN_USB_CLK_PHY0_ENABLE, 0);
awin_reg_set_clear(aio->aio_core_bst, aio->aio_core_bsh,
AWIN_SRAM_OFFSET + AWIN_SRAM_CTL1_REG,
__SHIFTIN(AWIN_SRAM_CTL1_SRAMD_MAP_USB0,
AWIN_SRAM_CTL1_SRAMD_MAP),
0);
}
sc->sc_motg.sc_dev = self;
sc->sc_motg.sc_bus.dmatag = aio->aio_dmat;
sc->sc_motg.sc_iot = aio->aio_core_bst;
bus_space_subregion(sc->sc_motg.sc_iot, aio->aio_core_bsh,
loc->loc_offset, loc->loc_size, &sc->sc_motg.sc_ioh);
sc->sc_motg.sc_size = loc->loc_size;
sc->sc_motg.sc_intr_poll = awin_otg_poll;
sc->sc_motg.sc_intr_poll_arg = sc;
sc->sc_motg.sc_mode = MOTG_MODE_HOST;
sc->sc_motg.sc_ep_max = 5;
sc->sc_motg.sc_ep_fifosize = 512;
sc->sc_ih = intr_establish(loc->loc_intr, IPL_USB, IST_LEVEL,
awin_otg_intr, sc);
if (sc->sc_ih == NULL) {
aprint_error_dev(self, "couldn't establish interrupt %d\n",
loc->loc_intr);
return;
}
device_printf(self, "interrupting at irq %d\n", loc->loc_intr);
awin_otg_init(sc);
motg_init(&sc->sc_motg);
}
static void
panel_attach(device_t parent, device_t self, void *aux)
{
struct panel_softc *sc = device_private(self);
struct mainbus_attach_args *maa = aux;
struct hd44780_io io;
static struct lcdkp_xlate keys[] = {
{ 0xfa, 'h' },
{ 0xf6, 'k' },
{ 0xde, 'l' },
{ 0xee, 'j' },
{ 0x7e, 's' },
{ 0xbe, 'e' }
};
sc->sc_lcd.sc_dev = self;
sc->sc_lcd.sc_iot = maa->ma_iot;
if (bus_space_map(sc->sc_lcd.sc_iot, maa->ma_addr, PANEL_REGION,
0, &sc->sc_lcd.sc_ioir)) {
aprint_error(": unable to map registers\n");
return;
}
bus_space_subregion(sc->sc_lcd.sc_iot, sc->sc_lcd.sc_ioir, DATA_OFFSET,
1, &sc->sc_lcd.sc_iodr);
printf("\n");
sc->sc_lcd.sc_dev_ok = 1;
sc->sc_lcd.sc_cols = PANEL_COLS;
sc->sc_lcd.sc_vcols = PANEL_VCOLS;
sc->sc_lcd.sc_flags = HD_8BIT | HD_MULTILINE | HD_KEYPAD;
sc->sc_lcd.sc_writereg = panel_cbt_hdwritereg;
sc->sc_lcd.sc_readreg = panel_cbt_hdreadreg;
hd44780_attach_subr(&sc->sc_lcd);
/* Hello World */
io.dat = 0;
io.len = PANEL_VCOLS * PANEL_ROWS;
memcpy(io.buf, &startup_message, io.len);
hd44780_ddram_io(&sc->sc_lcd, sc->sc_lcd.sc_curchip, &io,
HD_DDRAM_WRITE);
pmf_device_register1(self, NULL, NULL, panel_shutdown);
sc->sc_kp.sc_iot = maa->ma_iot;
sc->sc_kp.sc_ioh = MIPS_PHYS_TO_KSEG1(PANEL_BASE); /* XXX */
sc->sc_kp.sc_knum = sizeof(keys) / sizeof(struct lcdkp_xlate);
sc->sc_kp.sc_kpad = keys;
sc->sc_kp.sc_rread = panel_cbt_kprread;
lcdkp_attach_subr(&sc->sc_kp);
callout_init(&sc->sc_callout, 0);
selinit(&sc->sc_selq);
}
/* ARGSUSED */
static void
mvsoctmr_attach(device_t parent, device_t self, void *aux)
{
struct mvsoctmr_softc *sc = device_private(self);
struct marvell_attach_args *mva = aux;
uint32_t rstoutn;
aprint_naive("\n");
aprint_normal(": Marvell SoC Timer\n");
if (mvsoctmr_sc == NULL)
mvsoctmr_sc = sc;
sc->sc_dev = self;
sc->sc_iot = mva->mva_iot;
if (bus_space_subregion(mva->mva_iot, mva->mva_ioh,
mva->mva_offset, mva->mva_size, &sc->sc_ioh))
panic("%s: Cannot map registers", device_xname(self));
sc->sc_irq = mva->mva_irq;
switch (mva->mva_model) {
case MARVELL_ARMADAXP_MV78130:
case MARVELL_ARMADAXP_MV78160:
case MARVELL_ARMADAXP_MV78230:
case MARVELL_ARMADAXP_MV78260:
case MARVELL_ARMADAXP_MV78460:
sc->sc_flags = TMR_FLAGS_ARMADAXP;
break;
}
mvsoctmr_timecounter.tc_name = device_xname(self);
mvsoctmr_cntl(sc, MVSOCTMR_TIMER1, 0xffffffff, 1, 1);
/*
* stop watchdog timer, enable watchdog timer resets
*/
mvsoctmr_cntl(sc, MVSOCTMR_WATCHDOG, 0xffffffff, 0, 0);
write_mlmbreg(MVSOC_MLMB_MLMBICR,
~(1<<MVSOC_MLMB_MLMBI_CPUWDTIMERINTREQ));
rstoutn = read_mlmbreg(MVSOC_MLMB_RSTOUTNMASKR);
write_mlmbreg(MVSOC_MLMB_RSTOUTNMASKR,
rstoutn | MVSOC_MLMB_RSTOUTNMASKR_WDRSTOUTEN);
#ifdef DDB
db_trap_callback = mvsoctmr_wdog_ddb_trap;
#endif
sc->sc_wdog.smw_name = device_xname(self);
sc->sc_wdog.smw_cookie = sc;
sc->sc_wdog.smw_setmode = mvsoctmr_wdog_setmode;
sc->sc_wdog.smw_tickle = mvsoctmr_wdog_tickle;
sc->sc_wdog.smw_period = MVSOC_WDOG_MAX_PERIOD;
if (sysmon_wdog_register(&sc->sc_wdog) != 0)
aprint_error_dev(self,
"unable to register watchdog with sysmon\n");
}
int
agp_map_subregion(struct agp_map *map, bus_size_t offset, bus_size_t size,
bus_space_handle_t *bshp)
{
if (offset > map->size || size > map->size || offset + size > map->size)
return (EINVAL);
return (bus_space_subregion(map->bst, map->bsh, offset, size, bshp));
}
