uint64_t get_psw_mask(CPUS390XState *env) { uint64_t r = env->psw.mask; if (tcg_enabled()) { env->cc_op = calc_cc(env, env->cc_op, env->cc_src, env->cc_dst, env->cc_vr); r &= ~PSW_MASK_CC; assert(!(env->cc_op & ~3)); r |= (uint64_t)env->cc_op << 44; } return r; }
int s390_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) { S390CPU *cpu = S390_CPU(cs); CPUS390XState *env = &cpu->env; uint64_t val; int cc_op; switch (n) { case S390_PSWM_REGNUM: if (tcg_enabled()) { cc_op = calc_cc(env, env->cc_op, env->cc_src, env->cc_dst, env->cc_vr); val = deposit64(env->psw.mask, 44, 2, cc_op); return gdb_get_regl(mem_buf, val); } return gdb_get_regl(mem_buf, env->psw.mask); case S390_PSWA_REGNUM: return gdb_get_regl(mem_buf, env->psw.addr); case S390_R0_REGNUM ... S390_R15_REGNUM: return gdb_get_regl(mem_buf, env->regs[n - S390_R0_REGNUM]); } return 0; }