ulong fpga_control (fpga_t* fpga, int cmd)
{
volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
volatile memctl8xx_t *memctl = &immr->im_memctl;
switch (cmd) {
case FPGA_INIT_IS_HIGH:
immr->im_ioport.iop_pcdir &= ~fpga->init_mask; /* input */
return (immr->im_ioport.iop_pcdat & fpga->init_mask) ? 1:0;
case FPGA_INIT_SET_LOW:
immr->im_ioport.iop_pcdir |= fpga->init_mask; /* output */
immr->im_ioport.iop_pcdat &= ~fpga->init_mask;
break;
case FPGA_INIT_SET_HIGH:
immr->im_ioport.iop_pcdir |= fpga->init_mask; /* output */
immr->im_ioport.iop_pcdat |= fpga->init_mask;
break;
case FPGA_PROG_SET_LOW:
immr->im_ioport.iop_pcdat &= ~fpga->prog_mask;
break;
case FPGA_PROG_SET_HIGH:
immr->im_ioport.iop_pcdat |= fpga->prog_mask;
break;
case FPGA_DONE_IS_HIGH:
return (immr->im_ioport.iop_pcdat & fpga->done_mask) ? 1:0;
case FPGA_READ_MODE:
/* disable FPGA in memory controller */
memctl->memc_br4 = 0;
memctl->memc_or4 = PUMA_CONF_OR_READ;
memctl->memc_br4 = PUMA_CONF_BR_READ;
/* (re-) enable CAN drivers */
can_driver_enable ();
break;
case FPGA_LOAD_MODE:
/* disable FPGA in memory controller */
memctl->memc_br4 = 0;
/*
* We must disable the CAN drivers first because
* they use UPM B, too.
*/
can_driver_disable ();
/*
* Configure UPMB for FPGA
*/
upmconfig(UPMB,(uint *)puma_table,sizeof(puma_table)/sizeof(uint));
memctl->memc_or4 = PUMA_CONF_OR_LOAD;
memctl->memc_br4 = PUMA_CONF_BR_LOAD;
break;
case FPGA_GET_ID:
return *(volatile ulong *)fpga->conf_base;
case FPGA_INIT_PORTS:
immr->im_ioport.iop_pcpar &= ~fpga->init_mask; /* INIT I/O */
immr->im_ioport.iop_pcso &= ~fpga->init_mask;
immr->im_ioport.iop_pcdir &= ~fpga->init_mask;
immr->im_ioport.iop_pcpar &= ~fpga->prog_mask; /* PROG Output */
immr->im_ioport.iop_pcso &= ~fpga->prog_mask;
immr->im_ioport.iop_pcdir |= fpga->prog_mask;
immr->im_ioport.iop_pcpar &= ~fpga->done_mask; /* DONE Input */
immr->im_ioport.iop_pcso &= ~fpga->done_mask;
immr->im_ioport.iop_pcdir &= ~fpga->done_mask;
break;
}
return 0;
}
long int initdram (int board_type)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
long int size8, size9;
long int size = 0;
unsigned long reg;
upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
/*
* Preliminary prescaler for refresh (depends on number of
* banks): This value is selected for four cycles every 62.4 us
* with two SDRAM banks or four cycles every 31.2 us with one
* bank. It will be adjusted after memory sizing.
*/
memctl->memc_mptpr = CFG_MPTPR_2BK_8K;
memctl->memc_mar = 0x00000088;
/*
* Map controller banks 2 and 3 to the SDRAM banks 2 and 3 at
* preliminary addresses - these have to be modified after the
* SDRAM size has been determined.
*/
memctl->memc_or2 = CFG_OR2_PRELIM;
memctl->memc_br2 = CFG_BR2_PRELIM;
memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */
udelay(200);
/* perform SDRAM initializsation sequence */
memctl->memc_mcr = 0x80004105; /* SDRAM bank 0 */
udelay(1);
memctl->memc_mcr = 0x80004230; /* SDRAM bank 0 - execute twice */
udelay(1);
memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
udelay (1000);
/*
* Check Bank 0 Memory Size for re-configuration
*
* try 8 column mode
*/
size8 = dram_size (CFG_MAMR_8COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
udelay (1000);
/*
* try 9 column mode
*/
size9 = dram_size (CFG_MAMR_9COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
if (size8 < size9) { /* leave configuration at 9 columns */
size = size9;
/* debug ("SDRAM in 9 column mode: %ld MB\n", size >> 20); */
} else { /* back to 8 columns */
size = size8;
memctl->memc_mamr = CFG_MAMR_8COL;
udelay(500);
/* debug ("SDRAM in 8 column mode: %ld MB\n", size >> 20); */
}
udelay (1000);
/*
* Adjust refresh rate depending on SDRAM type
* For types > 128 MBit leave it at the current (fast) rate
*/
if (size < 0x02000000) {
/* reduce to 15.6 us (62.4 us / quad) */
memctl->memc_mptpr = CFG_MPTPR_2BK_4K;
udelay(1000);
}
/*
* Final mapping
*/
memctl->memc_or2 = ((-size) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
memctl->memc_br2 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
/* adjust refresh rate depending on SDRAM type, one bank */
reg = memctl->memc_mptpr;
reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */
memctl->memc_mptpr = reg;
can_driver_enable ();
init_leds ();
udelay(10000);
return (size);
}
