int re_cardbus_enable(struct rtk_softc *sc) { struct re_cardbus_softc *csc = (struct re_cardbus_softc *)sc; cardbus_devfunc_t ct = csc->sc_ct; cardbus_chipset_tag_t cc = ct->ct_cc; cardbus_function_tag_t cf = ct->ct_cf; /* * Power on the socket. */ Cardbus_function_enable(ct); /* * Set up the PCI configuration registers. */ re_cardbus_setup(csc); /* * Map and establish the interrupt. */ csc->sc_ih = cardbus_intr_establish(cc, cf, csc->sc_intrline, IPL_NET, re_intr, sc); if (csc->sc_ih == NULL) { aprint_error_dev(sc->sc_dev, "unable to establish interrupt\n"); Cardbus_function_disable(csc->sc_ct); return 1; } return 0; }
int com_cardbus_enable(struct com_softc *sc) { struct com_cardbus_softc *csc = (struct com_cardbus_softc*)sc; struct cardbus_softc *psc = (struct cardbus_softc *)sc->sc_dev.dv_parent; cardbus_chipset_tag_t cc = psc->sc_cc; cardbus_function_tag_t cf = psc->sc_cf; Cardbus_function_enable(csc->cc_ct); com_cardbus_setup(csc); /* establish the interrupt. */ csc->cc_ih = cardbus_intr_establish(cc, cf, psc->sc_intrline, IPL_TTY, comintr, sc, DEVNAME(csc)); if (csc->cc_ih == NULL) { printf("%s: couldn't establish interrupt\n", DEVNAME(csc)); return (1); } printf(": irq %d", psc->sc_intrline); return (0); }
int pgt_cardbus_enable(struct pgt_softc *sc) { struct pgt_cardbus_softc *csc = (struct pgt_cardbus_softc *)sc; cardbus_devfunc_t ct = csc->sc_ct; cardbus_chipset_tag_t cc = ct->ct_cc; cardbus_function_tag_t cf = ct->ct_cf; /* power on the socket */ Cardbus_function_enable(ct); /* setup the PCI configuration registers */ pgt_cardbus_setup(csc); /* map and establish the interrupt handler */ csc->sc_ih = cardbus_intr_establish(cc, cf, csc->sc_intrline, IPL_NET, pgt_intr, sc, sc->sc_dev.dv_xname); if (csc->sc_ih == NULL) { printf("%s: could not establish interrupt at %d\n", sc->sc_dev.dv_xname, csc->sc_intrline); Cardbus_function_disable(ct); return (1); } return (0); }
int atw_cardbus_enable(struct atw_softc *sc) { struct atw_cardbus_softc *csc = (void *) sc; cardbus_devfunc_t ct = csc->sc_ct; cardbus_chipset_tag_t cc = ct->ct_cc; cardbus_function_tag_t cf = ct->ct_cf; /* * Power on the socket. */ Cardbus_function_enable(ct); /* * Set up the PCI configuration registers. */ atw_cardbus_setup(csc); /* * Map and establish the interrupt. */ csc->sc_ih = cardbus_intr_establish(cc, cf, csc->sc_intrline, IPL_NET, atw_intr, sc, sc->sc_dev.dv_xname); if (csc->sc_ih == NULL) { printf("%s: unable to establish interrupt at %d\n", sc->sc_dev.dv_xname, csc->sc_intrline); Cardbus_function_disable(csc->sc_ct); return (1); } return (0); }
int ral_cardbus_enable(struct rt2560_softc *sc) { struct ral_cardbus_softc *csc = (struct ral_cardbus_softc *)sc; cardbus_devfunc_t ct = csc->sc_ct; cardbus_chipset_tag_t cc = ct->ct_cc; cardbus_function_tag_t cf = ct->ct_cf; /* power on the socket */ Cardbus_function_enable(ct); /* setup the PCI configuration registers */ ral_cardbus_setup(csc); /* map and establish the interrupt handler */ csc->sc_ih = cardbus_intr_establish(cc, cf, csc->sc_intrline, IPL_NET, csc->sc_opns->intr, sc); if (csc->sc_ih == NULL) { aprint_error_dev(&sc->sc_dev, "could not establish interrupt\n"); Cardbus_function_disable(ct); return 1; } return 0; }
/* * Attach the interface. Allocate softc structures, do ifmedia * setup and ethernet/BPF attach. */ void re_cardbus_attach(struct device *parent, struct device *self, void *aux) { struct re_cardbus_softc *csc = (struct re_cardbus_softc *)self; struct rl_softc *sc = &csc->sc_rl; struct cardbus_attach_args *ca = aux; struct cardbus_softc *psc = (struct cardbus_softc *)sc->sc_dev.dv_parent; cardbus_chipset_tag_t cc = psc->sc_cc; cardbus_function_tag_t cf = psc->sc_cf; cardbus_devfunc_t ct = ca->ca_ct; bus_addr_t adr; char intrstr[16]; sc->sc_dmat = ca->ca_dmat; csc->ct = ct; csc->sc_tag = ca->ca_tag; csc->sc_pc = ca->ca_pc; csc->sc_intrline = ca->ca_intrline; /* * Map control/status registers. */ if (Cardbus_mapreg_map(ct, RL_PCI_LOMEM, PCI_MAPREG_TYPE_MEM, 0, &sc->rl_btag, &sc->rl_bhandle, &adr, &csc->sc_mapsize) == 0) { csc->sc_cben = CARDBUS_MEM_ENABLE; csc->sc_csr |= PCI_COMMAND_MEM_ENABLE; csc->sc_bar_reg = RL_PCI_LOMEM; csc->sc_bar_val = adr | PCI_MAPREG_TYPE_MEM; } else { printf(": can't map mem space\n"); return; } /* Enable power */ Cardbus_function_enable(ct); /* Get chip out of powersave mode (if applicable), initialize * config registers */ re_cardbus_setup(sc); /* Allocate interrupt */ csc->sc_ih = cardbus_intr_establish(cc, cf, csc->sc_intrline, IPL_NET, re_intr, sc, sc->sc_dev.dv_xname); if (csc->sc_ih == NULL) { printf(": couldn't establish interrupt at %d", ca->ca_intrline); Cardbus_function_disable(csc->ct); return; } snprintf(intrstr, sizeof(intrstr), "irq %d", ca->ca_intrline); /* Call bus-independent (common) attach routine */ if (re_attach(sc, intrstr)) { cardbus_intr_disestablish(ct->ct_cc, ct->ct_cf, csc->sc_ih); Cardbus_mapreg_unmap(ct, csc->sc_bar_reg, sc->rl_btag, sc->rl_bhandle, csc->sc_mapsize); } }
void * puc_cardbus_intr_establish(struct puc_attach_args *paa, int type, int (*func)(void *), void *arg, char *name) { struct puc_cardbus_softc *sc = paa->puc; struct puc_softc *psc = &sc->sc_psc; struct cardbus_devfunc *ct = sc->ct; psc->sc_ports[paa->port].intrhand = cardbus_intr_establish(ct->ct_cc, ct->ct_cf, sc->intrline, type, func, arg, name); return (psc->sc_ports[paa->port].intrhand); }
static bool ath_cardbus_resume(device_t self PMF_FN_ARGS) { struct ath_cardbus_softc *csc = device_private(self); csc->sc_ih = cardbus_intr_establish(csc->sc_ct->ct_cc, csc->sc_ct->ct_cf, csc->sc_intrline, IPL_NET, ath_intr, &csc->sc_ath); if (csc->sc_ih == NULL) { aprint_error_dev(self, "unable to establish interrupt\n"); return false; } return ath_resume(&csc->sc_ath); }
int ex_cardbus_enable(struct ex_softc *sc) { struct ex_cardbus_softc *csc = (struct ex_cardbus_softc *)sc; cardbus_function_tag_t cf = csc->sc_ct->ct_cf; cardbus_chipset_tag_t cc = csc->sc_ct->ct_cc; Cardbus_function_enable(csc->sc_ct); ex_cardbus_setup(csc); sc->sc_ih = cardbus_intr_establish(cc, cf, csc->sc_intrline, IPL_NET, ex_intr, sc); if (NULL == sc->sc_ih) { aprint_error_dev(sc->sc_dev, "couldn't establish interrupt\n"); return (1); } return (0); }
static int fxp_cardbus_enable(struct fxp_softc * sc) { struct fxp_cardbus_softc *csc = (struct fxp_cardbus_softc *)sc; struct cardbus_softc *psc = device_private(device_parent(sc->sc_dev)); cardbus_chipset_tag_t cc = psc->sc_cc; cardbus_function_tag_t cf = psc->sc_cf; Cardbus_function_enable(csc->ct); fxp_cardbus_setup(sc); /* Map and establish the interrupt. */ sc->sc_ih = cardbus_intr_establish(cc, cf, psc->sc_intrline, IPL_NET, fxp_intr, sc); if (NULL == sc->sc_ih) { aprint_error_dev(sc->sc_dev, "couldn't establish interrupt\n"); return 1; } return 0; }
void dc_cardbus_attach(struct device *parent, struct device *self, void *aux) { struct dc_cardbus_softc *csc = (struct dc_cardbus_softc *)self; struct dc_softc *sc = &csc->sc_dc; struct cardbus_attach_args *ca = aux; struct cardbus_devfunc *ct = ca->ca_ct; cardbus_chipset_tag_t cc = ct->ct_cc; pci_chipset_tag_t pc = ca->ca_pc; cardbus_function_tag_t cf = ct->ct_cf; pcireg_t reg; bus_addr_t addr; sc->sc_dmat = ca->ca_dmat; csc->sc_ct = ct; csc->sc_tag = ca->ca_tag; csc->sc_pc = ca->ca_pc; Cardbus_function_enable(ct); if (Cardbus_mapreg_map(ct, PCI_CBIO, PCI_MAPREG_TYPE_IO, 0, &sc->dc_btag, &sc->dc_bhandle, &addr, &csc->sc_mapsize) == 0) { csc->sc_actype = CARDBUS_IO_ENABLE; } else if (Cardbus_mapreg_map(ct, PCI_CBMEM, PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, &sc->dc_btag, &sc->dc_bhandle, &addr, &csc->sc_mapsize) == 0) { csc->sc_actype = CARDBUS_MEM_ENABLE; } else { printf(": can't map device registers\n"); return; } csc->sc_intrline = ca->ca_intrline; sc->dc_cachesize = pci_conf_read(csc->sc_pc, ca->ca_tag, DC_PCI_CFLT) & 0xFF; dc_cardbus_setup(csc); /* Get the eeprom width */ if ((PCI_VENDOR(ca->ca_id) == PCI_VENDOR_XIRCOM && PCI_PRODUCT(ca->ca_id) == PCI_PRODUCT_XIRCOM_X3201_3_21143)) ; /* XIRCOM has non-standard eeprom */ else dc_eeprom_width(sc); switch (PCI_VENDOR(ca->ca_id)) { case PCI_VENDOR_DEC: if (PCI_PRODUCT(ca->ca_id) == PCI_PRODUCT_DEC_21142) { sc->dc_type = DC_TYPE_21143; sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; sc->dc_flags |= DC_REDUCED_MII_POLL; dc_read_srom(sc, sc->dc_romwidth); dc_parse_21143_srom(sc); } break; case PCI_VENDOR_XIRCOM: if (PCI_PRODUCT(ca->ca_id) == PCI_PRODUCT_XIRCOM_X3201_3_21143) { sc->dc_type = DC_TYPE_XIRCOM; sc->dc_flags |= DC_TX_INTR_ALWAYS|DC_TX_COALESCE | DC_TX_ALIGN; sc->dc_pmode = DC_PMODE_MII; } break; case PCI_VENDOR_ADMTEK: case PCI_VENDOR_ACCTON: case PCI_VENDOR_ABOCOM: case PCI_VENDOR_DLINK: case PCI_VENDOR_LINKSYS: case PCI_VENDOR_HAWKING: case PCI_VENDOR_MICROSOFT: if (PCI_PRODUCT(ca->ca_id) == PCI_PRODUCT_ADMTEK_AN985 || PCI_PRODUCT(ca->ca_id) == PCI_PRODUCT_ACCTON_EN2242 || PCI_PRODUCT(ca->ca_id) == PCI_PRODUCT_ABOCOM_FE2500 || PCI_PRODUCT(ca->ca_id) == PCI_PRODUCT_ABOCOM_FE2500MX || PCI_PRODUCT(ca->ca_id) == PCI_PRODUCT_ABOCOM_PCM200 || PCI_PRODUCT(ca->ca_id) == PCI_PRODUCT_DLINK_DRP32TXD || PCI_PRODUCT(ca->ca_id) == PCI_PRODUCT_LINKSYS_PCMPC200 || PCI_PRODUCT(ca->ca_id) == PCI_PRODUCT_LINKSYS_PCM200 || PCI_PRODUCT(ca->ca_id) == PCI_PRODUCT_HAWKING_PN672TX || PCI_PRODUCT(ca->ca_id) == PCI_PRODUCT_MICROSOFT_MN120) { sc->dc_type = DC_TYPE_AN983; sc->dc_flags |= DC_TX_USE_TX_INTR|DC_TX_ADMTEK_WAR | DC_64BIT_HASH; sc->dc_pmode = DC_PMODE_MII; /* Don't read SROM for - auto-loaded on reset */ } break; default: printf(": unknown device\n"); return; } /* * set latency timer, do we really need this? */ reg = pci_conf_read(pc, ca->ca_tag, PCI_BHLC_REG); if (PCI_LATTIMER(reg) < 0x20) { reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); reg |= (0x20 << PCI_LATTIMER_SHIFT); pci_conf_write(pc, ca->ca_tag, PCI_BHLC_REG, reg); } sc->sc_ih = cardbus_intr_establish(cc, cf, ca->ca_intrline, IPL_NET, dc_intr, csc, sc->sc_dev.dv_xname); if (sc->sc_ih == NULL) { printf(": can't establish interrupt at %d\n", ca->ca_intrline); return; } printf(": irq %d", ca->ca_intrline); dc_reset(sc); sc->dc_revision = PCI_REVISION(ca->ca_class); dc_attach(sc); }
void uhci_cardbus_attach(struct device *parent, struct device *self, void *aux) { struct uhci_cardbus_softc *sc = (struct uhci_cardbus_softc *)self; struct cardbus_attach_args *ca = aux; cardbus_devfunc_t ct = ca->ca_ct; cardbus_chipset_tag_t cc = ct->ct_cc; cardbus_function_tag_t cf = ct->ct_cf; cardbusreg_t csr; char devinfo[256]; usbd_status r; const char *vendor; const char *devname = sc->sc.sc_bus.bdev.dv_xname; cardbus_devinfo(ca->ca_id, ca->ca_class, 0, devinfo, sizeof(devinfo)); printf(" %s", devinfo); /* Map I/O registers */ if (Cardbus_mapreg_map(ct, PCI_CBIO, CARDBUS_MAPREG_TYPE_IO, 0, &sc->sc.iot, &sc->sc.ioh, NULL, &sc->sc.sc_size)) { printf("%s: can't map io space\n", devname); return; } /* Disable interrupts, so we don't get any spurious ones. */ bus_space_write_2(sc->sc.iot, sc->sc.ioh, UHCI_INTR, 0); sc->sc_cc = cc; sc->sc_cf = cf; sc->sc_ct = ct; sc->sc.sc_bus.dmatag = ca->ca_dmat; (ct->ct_cf->cardbus_ctrl)(cc, CARDBUS_IO_ENABLE); (ct->ct_cf->cardbus_ctrl)(cc, CARDBUS_BM_ENABLE); /* Enable the device. */ csr = cardbus_conf_read(cc, cf, ca->ca_tag, CARDBUS_COMMAND_STATUS_REG); cardbus_conf_write(cc, cf, ca->ca_tag, CARDBUS_COMMAND_STATUS_REG, csr | CARDBUS_COMMAND_MASTER_ENABLE | CARDBUS_COMMAND_IO_ENABLE); sc->sc_ih = cardbus_intr_establish(cc, cf, ca->ca_intrline, IPL_USB, uhci_intr, sc, devname); if (sc->sc_ih == NULL) { printf("%s: couldn't establish interrupt\n", devname); return; } printf(": irq %d\n", ca->ca_intrline); /* Set LEGSUP register to its default value. */ cardbus_conf_write(cc, cf, ca->ca_tag, PCI_LEGSUP, PCI_LEGSUP_USBPIRQDEN); switch(cardbus_conf_read(cc, cf, ca->ca_tag, PCI_USBREV) & PCI_USBREV_MASK) { case PCI_USBREV_PRE_1_0: sc->sc.sc_bus.usbrev = USBREV_PRE_1_0; break; case PCI_USBREV_1_0: sc->sc.sc_bus.usbrev = USBREV_1_0; break; case PCI_USBREV_1_1: sc->sc.sc_bus.usbrev = USBREV_1_1; break; default: sc->sc.sc_bus.usbrev = USBREV_UNKNOWN; break; } uhci_run(&sc->sc, 0); /* stop the controller */ /* disable interrupts */ bus_space_barrier(sc->sc.iot, sc->sc.ioh, 0, sc->sc.sc_size, BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE); bus_space_write_2(sc->sc.iot, sc->sc.ioh, UHCI_INTR, 0); /* Figure out vendor for root hub descriptor. */ vendor = cardbus_findvendor(ca->ca_id); sc->sc.sc_id_vendor = CARDBUS_VENDOR(ca->ca_id); if (vendor) strlcpy(sc->sc.sc_vendor, vendor, sizeof (sc->sc.sc_vendor)); else snprintf(sc->sc.sc_vendor, sizeof(sc->sc.sc_vendor), "vendor 0x%04x", CARDBUS_VENDOR(ca->ca_id)); r = uhci_init(&sc->sc); if (r != USBD_NORMAL_COMPLETION) { printf("%s: init failed, error=%d\n", devname, r); bus_space_unmap(sc->sc.iot, sc->sc.ioh, sc->sc.sc_size); return; } /* Attach usb device. */ sc->sc.sc_child = config_found((void *)sc, &sc->sc.sc_bus, usbctlprint); }
void adv_cardbus_attach(struct device *parent, struct device *self, void *aux) { struct cardbus_attach_args *ca = aux; struct adv_cardbus_softc *csc = device_private(self); struct asc_softc *sc = &csc->sc_adv; cardbus_devfunc_t ct = ca->ca_ct; cardbus_chipset_tag_t cc = ct->ct_cc; cardbus_function_tag_t cf = ct->ct_cf; bus_space_tag_t iot; bus_space_handle_t ioh; pcireg_t reg; u_int8_t latency = 0x20; sc->sc_flags = 0; if (PCI_VENDOR(ca->ca_id) == PCI_VENDOR_ADVSYS) { switch (PCI_PRODUCT(ca->ca_id)) { case PCI_PRODUCT_ADVSYS_1200A: printf(": AdvanSys ASC1200A SCSI adapter\n"); latency = 0; break; case PCI_PRODUCT_ADVSYS_1200B: printf(": AdvanSys ASC1200B SCSI adapter\n"); latency = 0; break; case PCI_PRODUCT_ADVSYS_ULTRA: switch (PCI_REVISION(ca->ca_class)) { case ASC_PCI_REVISION_3050: printf(": AdvanSys ABP-9xxUA SCSI adapter\n"); break; case ASC_PCI_REVISION_3150: printf(": AdvanSys ABP-9xxU SCSI adapter\n"); break; } break; default: printf(": unknown model!\n"); return; } } csc->sc_ct = ct; csc->sc_tag = ca->ca_tag; csc->sc_intrline = ca->ca_intrline; csc->sc_cbenable = 0; /* * Map the device. */ csc->sc_csr = PCI_COMMAND_MASTER_ENABLE; #ifdef ADV_CARDBUS_ALLOW_MEMIO if (Cardbus_mapreg_map(csc->sc_ct, ADV_CARDBUS_MMBA, PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, &iot, &ioh, NULL, &csc->sc_size) == 0) { #ifdef ADV_CARDBUS_DEBUG printf("%s: memio enabled\n", DEVNAME(sc)); #endif csc->sc_cbenable = CARDBUS_MEM_ENABLE; csc->sc_csr |= PCI_COMMAND_MEM_ENABLE; } else #endif if (Cardbus_mapreg_map(csc->sc_ct, ADV_CARDBUS_IOBA, PCI_MAPREG_TYPE_IO, 0, &iot, &ioh, NULL, &csc->sc_size) == 0) { #ifdef ADV_CARDBUS_DEBUG printf("%s: io enabled\n", DEVNAME(sc)); #endif csc->sc_cbenable = CARDBUS_IO_ENABLE; csc->sc_csr |= PCI_COMMAND_IO_ENABLE; } else { aprint_error_dev(&sc->sc_dev, "unable to map device registers\n"); return; } /* Make sure the right access type is on the CardBus bridge. */ (*ct->ct_cf->cardbus_ctrl)(cc, csc->sc_cbenable); (*ct->ct_cf->cardbus_ctrl)(cc, CARDBUS_BM_ENABLE); /* Enable the appropriate bits in the PCI CSR. */ reg = cardbus_conf_read(cc, cf, ca->ca_tag, PCI_COMMAND_STATUS_REG); reg &= ~(PCI_COMMAND_IO_ENABLE|PCI_COMMAND_MEM_ENABLE); reg |= csc->sc_csr; cardbus_conf_write(cc, cf, ca->ca_tag, PCI_COMMAND_STATUS_REG, reg); /* * Make sure the latency timer is set to some reasonable * value. */ reg = cardbus_conf_read(cc, cf, ca->ca_tag, PCI_BHLC_REG); if (PCI_LATTIMER(reg) < latency) { reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); reg |= (latency << PCI_LATTIMER_SHIFT); cardbus_conf_write(cc, cf, ca->ca_tag, PCI_BHLC_REG, reg); } ASC_SET_CHIP_CONTROL(iot, ioh, ASC_CC_HALT); ASC_SET_CHIP_STATUS(iot, ioh, 0); sc->sc_iot = iot; sc->sc_ioh = ioh; sc->sc_dmat = ca->ca_dmat; sc->pci_device_id = ca->ca_id; sc->bus_type = ASC_IS_PCI; sc->chip_version = ASC_GET_CHIP_VER_NO(iot, ioh); /* * Initialize the board */ if (adv_init(sc)) { printf("adv_init failed\n"); return; } /* * Establish the interrupt. */ sc->sc_ih = cardbus_intr_establish(cc, cf, ca->ca_intrline, IPL_BIO, adv_intr, sc); if (sc->sc_ih == NULL) { aprint_error_dev(&sc->sc_dev, "unable to establish interrupt\n"); return; } /* * Attach. */ adv_attach(sc); }
static void uhci_cardbus_attach(device_t parent, device_t self, void *aux) { struct uhci_cardbus_softc *sc = device_private(self); struct cardbus_attach_args *ca = (struct cardbus_attach_args *)aux; cardbus_devfunc_t ct = ca->ca_ct; cardbus_chipset_tag_t cc = ct->ct_cc; cardbus_function_tag_t cf = ct->ct_cf; cardbustag_t tag = ca->ca_tag; cardbusreg_t csr; const char *vendor; const char *devname = device_xname(self); char devinfo[256]; usbd_status r; sc->sc.sc_dev = self; sc->sc.sc_bus.hci_private = sc; cardbus_devinfo(ca->ca_id, ca->ca_class, 0, devinfo, sizeof(devinfo)); printf(": %s (rev. 0x%02x)\n", devinfo, CARDBUS_REVISION(ca->ca_class)); /* Map I/O registers */ if (Cardbus_mapreg_map(ct, CARDBUS_CBIO, CARDBUS_MAPREG_TYPE_IO, 0, &sc->sc.iot, &sc->sc.ioh, NULL, &sc->sc.sc_size)) { printf("%s: can't map i/o space\n", devname); return; } sc->sc_cc = cc; sc->sc_cf = cf; sc->sc_ct = ct; sc->sc_tag = tag; sc->sc.sc_bus.dmatag = ca->ca_dmat; #if rbus #else XXX (ct->ct_cf->cardbus_io_open)(cc, 0, iob, iob + 0x40); #endif (ct->ct_cf->cardbus_ctrl)(cc, CARDBUS_IO_ENABLE); (ct->ct_cf->cardbus_ctrl)(cc, CARDBUS_BM_ENABLE); /* Enable the device. */ csr = cardbus_conf_read(cc, cf, tag, CARDBUS_COMMAND_STATUS_REG); cardbus_conf_write(cc, cf, tag, CARDBUS_COMMAND_STATUS_REG, csr | CARDBUS_COMMAND_MASTER_ENABLE | CARDBUS_COMMAND_IO_ENABLE); /* Disable interrupts, so we don't get any spurious ones. */ bus_space_write_2(sc->sc.iot, sc->sc.ioh, UHCI_INTR, 0); /* Map and establish the interrupt. */ sc->sc_ih = cardbus_intr_establish(cc, cf, ca->ca_intrline, IPL_USB, uhci_intr, sc); if (sc->sc_ih == NULL) { printf("%s: couldn't establish interrupt\n", devname); return; } /* Set LEGSUP register to its default value. */ cardbus_conf_write(cc, cf, tag, PCI_LEGSUP, PCI_LEGSUP_USBPIRQDEN); switch(cardbus_conf_read(cc, cf, tag, PCI_USBREV) & PCI_USBREV_MASK) { case PCI_USBREV_PRE_1_0: sc->sc.sc_bus.usbrev = USBREV_PRE_1_0; break; case PCI_USBREV_1_0: sc->sc.sc_bus.usbrev = USBREV_1_0; break; case PCI_USBREV_1_1: sc->sc.sc_bus.usbrev = USBREV_1_1; break; default: sc->sc.sc_bus.usbrev = USBREV_UNKNOWN; break; } /* Figure out vendor for root hub descriptor. */ vendor = cardbus_findvendor(ca->ca_id); sc->sc.sc_id_vendor = CARDBUS_VENDOR(ca->ca_id); if (vendor) strlcpy(sc->sc.sc_vendor, vendor, sizeof(sc->sc.sc_vendor)); else snprintf(sc->sc.sc_vendor, sizeof(sc->sc.sc_vendor), "vendor 0x%04x", CARDBUS_VENDOR(ca->ca_id)); r = uhci_init(&sc->sc); if (r != USBD_NORMAL_COMPLETION) { printf("%s: init failed, error=%d\n", devname, r); /* Avoid spurious interrupts. */ cardbus_intr_disestablish(sc->sc_cc, sc->sc_cf, sc->sc_ih); sc->sc_ih = NULL; return; } #if NEHCI_CARDBUS > 0 usb_cardbus_add(&sc->sc_cardbus, ca, self); #endif /* Attach usb device. */ sc->sc.sc_child = config_found(self, &sc->sc.sc_bus, usbctlprint); }
void ehci_cardbus_attach(struct device *parent, struct device *self, void *aux) { struct ehci_cardbus_softc *sc = (struct ehci_cardbus_softc *)self; struct cardbus_attach_args *ca = aux; cardbus_devfunc_t ct = ca->ca_ct; cardbus_chipset_tag_t cc = ct->ct_cc; pci_chipset_tag_t pc = ca->ca_pc; cardbus_function_tag_t cf = ct->ct_cf; pcireg_t csr; usbd_status r; const char *vendor; const char *devname = sc->sc.sc_bus.bdev.dv_xname; /* Map I/O registers */ if (Cardbus_mapreg_map(ct, CARDBUS_CBMEM, PCI_MAPREG_TYPE_MEM, 0, &sc->sc.iot, &sc->sc.ioh, NULL, &sc->sc.sc_size)) { printf(": can't map mem space\n"); return; } sc->sc_cc = cc; sc->sc_cf = cf; sc->sc_ct = ct; sc->sc.sc_bus.dmatag = ca->ca_dmat; (ct->ct_cf->cardbus_ctrl)(cc, CARDBUS_MEM_ENABLE); (ct->ct_cf->cardbus_ctrl)(cc, CARDBUS_BM_ENABLE); /* Enable the device. */ csr = pci_conf_read(pc, ca->ca_tag, PCI_COMMAND_STATUS_REG); pci_conf_write(pc, ca->ca_tag, PCI_COMMAND_STATUS_REG, csr | PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_MEM_ENABLE); /* Disable interrupts, so we don't get any spurious ones. */ sc->sc.sc_offs = EREAD1(&sc->sc, EHCI_CAPLENGTH); EOWRITE2(&sc->sc, EHCI_USBINTR, 0); sc->sc_ih = cardbus_intr_establish(cc, cf, ca->ca_intrline, IPL_USB, ehci_intr, sc, devname); if (sc->sc_ih == NULL) { printf(": unable to establish interrupt\n"); return; } printf(": irq %d\n", ca->ca_intrline); /* Figure out vendor for root hub descriptor. */ vendor = cardbus_findvendor(ca->ca_id); sc->sc.sc_id_vendor = PCI_VENDOR(ca->ca_id); if (vendor) strlcpy(sc->sc.sc_vendor, vendor, sizeof(sc->sc.sc_vendor)); else snprintf(sc->sc.sc_vendor, sizeof(sc->sc.sc_vendor), "vendor 0x%04x", PCI_VENDOR(ca->ca_id)); r = ehci_init(&sc->sc); if (r != USBD_NORMAL_COMPLETION) { printf("%s: init failed, error=%d\n", devname, r); /* Avoid spurious interrupts. */ cardbus_intr_disestablish(sc->sc_cc, sc->sc_cf, sc->sc_ih); sc->sc_ih = NULL; return; } /* Attach usb device. */ config_found(self, &sc->sc.sc_bus, usbctlprint); }
static void njs_cardbus_attach(struct device *parent, struct device *self, void *aux) { struct cardbus_attach_args *ca = aux; struct njsc32_cardbus_softc *csc = (void *) self; struct njsc32_softc *sc = &csc->sc_njsc32; const struct njsc32_cardbus_product *prod; cardbus_devfunc_t ct = ca->ca_ct; cardbus_chipset_tag_t cc = ct->ct_cc; cardbus_function_tag_t cf = ct->ct_cf; pcireg_t reg; int csr; u_int8_t latency = 0x20; if ((prod = njs_cardbus_lookup(ca)) == NULL) panic("njs_cardbus_attach"); printf(": Workbit NinjaSCSI-32 SCSI adapter\n"); sc->sc_model = prod->p_model; sc->sc_clk = prod->p_clk; csc->sc_ct = ct; csc->sc_tag = ca->ca_tag; csc->sc_intrline = ca->ca_intrline; /* * Map the device. */ csr = PCI_COMMAND_MASTER_ENABLE; /* * Map registers. * Try memory map first, and then try I/O. */ if (Cardbus_mapreg_map(csc->sc_ct, NJSC32_CARDBUS_BASEADDR_MEM, PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, &sc->sc_regt, &csc->sc_regmaph, NULL, &csc->sc_regmap_size) == 0) { if (bus_space_subregion(sc->sc_regt, csc->sc_regmaph, NJSC32_MEMOFFSET_REG, NJSC32_REGSIZE, &sc->sc_regh) != 0) { /* failed -- undo map and try I/O */ Cardbus_mapreg_unmap(csc->sc_ct, NJSC32_CARDBUS_BASEADDR_MEM, sc->sc_regt, csc->sc_regmaph, csc->sc_regmap_size); goto try_io; } #ifdef NJSC32_DEBUG printf("%s: memory space mapped\n", sc->sc_dev.dv_xname); #endif csr |= PCI_COMMAND_MEM_ENABLE; sc->sc_flags = NJSC32_MEM_MAPPED; (*ct->ct_cf->cardbus_ctrl)(cc, CARDBUS_MEM_ENABLE); } else { try_io: if (Cardbus_mapreg_map(csc->sc_ct, NJSC32_CARDBUS_BASEADDR_IO, PCI_MAPREG_TYPE_IO, 0, &sc->sc_regt, &sc->sc_regh, NULL, &csc->sc_regmap_size) == 0) { #ifdef NJSC32_DEBUG printf("%s: io space mapped\n", sc->sc_dev.dv_xname); #endif csr |= PCI_COMMAND_IO_ENABLE; sc->sc_flags = NJSC32_IO_MAPPED; (*ct->ct_cf->cardbus_ctrl)(cc, CARDBUS_IO_ENABLE); } else { printf("%s: unable to map device registers\n", sc->sc_dev.dv_xname); return; } } /* Make sure the right access type is on the CardBus bridge. */ (*ct->ct_cf->cardbus_ctrl)(cc, CARDBUS_BM_ENABLE); /* Enable the appropriate bits in the PCI CSR. */ reg = cardbus_conf_read(cc, cf, ca->ca_tag, PCI_COMMAND_STATUS_REG); reg &= ~(PCI_COMMAND_IO_ENABLE|PCI_COMMAND_MEM_ENABLE); reg |= csr; cardbus_conf_write(cc, cf, ca->ca_tag, PCI_COMMAND_STATUS_REG, reg); /* * Make sure the latency timer is set to some reasonable * value. */ reg = cardbus_conf_read(cc, cf, ca->ca_tag, CARDBUS_BHLC_REG); if (CARDBUS_LATTIMER(reg) < latency) { reg &= ~(CARDBUS_LATTIMER_MASK << CARDBUS_LATTIMER_SHIFT); reg |= (latency << CARDBUS_LATTIMER_SHIFT); cardbus_conf_write(cc, cf, ca->ca_tag, CARDBUS_BHLC_REG, reg); } sc->sc_dmat = ca->ca_dmat; /* * Establish the interrupt. */ sc->sc_ih = cardbus_intr_establish(cc, cf, ca->ca_intrline, IPL_BIO, njsc32_intr, sc); if (sc->sc_ih == NULL) { printf("%s: unable to establish interrupt at %d\n", sc->sc_dev.dv_xname, ca->ca_intrline); return; } printf("%s: interrupting at %d\n", sc->sc_dev.dv_xname, ca->ca_intrline); /* CardBus device cannot supply termination power. */ sc->sc_flags |= NJSC32_CANNOT_SUPPLY_TERMPWR; /* attach */ njsc32_attach(sc); }