void tx_irq_handle(void)
{
unsigned tx_status = aocec_rd_reg(CEC_TX_MSG_STATUS);
switch (tx_status)
{
case TX_DONE:
aocec_wr_reg(CEC_TX_MSG_CMD, TX_NO_OP);
break;
case TX_BUSY:
aocec_wr_reg(CEC_TX_MSG_CMD, TX_ABORT);
aocec_wr_reg(CEC_TX_MSG_CMD, TX_NO_OP);
break;
case TX_ERROR:
if (cec_msg_dbg_en == 1)
hdmi_print(INF, CEC "TX ERROR!!!\n");
if (RX_ERROR == aocec_rd_reg(CEC_RX_MSG_STATUS))
{
cec_hw_reset();
}
else
{
aocec_wr_reg(CEC_TX_MSG_CMD, TX_NO_OP);
}
//aocec_wr_reg(CEC_TX_MSG_CMD, TX_NO_OP);
break;
default:
break;
}
aml_write_reg32(P_AO_CEC_INTR_CLR, aml_read_reg32(P_AO_CEC_INTR_CLR) | (1 << 1));
//aml_write_reg32(P_AO_CEC_INTR_MASKN, aml_read_reg32(P_AO_CEC_INTR_MASKN) | (1 << 2));
}
static int ao_cec_ll_rx( unsigned char *msg, unsigned char *len)
{
unsigned char i;
unsigned char data;
unsigned char n;
unsigned char *msg_start = msg;
unsigned int num;
int rx_msg_length;
int rx_status;
rx_status = aocec_rd_reg(CEC_RX_MSG_STATUS);
num = aocec_rd_reg(CEC_RX_NUM_MSG);
printk("rx irq:rx_status:0x%x:: num :0x%x\n", rx_status, num);
//aml_set_reg32_bits(P_AO_CEC_INTR_CLR, 1, 2, 1);
if(RX_DONE != rx_status){
printk("rx irq:!!!RX_DONE\n");
aocec_wr_reg(CEC_RX_MSG_CMD, RX_ACK_CURRENT);
aocec_wr_reg(CEC_RX_MSG_CMD, RX_NO_OP);
return -1;
}
if(1 != num){
printk("rx irq:!!!num\n");
//aocec_wr_reg(CEC_RX_MSG_CMD, RX_ACK_CURRENT);
//aocec_wr_reg(CEC_RX_MSG_CMD, RX_NO_OP);
aocec_wr_reg(CEC_RX_CLEAR_BUF, 1);
aml_set_reg32_bits(P_AO_CEC_INTR_CLR, 1, 2, 1);
return -1;
}
rx_msg_length = aocec_rd_reg(CEC_RX_MSG_LENGTH) + 1;
aocec_wr_reg(CEC_RX_MSG_CMD, RX_ACK_CURRENT);
for (i = 0; i < rx_msg_length && i < MAX_MSG; i++) {
data = aocec_rd_reg(CEC_RX_MSG_0_HEADER +i);
*msg = data;
msg++;
}
*len = rx_msg_length;
rx_status = aocec_rd_reg(CEC_RX_MSG_STATUS);
aocec_wr_reg(CEC_RX_MSG_CMD, RX_NO_OP);
//aocec_wr_reg(CEC_RX_CLEAR_BUF, 1);
aml_set_reg32_bits(P_AO_CEC_INTR_CLR, 1, 2, 1);
cec_hw_reset();
if(cec_msg_dbg_en == 1){
pos = 0;
pos += sprintf(msg_log_buf + pos, "CEC: rx msg len: %d dat: ", rx_msg_length);
for(n = 0; n < rx_msg_length; n++) {
pos += sprintf(msg_log_buf + pos, "%02x ", msg_start[n]);
}
pos += sprintf(msg_log_buf + pos, "\n");
msg_log_buf[pos] = '\0';
hdmi_print(INF, CEC "%s", msg_log_buf);
}
return rx_status;
}
void tx_irq_handle(void){
unsigned tx_status = aocec_rd_reg(CEC_TX_MSG_STATUS);
switch(tx_status){
case TX_DONE:
aocec_wr_reg(CEC_TX_MSG_CMD, TX_NO_OP);
break;
case TX_BUSY:
aocec_wr_reg(CEC_TX_MSG_CMD, TX_ABORT);
aocec_wr_reg(CEC_TX_MSG_CMD, TX_NO_OP);
break;
case TX_ERROR:
cec_hw_reset();
//aocec_wr_reg(CEC_TX_MSG_CMD, TX_NO_OP);
break;
default:
break;
}
aml_write_reg32(P_AO_CEC_INTR_CLR, aml_read_reg32(P_AO_CEC_INTR_CLR) | (1 << 1));
//aml_write_reg32(P_AO_CEC_INTR_MASKN, aml_read_reg32(P_AO_CEC_INTR_MASKN) | (1 << 2));
}
static void ao_cec_tx_irq_handle(void)
{
unsigned tx_status = aocec_rd_reg(CEC_TX_MSG_STATUS);
printk("tx_status:0x%x\n", tx_status);
switch(tx_status){
case TX_DONE:
aocec_wr_reg(CEC_TX_MSG_CMD, TX_NO_OP);
break;
case TX_BUSY:
aocec_wr_reg(CEC_TX_MSG_CMD, TX_ABORT);
aocec_wr_reg(CEC_TX_MSG_CMD, TX_NO_OP);
break;
case TX_ERROR:
cec_hw_reset();
//aocec_wr_reg(CEC_TX_MSG_CMD, TX_ABORT);
//aocec_wr_reg(CEC_TX_MSG_CMD, TX_NO_OP);
break;
default:
break;
}
aml_set_reg32_bits(P_AO_CEC_INTR_CLR, 1, 1, 1);
}
