/*
* Search interrupt stack for a valid frame.
*/
struct frame *
checkintstack(fcor)
{
char stack[NISP*NBPG];
off_t off = vtophys(intstack);
struct frame *fp;
register caddr_t addr;
if (off == -1 || lseek(fcor, off, L_SET) != off ||
read(fcor, stack, sizeof (stack)) != sizeof (stack))
return ((struct frame *)0);
addr = eintstack;
do {
addr -= sizeof (caddr_t);
fp = (struct frame *)&stack[addr - intstack];
} while (addr >= intstack + sizeof (struct frame) &&
!checkframe(fp));
return (addr < intstack+sizeof (struct frame) ? (struct frame *)0 : fp);
}
static int mipi_vdin_run(vdin_dev_t* devp,struct vframe_s *vf)
{
vdin_ops_privdata_t* data = (vdin_ops_privdata_t*)devp->priv_data;
data->watchdog_cnt = 0;
if (data->wr_canvas_index == 0xff) {
mipi_wr_vdin_canvas(data,0);
data->wr_canvas_index = 0;
return 0;
}
#ifdef TEST_FRAME_RATE
if(time_count==0){
mipi_error("[mipi_vdin]:mipi_vdin_run ---- time start\n");
}
time_count++;
if(time_count>49){
time_count = 0;
}
#endif
if(data->mipi_vdin_skip>0){
data->mipi_vdin_skip--;
vf->type = INVALID_VDIN_INPUT;
}else if(checkframe(data->wr_canvas_index,&data->input) == true){
mipi_send_buff_to_display_fifo(data,vf);
data->wr_canvas_index++;
}else{
vf->type = INVALID_VDIN_INPUT;
}
if (data->wr_canvas_index >= data->canvas_total_count)
data->wr_canvas_index = 0;
mipi_wr_vdin_canvas(data,data->wr_canvas_index);
//WRITE_CBUS_REG(CSI2_INTERRUPT_CTRL_STAT, (1 << CSI2_CFG_VS_FAIL_INTERRUPT_CLR) | (1 << CSI2_CFG_VS_FAIL_INTERRUPT));
// Clear error flag
WRITE_CBUS_REG(CSI2_ERR_STAT0, 0);
return 0;
}
