int arch_cpu_init(void) { chip_configuration_unlock(); icache_enable(); if (cpu_is_k2g()) { msmc_k2g_setup(); } else { msmc_k2hkle_common_setup(); if (cpu_is_k2e()) msmc_k2e_setup(); else if (cpu_is_k2l()) msmc_k2l_setup(); else msmc_k2hk_setup(); } /* Initialize the PCIe-0 to work as Root Complex */ config_pcie_mode(0, ROOTCOMPLEX); #if defined(CONFIG_SOC_K2E) || defined(CONFIG_SOC_K2L) /* Initialize the PCIe-1 to work as Root Complex */ config_pcie_mode(1, ROOTCOMPLEX); #endif #ifdef CONFIG_SOC_K2L osr_init(); #endif /* * just initialise the COM2 port so that TI specific * UART register PWREMU_MGMT is initialized. Linux UART * driver doesn't handle this. */ #ifndef CONFIG_DM_SERIAL NS16550_init((NS16550_t)(CONFIG_SYS_NS16550_COM2), CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE); #endif return 0; }
int arch_cpu_init(void) { chip_configuration_unlock(); icache_enable(); #ifdef CONFIG_SOC_K2HK share_all_segments(8); share_all_segments(9); share_all_segments(10); /* QM PDSP */ share_all_segments(11); /* PCIE */ #endif /* * just initialise the COM2 port so that TI specific * UART register PWREMU_MGMT is initialized. Linux UART * driver doesn't handle this. */ NS16550_init((NS16550_t)(CONFIG_SYS_NS16550_COM2), CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE); return 0; }