/* call it before pinmux init; call it before soft reset; */ void clearall_pinmux(void) { int i; for(i=0;i<13;i++) clear_mio_mux(i,0xffffffff); return; }
void board_nand_pinmux( unsigned int en_dis ) { // printf("TODO SET A3 board pinmux"); if(en_dis) set_mio_mux(4, (0x1<<11) | (0xff<<14)); else clear_mio_mux(4, (0x1<<11) | (0xff<<14)); return; }
static void save_pinmux(void) { int i; for (i=0;i<6;i++) pinmux_backup[i] = READ_CBUS_REG(PERIPHS_PIN_MUX_0+i); for (i=0;i<MAX_PINMUX;i++){ if (pinmux_data[i].enable){ printk("%s %x\n", pinmux_data[i].name, pinmux_data[i].bits); clear_mio_mux(pinmux_data[i].reg, pinmux_data[i].bits); } } }
static void set_tcon_pinmux(void) { debug("%s\n", __FUNCTION__); /* TCON control pins pinmux */ clear_mio_mux(1, 0x0f<<11); // disable cph50(11),cph1(12),cph2(13),cph3(14) #ifdef USE_CLKO set_mio_mux(1, 1<<21); // enable clko #else set_mio_mux(1, 1<<14); // enable cph1 #endif set_mio_mux(1, 1<<17); // enable oeh set_mio_mux(0, 0x3f<<0); //For 8bits RGB }
void power_off_backlight(void) { if(ver == 2) { clear_mio_mux(2, 1<<17); clear_mio_mux(4, 1<<12); clear_mio_mux(3, 1<<3); clear_mio_mux(7, 1<<20); clear_mio_mux(10, 1<<6); set_gpio_val(GPIOX_bank_bit32_63(53), GPIOX_bit_bit32_63(53), 1); set_gpio_mode(GPIOX_bank_bit32_63(53), GPIOX_bit_bit32_63(53), 0); } else { clear_mio_mux(10, 1<<13); clear_mio_mux(4, 1<<5); clear_mio_mux(0, 1<<1); set_gpio_val(GPIOB_bank_bit0_8(6), GPIOB_bit_bit0_8(6), 0); set_gpio_mode(GPIOB_bank_bit0_8(6), GPIOB_bit_bit0_8(6), GPIO_OUTPUT_MODE); } }
void power_hold(void) { //power hold //printf("power hold\n"); clear_mio_mux(12, 0x40); //disable ENC_6 clear_mio_mux(0, 0x100); //disable TCON_CPH3 clear_mio_mux(2, 0x40000000); //disable PWM_B clear_mio_mux(2, 0x10000000); //disable DEMOD_RF_PWM clear_mio_mux(0, 0x200000); //disable LED_BL_PWM clear_mio_mux(9, 0x800000); //disable WIFI Debug set_gpio_mode(GPIOA_bank_bit(8), GPIOA_bit_bit0_14(8), GPIO_OUTPUT_MODE); // OEN = 0 (output) set_gpio_val(GPIOA_bank_bit(8), GPIOA_bit_bit0_14(8), 1); // Output level = 1 (pull high) //*(volatile unsigned long *)(0xC1108030) &= ~(1 << 12); // OEN = 0 (output) //*(volatile unsigned long *)(0xC1108034) |= (1 << 12); // Output level = 1 (pull high) }
int aml_eth_clearall_pinmux(void) { clear_mio_mux(ETH_BANK0_REG1,ETH_BANK0_REG1_VAL); return 0; }
void power_on_backlight(void) { if(ver == 2) { clear_mio_mux(2, 1<<17); clear_mio_mux(4, 1<<12); clear_mio_mux(3, 1<<3); clear_mio_mux(7, 1<<20); clear_mio_mux(10, 1<<6); set_gpio_val(GPIOX_bank_bit32_63(53), GPIOX_bit_bit32_63(53), 0); set_gpio_mode(GPIOX_bank_bit32_63(53), GPIOX_bit_bit32_63(53), 0); } else { clear_mio_mux(10, 1<<13); clear_mio_mux(4, 1<<5); clear_mio_mux(0, 1<<1); set_gpio_val(GPIOB_bank_bit0_8(6), GPIOB_bit_bit0_8(6), 1); set_gpio_mode(GPIOB_bank_bit0_8(6), GPIOB_bit_bit0_8(6), GPIO_OUTPUT_MODE); } //Init Analog pwm pinmux CLEAR_CBUS_REG_MASK(PERIPHS_PIN_MUX_4, (1<<11)); CLEAR_CBUS_REG_MASK(PERIPHS_PIN_MUX_3, 1); CLEAR_CBUS_REG_MASK(PERIPHS_PIN_MUX_3, (1<<1)); CLEAR_CBUS_REG_MASK(PERIPHS_PIN_MUX_7, (1<<18)); CLEAR_CBUS_REG_MASK(PERIPHS_PIN_MUX_10, (1<<6)); SET_CBUS_REG_MASK(PERIPHS_PIN_MUX_1, (1<<24)); WRITE_CBUS_REG(PWM_MISC_REG_AB, 0x2); WRITE_CBUS_REG(PWM_PWM_B, 0); //Init Digital pwm pinmux, tcon GPIOB2, GPIOB3,GPIOB4 SET_CBUS_REG_MASK(PERIPHS_PIN_MUX_0, (1<<4)|(1<<5)|(1<<3)); WRITE_CBUS_REG_BITS(TCON_MISC_SEL_ADDR, 1, OEH_SEL, 1); WRITE_CBUS_REG(OEH_HS_ADDR, TCON_PWM_HS1); WRITE_CBUS_REG(OEH_HE_ADDR, TCON_PWM_HE1); WRITE_CBUS_REG(OEH_VS_ADDR, TCON_PWM_VS1); WRITE_CBUS_REG(OEH_VE_ADDR, TCON_PWM_VS2);//180HZ WRITE_CBUS_REG_BITS(TCON_MISC_SEL_ADDR, 1, CPV1_SEL, 1); WRITE_CBUS_REG(CPV1_HS_ADDR, TCON_PWM_HS2); WRITE_CBUS_REG(CPV1_HE_ADDR, TCON_PWM_HE2); WRITE_CBUS_REG(CPV1_VS_ADDR, TCON_PWM_VS2); WRITE_CBUS_REG(CPV1_VE_ADDR, TCON_PWM_VS2+TCON_PWM_VS2); WRITE_CBUS_REG_BITS(TCON_MISC_SEL_ADDR, 1, OEV2_SEL, 1); WRITE_CBUS_REG_BITS(TCON_MISC_SEL_ADDR, 1, OEV1_SEL, 1); WRITE_CBUS_REG_BITS(TCON_MISC_SEL_ADDR, 1, OEV3_SEL, 1); CLEAR_CBUS_REG_MASK(TCON_MISC_SEL_ADDR, 1<<OEV_UNITE); WRITE_CBUS_REG(OEV1_HS_ADDR, TCON_PWM_HS3); WRITE_CBUS_REG(OEV1_HE_ADDR, TCON_PWM_HE3); WRITE_CBUS_REG(OEV1_VS_ADDR, TCON_PWM_VS3); WRITE_CBUS_REG(OEV1_VE_ADDR, TCON_PWM_VS3+TCON_PWM_VS2); }
/* --------------------------------------------------------------------------*/ static void __init set_audio_codec_pinmux(void) { /* for gpiox_17~20 I2S_AMCLK I2S_AOCLK I2S_LRCLK I2S_OUT */ clear_mio_mux(7, (1 << 18) | (1 << 19) | (1 << 20) | (1 << 21) | (1 << 22) | (1 << 23)); set_mio_mux(8, (1 << 27) | (1 << 26) | (1 << 25) | (1 << 24)); }
static void __init device_pinmux_init(void ) { clearall_pinmux(); /*other deivce power on*/ /*GPIOA_200e_bit4..usb/eth/YUV power on*/ //set_gpio_mode(PREG_EGPIO,1<<4,GPIO_OUTPUT_MODE); //set_gpio_val(PREG_EGPIO,1<<4,1); //uart_set_pinmux(UART_PORT_A,PINMUX_UART_A); //uart_set_pinmux(UART_PORT_B,PINMUX_UART_B); /*pinmux of eth*/ eth_pinmux_init(); aml_i2c_init(); printk("SPDIF output.\n"); CLEAR_CBUS_REG_MASK(PERIPHS_PIN_MUX_0,(1<<19)); CLEAR_CBUS_REG_MASK(PERIPHS_PIN_MUX_3,(1<<25)); CLEAR_CBUS_REG_MASK(PERIPHS_PIN_MUX_7,(1<<17)); SET_CBUS_REG_MASK(PERIPHS_PIN_MUX_3, (1<<24)); // set_audio_pinmux(AUDIO_OUT_TEST_N); // set_audio_pinmux(AUDIO_IN_JTAG); #ifdef CONFIG_AM_MXL101 //for mxl101 //set_mio_mux(3, 0x3F); //clear_mio_mux(6, 0x1F<<19); set_mio_mux(3, 0x3F<<6); clear_mio_mux(0, 0xF); clear_mio_mux(5, 0x1<<23); clear_mio_mux(0, 1<<6); //pwr pin; clear_mio_mux(0, 1<<13); clear_mio_mux(1, 1<<8); //rst pin; clear_mio_mux(0, 1<<28); clear_mio_mux(1, 1<<20); /* set_mio_mux(3, 1<<0); set_mio_mux(3, 1<<1); set_mio_mux(3, 1<<2); set_mio_mux(3, 1<<3); set_mio_mux(3, 1<<4); clear_mio_mux(0, 1<<6);*/ #endif #ifdef CONFIG_AM_AVL6211 //for avl6211 printk("CONFIG_AM_AVL6211 set pinmux\n"); set_mio_mux(3, 0x3F<<6); // clear_mio_mux(0, 1<<4); clear_mio_mux(0, 0x7); #endif #ifdef CONFIG_AM_ITE9173 //for ite9173 printk("CONFIG_AM_ITE9173 set pinmux\n"); set_mio_mux(3, 0x3F<<6); // clear_mio_mux(0, 1<<4); clear_mio_mux(0, 0x7); #endif #ifdef CONFIG_AM_RTL2830 //for rtl2830 printk("CONFIG_AM_RTL2830 set pinmux\n"); set_mio_mux(3, 0x3F<<6); // clear_mio_mux(0, 1<<4); clear_mio_mux(0, 0x7); #endif #ifdef CONFIG_AM_DS3000 //for rtl2830 printk("CONFIG_AM_DS3000 set pinmux\n"); set_mio_mux(3, 0x3F<<6); // clear_mio_mux(0, 1<<4); clear_mio_mux(0, 0x7); #endif #ifdef CONFIG_TH_SONY_T2 //for rtl2830 printk("CONFIG_AM_DS3000 set pinmux\n"); set_mio_mux(3, 0x3F<<6); // clear_mio_mux(0, 1<<4); clear_mio_mux(0, 0x7); #endif #ifdef CONFIG_AM_ITE9133 //for ite9133 printk("CONFIG_AM_ITE9133 set pinmux\n"); set_mio_mux(3, 0xFFF<<6); // clear_mio_mux(0, 1<<4); clear_mio_mux(0, 0x3F); #endif #ifdef CONFIG_AM_DIB7090P printk("CONFIG_AM_DIB7090P set pinmux\n"); set_mio_mux(3, 0x3F<<6); clear_mio_mux(0, 0xF); clear_mio_mux(5, 0x1<<23); /* clear_mio_mux(0, 1<<6); //pwr pin; clear_mio_mux(0, 1<<13); clear_mio_mux(1, 1<<8); //rst pin; clear_mio_mux(0, 1<<28); clear_mio_mux(1, 1<<20);*/ #endif }
static int uVideoFmt_SetVideoType(control_t* cntl, cond_item_t* param) { int ret=0; uvideofmt_t* uvideofmt = (uvideofmt_t*)(cntl->private_data); int fmt = (int)(param[0]); int outputmode = (int)(param[1]); /* Add Method code here, Set ret to be -1 if fail */ int displayctl_fd, resolution_data; video_appmode_t video_appmode = { DISPCTL_MODE_1080P, 0, 0, 0, DISPCTL_MODE_1080P }; page_t *page = af_find_page(SYSTEM_DEFAULT_PAGE); if (this_curVideoFmt!=fmt || this_outputmode!= outputmode) { /* when NTSC/PAL CVBS output is enabled in first 3 video dacs, * enable pedestal. Component 480i has pedestal disabled. */ #ifdef AML_NIKE fmt = 6; #endif #ifndef EDGE_ADJUST set_display_edge_adjust(0,0,0,0); #endif af_osd_layer_destroy(OSD_LAYER_HW_LAYER0); switch(outputmode) { case 0://Analog clear_mio_mux(5, (1<<0) | (1<<2) | (1<<3) | (1<<4) | (1<<7)); //disable RGB data //clear_mio_mux(4, (1<<20) | (1<<22) | (1<<24));//6bits clear_mio_mux(4, (0x3f<<20));//8bits #ifdef APOLLO_PMP_TVOUT clear_mio_mux(4, 0x7c000000); //disable hdmi output , #endif resolution_data = set_analog_output(fmt, &video_appmode); break; case 2://HDMI clear_mio_mux(5, (1<<0) | (1<<2) | (1<<3) | (1<<4) | (1<<7)); //disable RGB data //clear_mio_mux(4, (1<<20) | (1<<22) | (1<<24));//6bits clear_mio_mux(4, (0x3f<<20));//8bits resolution_data = set_hdmi_output(fmt, &video_appmode); set_mio_mux(4, 0x7c000000); //mux GPIOC_28 to hsync, mux GPIOC_29 to vsync, mux GPIOC_30 to DE, mux GPIOC_31 to pixel clock, mux GPIOC_32~GPIOC_55 to HDMI data lines, Codec_PowerDown_Entile_Codec(0); break; #if (defined APOLLO_PMP_LCD) || (defined NIKE_PMP_LCD) case 1://Panel #ifdef EDGE_ADJUST set_display_edge_adjust(0,0,0,0); #endif clear_mio_mux(4, 0x7c000000); //disable hdmi output , //enable Tcon //set_mio_mux(5, (1<<0) | (1<<2) | (1<<3) | (1<<4) | (1<<7) | (1<<8) | (1<<9)); set_mio_mux(5, (1<<0) | (1<<2) | (1<<3) | (1<<4) | (1<<7)); //enable RGB data //set_mio_mux(4, (1<<20) | (1<<22) | (1<<24));//6bits set_mio_mux(4, (0x3f<<20));//8bits resolution_data = set_lcd_output(fmt, &video_appmode); power_off_USBb(); break; #endif default: AVOS_printf("Please select the valid output mode!\n"); break; } GF_SetHdmode(cntl, &video_appmode.hdmode); af_set_current_resolution(resolution_data); af_init_osd(page); } this_curVideoFmt_Set(fmt); if(outputmode<=2&&outputmode>=0) { this_outputmode_Set(outputmode); } /////////////////////////////////////////// int video_fd; video_fd=open("/dev/video",O_RDONLY); //video_appmode_t video_appmode = {DISPCTL_MODE_480P, VIDEO_APPVMODE_480_480, VIDEO_APPHMODE_720, 0, DISPCTL_MODE_VGA}; video_appmode_t video_appmode2 = {DISPCTL_MODE_480P, VIDEO_APPVMODE_480_480, VIDEO_APPHMODE_720, 0, DISPCTL_MODE_VGA}; ioctl(video_fd, VIDEOIO_SETAPPMODE, &video_appmode2); WRITE_MPEG_REG(VENC_VDAC_SETTING,0); power_on_vdac(); /////////////////////////////////////////// AVTimeDly(100); /* end */ return ret; }